From 5030a56f57a8473f396b690aad21c93b0829da82 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 11:41:16 -0600 Subject: [PATCH 01/38] Optomized gshare. --- pipelined/src/ifu/brpred/speculativegshare.sv | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 05753c76d..eee2abc95 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -45,7 +45,7 @@ module speculativegshare input logic PCSrcE ); - logic MatchF, MatchD, MatchE, MatchM; + logic MatchF, MatchD, MatchE; logic MatchNextX, MatchXF; logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; @@ -57,7 +57,7 @@ module speculativegshare logic [k:-1] GHRNextD, OldGHRD; logic [k:0] GHRNextE, GHRNextM, GHRNextW; logic [k-1:0] IndexNextF, IndexF; - logic [k-1:0] IndexD, IndexE, IndexM; + logic [k-1:0] IndexD, IndexE; logic PCSrcM, PCSrcW; logic [`XLEN-1:0] PCW; @@ -68,15 +68,14 @@ module speculativegshare assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]}; assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]}; assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]}; - assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]}; ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF | reset), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(TableDirPredictionF), - .wa2(IndexM), - .wd2(NewDirPredictionM), - .we2(BranchInstrM & ~StallW & ~FlushW), + .wa2(IndexE), + .wd2(NewDirPredictionE), + .we2(BranchInstrE & ~StallM & ~FlushM), .bwe2(1'b1)); // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage @@ -84,15 +83,13 @@ module speculativegshare assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF); assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD); assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE); - assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM); - assign MatchNextX = MatchF | MatchD | MatchE | MatchM; + assign MatchNextX = MatchF | MatchD | MatchE; flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF : MatchD ? NewDirPredictionD : - MatchE ? NewDirPredictionE : - NewDirPredictionM; + NewDirPredictionE ; flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF); From a0bca35b5043c8f8e7cd6a11aca25187f1823714 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 12:05:13 -0600 Subject: [PATCH 02/38] BTB cleanup. --- pipelined/src/ifu/brpred/bpred.sv | 2 +- pipelined/src/ifu/brpred/btb.sv | 46 +++++++------------------------ 2 files changed, 11 insertions(+), 37 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 9c5efe306..6817dfd59 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -143,7 +143,7 @@ module bpred ( .InstrClass(PredInstrClassF), .Valid(BTBValidF), // update - .UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE), + .UpdateEN(|InstrClassE | PredictionInstrClassWrongE), .PCE, .IEUAdrE, .UpdateInvalid(PredictionInstrClassWrongE), diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index 5f725b83a..8eba026ec 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -35,7 +35,7 @@ module btb ) (input logic clk, input logic reset, - input logic StallF, StallE, + input logic StallF, StallE, StallM, FlushM, input logic [`XLEN-1:0] PCNextF, output logic [`XLEN-1:0] BTBPredPCF, output logic [3:0] InstrClass, @@ -50,7 +50,7 @@ module btb localparam TotalDepth = 2 ** Depth; logic [TotalDepth-1:0] ValidBits; - logic [Depth-1:0] PCNextFIndex, PCEIndex, PCNextFIndexQ, PCEIndexQ; + logic [Depth-1:0] PCNextFIndex, PCEIndex; logic UpdateENQ; logic [`XLEN-1:0] ResetPC; @@ -60,51 +60,25 @@ module btb // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if // using compressed instructions. XOR bit 1 with the MSB of index. assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]}; + + // must output a valid PC and valid bit during reset. Because the PCNextF logic of the IFU and trap units + // does not mux in RESET_VECTOR we have to do it here. This is a performance optimization. assign ResetPC = `RESET_VECTOR; assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; - //assign PCNextFIndex = {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; - - flopenr #(Depth) PCEIndexReg(.clk(clk), - .reset(reset), - .en(~StallE), - .d(PCEIndex), - .q(PCEIndexQ)); - // The valid bit must be resetable. always_ff @ (posedge clk) begin if (reset) begin ValidBits <= #1 {TotalDepth{1'b0}}; - end else - if (UpdateENQ) begin - ValidBits[PCEIndexQ] <= #1 ~ UpdateInvalid; + end else if (UpdateEN & ~StallM & ~FlushM) begin + ValidBits[PCEIndex] <= #1 ~ UpdateInvalid; end + Valid = ValidBits[PCNextFIndex]; end - assign Valid = ValidBits[PCNextFIndexQ]; - - flopenr #(1) UpdateENReg(.clk(clk), - .reset(reset), - .en(~StallF), - .d(UpdateEN), - .q(UpdateENQ)); - - - flopenr #(Depth) LookupPCIndexReg(.clk(clk), - .reset(reset), - .en(~StallF), - .d(PCNextFIndex), - .q(PCNextFIndexQ)); - - - - // the BTB contains the target address. - // Another optimization may be using a PC relative address. + // An optimization may be using a PC relative address. // *** need to add forwarding. - - // *** optimize for byte write enables - ram2p1r1wbe #(2**Depth, `XLEN+4) memory( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}), - .ce2(~StallE), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1)); + .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1)); endmodule From 85e015d61ec5717190176fbe8521881476258350 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 12:08:54 -0600 Subject: [PATCH 03/38] Found minor bug in gshare. --- pipelined/config/rv32ic/wally-config.vh | 2 +- pipelined/src/ifu/brpred/speculativegshare.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index 311ce8ab2..dbe29a2ee 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -132,7 +132,7 @@ `define PLIC_UART_ID 10 `define BPRED_ENABLED 1 -`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index eee2abc95..489024491 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -70,7 +70,7 @@ module speculativegshare assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]}; ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), - .ce1(~StallF | reset), .ce2(~StallW & ~FlushW), + .ce1(~StallF | reset), .ce2(~StallM & ~FlushM), .ra1(IndexNextF), .rd1(TableDirPredictionF), .wa2(IndexE), From 62d812b150af3a37d84381f335b337c2ea2b0eda Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 12:09:02 -0600 Subject: [PATCH 04/38] Updated gitflow. --- gitflow.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gitflow.txt b/gitflow.txt index 57d79333b..57300830a 100644 --- a/gitflow.txt +++ b/gitflow.txt @@ -48,3 +48,6 @@ Create pull request 1. git pull upstream main # fetch and merge the upstream openhwgroup/cvw into your local clone 3. git push # sync your fork with the upstream and clone + +If the pull request need changes, modify accordingly, commit, and push changes back to the fork. +The pull request will automatically update. From 541524a7549bb2e28af69927e6c881b97007c8cf Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 12:14:18 -0600 Subject: [PATCH 05/38] More btb cleanup. --- pipelined/src/ifu/brpred/bpred.sv | 10 +++++----- pipelined/src/ifu/brpred/btb.sv | 8 ++++---- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 6817dfd59..dd7b9e850 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -60,7 +60,7 @@ module bpred ( output logic PredictionInstrClassWrongM // Class prediction is wrong ); - logic BTBValidF; + logic PredValidF; logic [1:0] DirPredictionF; logic [3:0] PredInstrClassF, PredInstrClassD, PredInstrClassE; @@ -128,9 +128,9 @@ module bpred ( // 1) A direction (1 = Taken, 0 = Not Taken) // 2) Any information which is necessary for the predictor to build its next state. // For a 2 bit table this is the prediction count. - assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & BTBValidF) | + assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | PredInstrClassF[2] | - (PredInstrClassF[1] & BTBValidF) ; + (PredInstrClassF[1] & PredValidF) ; // Part 2 Branch target address prediction // *** For now the BTB will house the direct and indirect targets @@ -140,8 +140,8 @@ module bpred ( .*, // Stalls and flushes .PCNextF, .BTBPredPCF, - .InstrClass(PredInstrClassF), - .Valid(BTBValidF), + .PredInstrClassF, + .PredValidF, // update .UpdateEN(|InstrClassE | PredictionInstrClassWrongE), .PCE, diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index 8eba026ec..839b1b7d5 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -38,8 +38,8 @@ module btb input logic StallF, StallE, StallM, FlushM, input logic [`XLEN-1:0] PCNextF, output logic [`XLEN-1:0] BTBPredPCF, - output logic [3:0] InstrClass, - output logic Valid, + output logic [3:0] PredInstrClassF, + output logic PredValidF, // update input logic UpdateEN, input logic [`XLEN-1:0] PCE, @@ -72,13 +72,13 @@ module btb end else if (UpdateEN & ~StallM & ~FlushM) begin ValidBits[PCEIndex] <= #1 ~ UpdateInvalid; end - Valid = ValidBits[PCNextFIndex]; + PredValidF = ValidBits[PCNextFIndex]; end // An optimization may be using a PC relative address. // *** need to add forwarding. ram2p1r1wbe #(2**Depth, `XLEN+4) memory( - .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}), + .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({PredInstrClassF, BTBPredPCF}), .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1)); endmodule From d4004c2c22d3674509020db29d48a0ef4c433f1b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 13:02:20 -0600 Subject: [PATCH 06/38] Added logic to forward btb prediction results. --- pipelined/src/ifu/brpred/btb.sv | 42 ++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 8 deletions(-) diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index 839b1b7d5..bcf5dcfd9 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -35,8 +35,8 @@ module btb ) (input logic clk, input logic reset, - input logic StallF, StallE, StallM, FlushM, - input logic [`XLEN-1:0] PCNextF, + input logic StallF, StallD, StallE, StallM, FlushD, FlushM, + input logic [`XLEN-1:0] PCNextF, PCF, PCD, output logic [`XLEN-1:0] BTBPredPCF, output logic [3:0] PredInstrClassF, output logic PredValidF, @@ -50,22 +50,44 @@ module btb localparam TotalDepth = 2 ** Depth; logic [TotalDepth-1:0] ValidBits; - logic [Depth-1:0] PCNextFIndex, PCEIndex; + logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex; logic UpdateENQ; logic [`XLEN-1:0] ResetPC; - - + logic MatchF, MatchD, MatchE, MatchNextX, MatchXF; + logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF; + logic [`XLEN+3:0] TableBTBPredictionF; + logic [`XLEN-1:0] BTBPredPCD; + logic [3:0] PredInstrClassD; // copy of reg outside module + + // hashing function for indexing the PC // We have Depth bits to index, but XLEN bits as the input. // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if // using compressed instructions. XOR bit 1 with the MSB of index. + assign PCFIndex = {PCF[Depth+1] ^ PCF[1], PCF[Depth:2]}; + assign PCDIndex = {PCD[Depth+1] ^ PCD[1], PCD[Depth:2]}; assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]}; // must output a valid PC and valid bit during reset. Because the PCNextF logic of the IFU and trap units // does not mux in RESET_VECTOR we have to do it here. This is a performance optimization. assign ResetPC = `RESET_VECTOR; - assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; + assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; + + assign MatchF = PCNextFIndex == PCFIndex; + assign MatchD = PCNextFIndex == PCDIndex; + assign MatchE = PCNextFIndex == PCEIndex; + assign MatchNextX = MatchF | MatchD | MatchE; + flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); + + assign ForwardBTBPrediction = MatchF ? {PredInstrClassF, BTBPredPCF} : + MatchD ? {PredInstrClassD, BTBPredPCD} : + {InstrClassE, IEUAdrE} ; + + flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); + + assign {PredInstrClassF, BTBPredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF; + always_ff @ (posedge clk) begin if (reset) begin ValidBits <= #1 {TotalDepth{1'b0}}; @@ -76,9 +98,13 @@ module btb end // An optimization may be using a PC relative address. - // *** need to add forwarding. ram2p1r1wbe #(2**Depth, `XLEN+4) memory( - .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({PredInstrClassF, BTBPredPCF}), + .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1)); + flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {PredInstrClassF, BTBPredPCF}, {PredInstrClassD, BTBPredPCD}); + + + + endmodule From bb89bf82bfd08a6ed87457db7915ce9087a51bf4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 15:16:53 -0600 Subject: [PATCH 07/38] Fixed subtle bug in btb. --- pipelined/src/ifu/brpred/bpred.sv | 1 - pipelined/src/ifu/brpred/btb.sv | 5 ++--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index dd7b9e850..485875b66 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -146,7 +146,6 @@ module bpred ( .UpdateEN(|InstrClassE | PredictionInstrClassWrongE), .PCE, .IEUAdrE, - .UpdateInvalid(PredictionInstrClassWrongE), .InstrClassE); // Part 3 RAS diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index bcf5dcfd9..aba3826b3 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -44,8 +44,7 @@ module btb input logic UpdateEN, input logic [`XLEN-1:0] PCE, input logic [`XLEN-1:0] IEUAdrE, - input logic [3:0] InstrClassE, - input logic UpdateInvalid + input logic [3:0] InstrClassE ); localparam TotalDepth = 2 ** Depth; @@ -92,7 +91,7 @@ module btb if (reset) begin ValidBits <= #1 {TotalDepth{1'b0}}; end else if (UpdateEN & ~StallM & ~FlushM) begin - ValidBits[PCEIndex] <= #1 ~ UpdateInvalid; + ValidBits[PCEIndex] <= #1 |InstrClassE; end PredValidF = ValidBits[PCNextFIndex]; end From 3d285312f03ccb4fcc7e13ac15ffcee5a401967c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 15:29:55 -0600 Subject: [PATCH 08/38] Cleaned up branch predictor. --- pipelined/src/ifu/brpred/bpred.sv | 3 +-- pipelined/src/ifu/brpred/btb.sv | 14 ++++++-------- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 485875b66..d259b3b3d 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -142,8 +142,7 @@ module bpred ( .BTBPredPCF, .PredInstrClassF, .PredValidF, - // update - .UpdateEN(|InstrClassE | PredictionInstrClassWrongE), + .PredictionInstrClassWrongE, .PCE, .IEUAdrE, .InstrClassE); diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index aba3826b3..fdac1c54d 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -41,7 +41,7 @@ module btb output logic [3:0] PredInstrClassF, output logic PredValidF, // update - input logic UpdateEN, + input logic PredictionInstrClassWrongE, input logic [`XLEN-1:0] PCE, input logic [`XLEN-1:0] IEUAdrE, input logic [3:0] InstrClassE @@ -50,7 +50,6 @@ module btb localparam TotalDepth = 2 ** Depth; logic [TotalDepth-1:0] ValidBits; logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex; - logic UpdateENQ; logic [`XLEN-1:0] ResetPC; logic MatchF, MatchD, MatchE, MatchNextX, MatchXF; logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF; @@ -67,8 +66,10 @@ module btb assign PCDIndex = {PCD[Depth+1] ^ PCD[1], PCD[Depth:2]}; assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]}; - // must output a valid PC and valid bit during reset. Because the PCNextF logic of the IFU and trap units - // does not mux in RESET_VECTOR we have to do it here. This is a performance optimization. + // must output a valid PC and valid bit during reset. Because only PCF, not PCNextF is reset, PCNextF is invalid + // during reset. The BTB must produce a non X PC1NextF to allow the simulation to run. + // While thie mux could be included in IFU it is not necessary for the IROM/I$/bus. + // For now it is optimal to leave it here. assign ResetPC = `RESET_VECTOR; assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; @@ -90,7 +91,7 @@ module btb always_ff @ (posedge clk) begin if (reset) begin ValidBits <= #1 {TotalDepth{1'b0}}; - end else if (UpdateEN & ~StallM & ~FlushM) begin + end else if ((|InstrClassE | PredictionInstrClassWrongE) & ~StallM & ~FlushM) begin ValidBits[PCEIndex] <= #1 |InstrClassE; end PredValidF = ValidBits[PCNextFIndex]; @@ -103,7 +104,4 @@ module btb flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {PredInstrClassF, BTBPredPCF}, {PredInstrClassD, BTBPredPCD}); - - - endmodule From 56aa798d5c2a131c24afcf19b9d6ecd2099500a8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 16:03:02 -0600 Subject: [PATCH 09/38] More branch predictor improvements. --- pipelined/src/ifu/brpred/bpred.sv | 17 +++-- pipelined/src/ifu/brpred/btb.sv | 39 ++++++------ .../ifu/brpred/speculativeglobalhistory.sv | 62 ++++++++++--------- pipelined/src/ifu/brpred/speculativegshare.sv | 8 +-- 4 files changed, 60 insertions(+), 66 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index d259b3b3d..35dffa964 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -64,7 +64,7 @@ module bpred ( logic [1:0] DirPredictionF; logic [3:0] PredInstrClassF, PredInstrClassD, PredInstrClassE; - logic [`XLEN-1:0] BTBPredPCF, RASPCF; + logic [`XLEN-1:0] PredPCF, RASPCF; logic TargetWrongE; logic FallThroughWrongE; logic PredictionPCWrongE; @@ -95,8 +95,8 @@ module bpred ( speculativeglobalhistory #(10) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), - .BranchInstrW(InstrClassW[0]), .PCSrcE); - + .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE); + end else if (`BPTYPE == "BPGSHARE") begin:Predictor gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, @@ -135,15 +135,12 @@ module bpred ( // Part 2 Branch target address prediction // *** For now the BTB will house the direct and indirect targets - btb TargetPredictor(.clk(clk), - .reset(reset), - .*, // Stalls and flushes - .PCNextF, - .BTBPredPCF, + btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM, + .PCNextF, .PCF, .PCD, .PCE, + .PredPCF, .PredInstrClassF, .PredValidF, .PredictionInstrClassWrongE, - .PCE, .IEUAdrE, .InstrClassE); @@ -160,7 +157,7 @@ module bpred ( .incr(1'b0), .PCLinkE); - assign BPPredPCF = PredInstrClassF[2] ? RASPCF : BTBPredPCF; + assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; // the branch predictor needs a compact decoding of the instruction class. assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index fdac1c54d..a81af5bb4 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -35,16 +35,15 @@ module btb ) (input logic clk, input logic reset, - input logic StallF, StallD, StallE, StallM, FlushD, FlushM, - input logic [`XLEN-1:0] PCNextF, PCF, PCD, - output logic [`XLEN-1:0] BTBPredPCF, - output logic [3:0] PredInstrClassF, - output logic PredValidF, + input logic StallF, StallD, StallM, FlushD, FlushM, + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, // PC at various stages + output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC + output logic [3:0] PredInstrClassF, // BTB's guess at instruction class + output logic PredValidF, // BTB's guess is valid // update - input logic PredictionInstrClassWrongE, - input logic [`XLEN-1:0] PCE, - input logic [`XLEN-1:0] IEUAdrE, - input logic [3:0] InstrClassE + input logic PredictionInstrClassWrongE, // BTB's instruction class guess was wrong + input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb + input logic [3:0] InstrClassE // Instruction class to insert into btb ); localparam TotalDepth = 2 ** Depth; @@ -54,10 +53,10 @@ module btb logic MatchF, MatchD, MatchE, MatchNextX, MatchXF; logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF; logic [`XLEN+3:0] TableBTBPredictionF; - logic [`XLEN-1:0] BTBPredPCD; - logic [3:0] PredInstrClassD; // copy of reg outside module - - + logic [`XLEN-1:0] PredPCD; + logic [3:0] PredInstrClassD; // *** copy of reg outside module + logic UpdateEn; + // hashing function for indexing the PC // We have Depth bits to index, but XLEN bits as the input. // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if @@ -80,28 +79,30 @@ module btb flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - assign ForwardBTBPrediction = MatchF ? {PredInstrClassF, BTBPredPCF} : - MatchD ? {PredInstrClassD, BTBPredPCD} : + assign ForwardBTBPrediction = MatchF ? {PredInstrClassF, PredPCF} : + MatchD ? {PredInstrClassD, PredPCD} : {InstrClassE, IEUAdrE} ; flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); - assign {PredInstrClassF, BTBPredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF; + assign {PredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF; always_ff @ (posedge clk) begin if (reset) begin ValidBits <= #1 {TotalDepth{1'b0}}; - end else if ((|InstrClassE | PredictionInstrClassWrongE) & ~StallM & ~FlushM) begin + end else if ((UpdateEn) & ~StallM & ~FlushM) begin ValidBits[PCEIndex] <= #1 |InstrClassE; end PredValidF = ValidBits[PCNextFIndex]; end + assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE; + // An optimization may be using a PC relative address. ram2p1r1wbe #(2**Depth, `XLEN+4) memory( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), - .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1)); + .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1)); - flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {PredInstrClassF, BTBPredPCF}, {PredInstrClassD, BTBPredPCD}); + flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {PredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD}); endmodule diff --git a/pipelined/src/ifu/brpred/speculativeglobalhistory.sv b/pipelined/src/ifu/brpred/speculativeglobalhistory.sv index 094adca99..ecc7a3b0f 100644 --- a/pipelined/src/ifu/brpred/speculativeglobalhistory.sv +++ b/pipelined/src/ifu/brpred/speculativeglobalhistory.sv @@ -40,52 +40,56 @@ module speculativeglobalhistory output logic DirPredictionWrongE, // update input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, + input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, + input logic [3:0] WrongPredInstrClassD, input logic PCSrcE ); - logic MatchF, MatchD, MatchE, MatchM, MatchW; + logic MatchF, MatchD, MatchE; logic MatchNextX, MatchXF; logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW; + logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; logic [k-1:0] GHRF; logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; logic [k-1:0] GHRNextF; - logic [k:0] GHRNextD, GHRNextE, GHRNextM, GHRNextW; - logic PCSrcM, PCSrcW; + logic [k:-1] GHRNextD, OldGHRD; + logic [k:0] GHRNextE, GHRNextM, GHRNextW; + logic [k-1:0] IndexNextF, IndexF; + logic [k-1:0] IndexD, IndexE; + logic [`XLEN-1:0] PCW; logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; + assign IndexNextF = GHRNextF; + assign IndexF = GHRF; + assign IndexD = GHRD[k-1:0]; + assign IndexE = GHRE[k-1:0]; ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), - .ce1(~StallF | reset), .ce2(~StallW & ~FlushW), - .ra1(GHRNextF), + .ce1(~StallF | reset), .ce2(~StallM & ~FlushM), + .ra1(IndexNextF), .rd1(TableDirPredictionF), - .wa2(GHRW[k-1:0]), - .wd2(NewDirPredictionW), - .we2(BranchInstrW & ~StallW & ~FlushW), + .wa2(IndexE), + .wd2(NewDirPredictionE), + .we2(BranchInstrE & ~StallM & ~FlushM), .bwe2(1'b1)); // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage - // and then register for use in the Fetch stage. - assign MatchF = BranchInstrF & ~FlushD & (GHRNextF == GHRF); - assign MatchD = BranchInstrD & ~FlushE & (GHRNextF == GHRD[k-1:0]); - assign MatchE = BranchInstrE & ~FlushM & (GHRNextF == GHRE[k-1:0]); - assign MatchM = BranchInstrM & ~FlushW & (GHRNextF == GHRM[k-1:0]); - assign MatchW = BranchInstrW & (GHRNextF == GHRW[k-1:0]); - assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW; + // and then register for use in the Fetch stage. + assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF); + assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD); + assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE); + assign MatchNextX = MatchF | MatchD | MatchE; flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF : MatchD ? NewDirPredictionD : - MatchE ? NewDirPredictionE : - MatchM ? NewDirPredictionM : - NewDirPredictionW; - + NewDirPredictionE ; + flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF); assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF; @@ -95,16 +99,11 @@ module speculativeglobalhistory flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE); // New prediction pipeline - satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF)); + assign NewDirPredictionF = {DirPredictionF[1], DirPredictionF[1]}; + flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD); satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); - flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM); - flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW); - // PCSrc pipeline - flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM); - flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW); - // GHR pipeline assign GHRNextF = FlushD ? GHRNextD[k:1] : BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : @@ -112,8 +111,11 @@ module speculativeglobalhistory flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); - assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF}; - flopenr #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); + assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]}; + flopenr #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD); + assign GHRD = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right + WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left + OldGHRD[k:0]; assign GHRNextE = FlushE ? GHRNextM : GHRD; flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE); diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 489024491..b72aacb44 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -49,7 +49,7 @@ module speculativegshare logic MatchNextX, MatchXF; logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM; + logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; logic [k-1:0] GHRF; logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; @@ -59,7 +59,6 @@ module speculativegshare logic [k-1:0] IndexNextF, IndexF; logic [k-1:0] IndexD, IndexE; - logic PCSrcM, PCSrcW; logic [`XLEN-1:0] PCW; logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; @@ -104,12 +103,7 @@ module speculativegshare flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD); satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); - flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM); - // PCSrc pipeline - flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM); - flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW); - // GHR pipeline assign GHRNextF = FlushD ? GHRNextD[k:1] : BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : From 172c40d44b9ffb2e890a8548884c911b803e6a16 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 17:06:25 -0600 Subject: [PATCH 10/38] Improved RAS. --- pipelined/config/rv64gc/wally-config.vh | 7 ++++--- pipelined/src/ifu/brpred/RAsPredictor.sv | 16 ++++++++++------ pipelined/src/ifu/brpred/bpred.sv | 21 +++++++++++---------- pipelined/src/ifu/brpred/globalhistory.sv | 9 ++++----- pipelined/src/ifu/brpred/gshare.sv | 15 +++++++-------- 5 files changed, 36 insertions(+), 32 deletions(-) diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 29148944f..6ecab2845 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -135,9 +135,10 @@ `define PLIC_UART_ID 10 `define BPRED_ENABLED 1 -//`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 -`define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 -//`define BPTYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +//`define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +//`define BPTYPE "BPGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv index c71ff2966..422a785cc 100644 --- a/pipelined/src/ifu/brpred/RAsPredictor.sv +++ b/pipelined/src/ifu/brpred/RAsPredictor.sv @@ -32,13 +32,10 @@ module RASPredictor #(parameter int StackSize = 16 ) (input logic clk, - input logic reset, - input logic PopF, + input logic reset, StallF, StallD, StallE, output logic [`XLEN-1:0] RASPCF, input logic [3:0] WrongPredInstrClassD, - input logic [3:0] InstrClassD, - input logic PushE, - input logic incr, + input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF, input logic [`XLEN-1:0] PCLinkE ); @@ -51,8 +48,15 @@ module RASPredictor logic [Depth-1:0] PtrD, PtrQ, PtrP1, PtrM1; logic [StackSize-1:0] [`XLEN-1:0] memory; integer index; + logic PopF; + logic PushE; - assign CounterEn = PopF | PushE | incr | WrongPredInstrClassD[2]; + + + assign PopF = PredInstrClassF[2] & ~StallF; + assign PushE = InstrClassE[3] & ~StallE; + + assign CounterEn = PopF | PushE | WrongPredInstrClassD[2]; assign PtrD = PopF | InstrClassD[2] ? PtrM1 : PtrP1; diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 35dffa964..1669ee4f3 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -99,7 +99,7 @@ module bpred ( end else if (`BPTYPE == "BPGSHARE") begin:Predictor gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, + .PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); end else if (`BPTYPE == "BPSPECULATIVEGSHARE") begin:Predictor @@ -147,15 +147,9 @@ module bpred ( // Part 3 RAS // *** need to add the logic to restore RAS on flushes. We will use incr for this. // *** needs to include flushX - RASPredictor RASPredictor(.clk(clk), - .reset(reset), - .PopF(PredInstrClassF[2] & ~StallF), - .WrongPredInstrClassD, - .InstrClassD, - .RASPCF, - .PushE(InstrClassE[3] & ~StallE), - .incr(1'b0), - .PCLinkE); + RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, + .PredInstrClassF, .InstrClassD, .InstrClassE, + .WrongPredInstrClassD, .RASPCF, .PCLinkE); assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; @@ -227,5 +221,12 @@ module bpred ( // end else begin // assign NextValidPCE = PCE; // end + + // performance counters + // 1. class (class wrong / minstret) + // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) + // 3. target ras (ras target wrong / class[2]) + // 4. direction (br dir wrong / class[0]) + endmodule diff --git a/pipelined/src/ifu/brpred/globalhistory.sv b/pipelined/src/ifu/brpred/globalhistory.sv index 7aa86dbb9..55b6827cd 100644 --- a/pipelined/src/ifu/brpred/globalhistory.sv +++ b/pipelined/src/ifu/brpred/globalhistory.sv @@ -46,7 +46,7 @@ module globalhistory logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionE, NewDirPredictionM; - logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR; + logic [k-1:0] GHRF, GHRD, GHRE, GHR; logic [k-1:0] GHRNext; logic PCSrcM; @@ -55,9 +55,9 @@ module globalhistory .ce1(~StallF), .ce2(~StallM & ~FlushM), .ra1(GHR), .rd1(DirPredictionF), - .wa2(GHRM), - .wd2(NewDirPredictionM), - .we2(BranchInstrM & ~StallM & ~FlushM), + .wa2(GHRE), + .wd2(NewDirPredictionE), + .we2(BranchInstrE & ~StallM & ~FlushM), .bwe2(1'b1)); flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD); @@ -76,7 +76,6 @@ module globalhistory flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF); flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD); flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE); - flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM); endmodule diff --git a/pipelined/src/ifu/brpred/gshare.sv b/pipelined/src/ifu/brpred/gshare.sv index ce189d268..ff24c84d3 100644 --- a/pipelined/src/ifu/brpred/gshare.sv +++ b/pipelined/src/ifu/brpred/gshare.sv @@ -39,28 +39,28 @@ module gshare output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update - input logic [`XLEN-1:0] PCNextF, PCM, + input logic [`XLEN-1:0] PCNextF, PCE, input logic BranchInstrE, BranchInstrM, PCSrcE ); - logic [k-1:0] IndexNextF, IndexM; + logic [k-1:0] IndexNextF, IndexE; logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionE, NewDirPredictionM; - logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR; + logic [k-1:0] GHRF, GHRD, GHRE, GHR; logic [k-1:0] GHRNext; logic PCSrcM; assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; - assign IndexM = GHRM & {PCM[k+1] ^ PCM[1], PCM[k:2]}; + assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]}; ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallM & ~FlushM), .ra1(IndexNextF), .rd1(DirPredictionF), - .wa2(IndexM), - .wd2(NewDirPredictionM), - .we2(BranchInstrM & ~StallM & ~FlushM), + .wa2(IndexE), + .wd2(NewDirPredictionE), + .we2(BranchInstrE & ~StallM & ~FlushM), .bwe2(1'b1)); flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD); @@ -78,7 +78,6 @@ module gshare flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF); flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD); flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE); - flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM); endmodule From 0b9f78763530119556672c8f2ab2d4f730d5b57c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 17:10:52 -0600 Subject: [PATCH 11/38] Improved RAS again. --- pipelined/regression/wave.do | 83 ++++++++++-------------- pipelined/src/ifu/brpred/RAsPredictor.sv | 15 ++--- pipelined/src/ifu/brpred/bpred.sv | 2 +- 3 files changed, 44 insertions(+), 56 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index be29ed870..393f6ee11 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -41,12 +41,12 @@ add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpi add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM -add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF -add wave -noupdate -expand -group PCS /testbench/dut/core/PCF -add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD -add wave -noupdate -expand -group PCS /testbench/dut/core/PCE -add wave -noupdate -expand -group PCS /testbench/dut/core/PCM -add wave -noupdate -expand -group PCS /testbench/PCW +add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF +add wave -noupdate -group PCS /testbench/dut/core/PCF +add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD +add wave -noupdate -group PCS /testbench/dut/core/PCE +add wave -noupdate -group PCS /testbench/dut/core/PCM +add wave -noupdate -group PCS /testbench/PCW add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD add wave -noupdate -group {Decode Stage} /testbench/InstrDName @@ -55,15 +55,15 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE -add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE -add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM -add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE +add wave -noupdate -group {Execution Stage} /testbench/InstrEName +add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE +add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName +add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM +add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM +add wave -noupdate -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM add wave -noupdate -group {WriteBack stage} /testbench/PCW add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName @@ -85,25 +85,18 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check} -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC -add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE +add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF +add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF +add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF +add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE +add wave -noupdate -group Bpred -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE +add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF @@ -148,20 +141,15 @@ add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE -add wave -noupdate -group AHB -expand -group multicontroller -color Gold /testbench/dut/core/ebu/ebu/CurrState add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUReq add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUReq -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/both add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSave add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFURestore add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUDisable add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/BeatCount -add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/FinalBeat add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS -add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/Threshold add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR @@ -463,10 +451,6 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/P add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F -add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF -add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState -add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0 -add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE @@ -484,7 +468,6 @@ add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF -add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay @@ -571,7 +554,6 @@ add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD3E add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/Funct3E -add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/MDUE add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/W64E add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/X add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Y @@ -603,8 +585,15 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/Br add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrM add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionW +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/ra1 +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/rd1 +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/IEUAdrE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {116741 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {125611 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -620,4 +609,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {118528 ns} {128752 ns} +WaveRestoreZoom {79760 ns} {171462 ns} diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv index 422a785cc..28d15ebbe 100644 --- a/pipelined/src/ifu/brpred/RAsPredictor.sv +++ b/pipelined/src/ifu/brpred/RAsPredictor.sv @@ -32,15 +32,13 @@ module RASPredictor #(parameter int StackSize = 16 ) (input logic clk, - input logic reset, StallF, StallD, StallE, + input logic reset, StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM, output logic [`XLEN-1:0] RASPCF, input logic [3:0] WrongPredInstrClassD, input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF, input logic [`XLEN-1:0] PCLinkE ); - // *** need to update so it either doesn't push until the memory stage - // or need to repair flushed push. // *** need to repair popped and then flushed returns. logic CounterEn; localparam Depth = $clog2(StackSize); @@ -50,19 +48,20 @@ module RASPredictor integer index; logic PopF; logic PushE; + logic RepairD; - assign PopF = PredInstrClassF[2] & ~StallF; - assign PushE = InstrClassE[3] & ~StallE; + assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD; + assign RepairD = InstrClassD[2] & ~StallE & ~FlushE; + assign PushE = InstrClassE[3] & ~StallM & ~FlushM; assign CounterEn = PopF | PushE | WrongPredInstrClassD[2]; - assign PtrD = PopF | InstrClassD[2] ? PtrM1 : PtrP1; + assign PtrD = PopF | RepairD ? PtrM1 : PtrP1; assign PtrM1 = PtrQ - 1'b1; assign PtrP1 = PtrQ + 1'b1; - // may have to handle a PushE and an incr at the same time. // *** what happens if jal is executing and there is a return being flushed in Decode? flopenr #(Depth) PTR(.clk(clk), @@ -75,7 +74,7 @@ module RASPredictor always_ff @ (posedge clk) begin if(reset) begin for(index=0; index Date: Wed, 25 Jan 2023 17:18:07 -0600 Subject: [PATCH 12/38] RAS is now compliant with our header and documentation guide. --- pipelined/src/ifu/brpred/RAsPredictor.sv | 40 +++++++++++++----------- 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv index 28d15ebbe..42c484393 100644 --- a/pipelined/src/ifu/brpred/RAsPredictor.sv +++ b/pipelined/src/ifu/brpred/RAsPredictor.sv @@ -1,13 +1,14 @@ /////////////////////////////////////////// // RASPredictor.sv // -// Written: Ross Thomposn -// Email: ross1728@gmail.com -// Created: February 15, 2021 -// Modified: +// Written: Ross Thomposn ross1728@gmail.com +// Created: 15 February 2021 +// Modified: 25 January 2023 // // Purpose: 2 bit saturating counter predictor with parameterized table depth. // +// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) +// // A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University @@ -28,41 +29,42 @@ `include "wally-config.vh" -module RASPredictor - #(parameter int StackSize = 16 - ) - (input logic clk, - input logic reset, StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM, - output logic [`XLEN-1:0] RASPCF, - input logic [3:0] WrongPredInstrClassD, - input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF, - input logic [`XLEN-1:0] PCLinkE +module RASPredictor #(parameter int StackSize = 16 +)(input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM, + input logic [3:0] WrongPredInstrClassD, // Prediction class is wrong + input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF, // Instr class + input logic [`XLEN-1:0] PCLinkE, // PC of instruction after a jal + output logic [`XLEN-1:0] RASPCF // Top of the stack ); - // *** need to repair popped and then flushed returns. logic CounterEn; localparam Depth = $clog2(StackSize); logic [Depth-1:0] PtrD, PtrQ, PtrP1, PtrM1; logic [StackSize-1:0] [`XLEN-1:0] memory; integer index; + logic PopF; logic PushE; logic RepairD; + logic PossibleRepairD; + logic DecrementPtr; - assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD; - assign RepairD = InstrClassD[2] & ~StallE & ~FlushE; + assign PossibleRepairD = InstrClassD[2] & ~StallE & ~FlushE; + assign RepairD = WrongPredInstrClassD[2] & ~StallE & ~FlushE; assign PushE = InstrClassE[3] & ~StallM & ~FlushM; - assign CounterEn = PopF | PushE | WrongPredInstrClassD[2]; + assign CounterEn = PopF | PushE | RepairD; - assign PtrD = PopF | RepairD ? PtrM1 : PtrP1; + assign DecrementPtr = PopF | PossibleRepairD; + mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, PtrD); assign PtrM1 = PtrQ - 1'b1; assign PtrP1 = PtrQ + 1'b1; - // *** what happens if jal is executing and there is a return being flushed in Decode? flopenr #(Depth) PTR(.clk(clk), .reset(reset), From 4e858199e5aa5d50706dafcdb3f8352c83352a0c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 18:51:09 -0600 Subject: [PATCH 13/38] Fixed typos. --- pipelined/src/ifu/brpred/bpred.sv | 6 +++--- pipelined/src/ifu/ifu.sv | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index d9f342db1..6803f65d4 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -197,8 +197,8 @@ module bpred ( assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | BPPredClassNonCFIWrongE; // If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter. - assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1]) & PredictionPCWrongE; - // similar with RAS + assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE; + // similar with RAS. Over counts ras if the class prediction was wrong. assign RASPredPCWrongE = InstrClassE[2] & PredictionPCWrongE; // Finally if the real instruction class is non CFI but the predictor said it was we need to count. assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE; @@ -223,7 +223,7 @@ module bpred ( // end // performance counters - // 1. class (class wrong / minstret) + // 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) // 3. target ras (ras target wrong / class[2]) // 4. direction (br dir wrong / class[0]) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 476f666ff..f48727500 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -115,7 +115,7 @@ module ifu ( logic [31:0] NextInstrD, NextInstrE; // Instruction into the next stage after possible stage flush - logic CacheableF; // PMA indicates isntruction address is cacheable + logic CacheableF; // PMA indicates instruction address is cacheable logic SelNextSpillF; // In a spill, stall pipeline and gate local stallF logic BusStall; // Bus interface busy with multicycle operation logic ICacheStallF; // I$ busy with multicycle operation From 43d4ac1c7b67da024a71bda064e9838d8f22cc05 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 19:39:18 -0600 Subject: [PATCH 14/38] Intermediate commit. Passes regression tests, but RAS is not correct. --- pipelined/regression/wave.do | 47 ++++++------------------ pipelined/src/ifu/brpred/RAsPredictor.sv | 3 +- pipelined/src/ifu/brpred/bpred.sv | 40 ++++++++++++++++++-- pipelined/src/ifu/brpred/btb.sv | 8 ++-- pipelined/src/ifu/ifu.sv | 2 +- 5 files changed, 55 insertions(+), 45 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 393f6ee11..ccc5928a5 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -55,11 +55,11 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D -add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE -add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE -add wave -noupdate -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE -add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName +add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE +add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE +add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName +add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE +add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM add wave -noupdate -group {Memory Stage} /testbench/InstrMName @@ -85,11 +85,8 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check} -add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF -add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE -add wave -noupdate -group Bpred -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE @@ -566,34 +563,12 @@ add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchNextX -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchW -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrW -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionW -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/ra1 -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/rd1 -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/IEUAdrE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PtrQ +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PopF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PushE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RASPCF TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {125611 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {117097 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -609,4 +584,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {79760 ns} {171462 ns} +WaveRestoreZoom {117047 ns} {117181 ns} diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv index 42c484393..6f2cbd059 100644 --- a/pipelined/src/ifu/brpred/RAsPredictor.sv +++ b/pipelined/src/ifu/brpred/RAsPredictor.sv @@ -54,7 +54,8 @@ module RASPredictor #(parameter int StackSize = 16 logic DecrementPtr; assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD; - assign PossibleRepairD = InstrClassD[2] & ~StallE & ~FlushE; + // **********this part is wrong. + assign PossibleRepairD = (InstrClassD[2] & ~StallE & FlushE) | (PredInstrClassF[2] & ~StallD & FlushD); assign RepairD = WrongPredInstrClassD[2] & ~StallE & ~FlushE; assign PushE = InstrClassE[3] & ~StallM & ~FlushM; diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 6803f65d4..82bdf1f00 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -28,6 +28,8 @@ `include "wally-config.vh" +`define INSTR_CLASS_PRED 0 + module bpred ( input logic clk, reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -46,6 +48,8 @@ module bpred ( input logic [`XLEN-1:0] PCE, // Execution stage instruction address input logic [`XLEN-1:0] PCM, // Memory stage instruction address + input logic [31:0] PostSpillInstrRawF, // Instruction + // Branch and jump outcome input logic PCSrcE, // Executation stage branch is taken input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address @@ -63,13 +67,13 @@ module bpred ( logic PredValidF; logic [1:0] DirPredictionF; - logic [3:0] PredInstrClassF, PredInstrClassD, PredInstrClassE; + logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD, PredInstrClassE; logic [`XLEN-1:0] PredPCF, RASPCF; logic TargetWrongE; logic FallThroughWrongE; logic PredictionPCWrongE; logic PredictionInstrClassWrongE; - logic [3:0] InstrClassD, InstrClassE, InstrClassW; + logic [3:0] InstrClassF, InstrClassD, InstrClassE, InstrClassW; logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE; logic SelBPPredF; @@ -138,7 +142,7 @@ module bpred ( btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM, .PCNextF, .PCF, .PCD, .PCE, .PredPCF, - .PredInstrClassF, + .BTBPredInstrClassF, .PredValidF, .PredictionInstrClassWrongE, .IEUAdrE, @@ -154,6 +158,36 @@ module bpred ( assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; // the branch predictor needs a compact decoding of the instruction class. + if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode + logic [4:0] CompressedOpcF; + logic [3:0] InstrClassF; + logic cjal, cj, cjr, cjalr; + + assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]}; + + assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32; + assign cj = CompressedOpcF == 5'h0d; + assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; + assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; + + assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | + (`C_SUPPORTED & CompressedOpcF == 5'h0e); + + assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return + (PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5 + (`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) )); + + assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5 + (`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); + + assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 + (`C_SUPPORTED & (cjal | cjalr) & ((PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)); + assign PredInstrClassF = InstrClassF; + end else begin + assign PredInstrClassF = BTBPredInstrClassF; + end + + assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5 assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index a81af5bb4..9b6c66b85 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -38,7 +38,7 @@ module btb input logic StallF, StallD, StallM, FlushD, FlushM, input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, // PC at various stages output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC - output logic [3:0] PredInstrClassF, // BTB's guess at instruction class + output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class output logic PredValidF, // BTB's guess is valid // update input logic PredictionInstrClassWrongE, // BTB's instruction class guess was wrong @@ -79,13 +79,13 @@ module btb flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - assign ForwardBTBPrediction = MatchF ? {PredInstrClassF, PredPCF} : + assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} : MatchD ? {PredInstrClassD, PredPCD} : {InstrClassE, IEUAdrE} ; flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); - assign {PredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF; + assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF; always_ff @ (posedge clk) begin if (reset) begin @@ -103,6 +103,6 @@ module btb .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1)); - flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {PredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD}); + flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {BTBPredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD}); endmodule diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index f48727500..26227bb9b 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -327,7 +327,7 @@ module ifu ( .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE, - .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, + .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM); end else begin : bpred From 29d4cd7ffa3705f31285bf4e763291481f5aae37 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 23:33:03 -0600 Subject: [PATCH 15/38] Modified the RAS to correctly repair itself. --- pipelined/src/ifu/brpred/RAsPredictor.sv | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ifu/brpred/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv index 6f2cbd059..17ebbd1c4 100644 --- a/pipelined/src/ifu/brpred/RAsPredictor.sv +++ b/pipelined/src/ifu/brpred/RAsPredictor.sv @@ -49,29 +49,33 @@ module RASPredictor #(parameter int StackSize = 16 logic PopF; logic PushE; logic RepairD; - logic PossibleRepairD; + logic IncrRepairD, DecRepairD; logic DecrementPtr; assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD; - // **********this part is wrong. - assign PossibleRepairD = (InstrClassD[2] & ~StallE & FlushE) | (PredInstrClassF[2] & ~StallD & FlushD); - assign RepairD = WrongPredInstrClassD[2] & ~StallE & ~FlushE; + + assign RepairD = ((WrongPredInstrClassD[2]) & ~StallE & ~FlushE) | // Wrong class undo increment or decrement. + (~StallE & FlushE & InstrClassD[2]) | // ret in decode flushed + (~StallM & FlushM & InstrClassE[2]) ; // ret in execution flushed + + assign IncrRepairD = (~StallE & FlushE & InstrClassD[2]) | // ret in decode flushed + (~StallM & FlushM & InstrClassE[2]) | // ret in execution flushed + (WrongPredInstrClassD[2] & ~InstrClassD[2] & ~StallE & ~FlushE); // Guessed it was a ret, but its not + + assign DecRepairD = (WrongPredInstrClassD[2] & InstrClassD[2] & ~StallE & ~FlushE); // Guessed non ret but is a ret. + assign PushE = InstrClassE[3] & ~StallM & ~FlushM; assign CounterEn = PopF | PushE | RepairD; - assign DecrementPtr = PopF | PossibleRepairD; + assign DecrementPtr = (PopF | DecRepairD) & ~IncrRepairD; mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, PtrD); assign PtrM1 = PtrQ - 1'b1; assign PtrP1 = PtrQ + 1'b1; - flopenr #(Depth) PTR(.clk(clk), - .reset(reset), - .en(CounterEn), - .d(PtrD), - .q(PtrQ)); + flopenr #(Depth) PTR(clk, reset, CounterEn, PtrD, PtrQ); // RAS must be reset. always_ff @ (posedge clk) begin From 2ee6ffe74b75c7c132003ae5c51dcc528b1c43b1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 26 Jan 2023 10:54:43 -0600 Subject: [PATCH 16/38] Improved no class prediction mode. --- pipelined/src/ifu/brpred/bpred.sv | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 82bdf1f00..ff26904ce 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -132,9 +132,6 @@ module bpred ( // 1) A direction (1 = Taken, 0 = Not Taken) // 2) Any information which is necessary for the predictor to build its next state. // For a 2 bit table this is the prediction count. - assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | - PredInstrClassF[2] | - (PredInstrClassF[1] & PredValidF) ; // Part 2 Branch target address prediction // *** For now the BTB will house the direct and indirect targets @@ -183,8 +180,14 @@ module bpred ( assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 (`C_SUPPORTED & (cjal | cjalr) & ((PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)); assign PredInstrClassF = InstrClassF; + assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | + PredInstrClassF[2] | + (PredInstrClassF[1]) ; end else begin assign PredInstrClassF = BTBPredInstrClassF; + assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | + PredInstrClassF[2] | + (PredInstrClassF[1] & PredValidF) ; end From 36526734870bd5eaef40a81b1e2d3443bfe8e120 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 26 Jan 2023 11:07:47 -0600 Subject: [PATCH 17/38] Fixed compressed branch class decode. --- pipelined/src/ifu/brpred/bpred.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index ff26904ce..b55738ae8 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -28,7 +28,7 @@ `include "wally-config.vh" -`define INSTR_CLASS_PRED 0 +`define INSTR_CLASS_PRED 1 module bpred ( input logic clk, reset, @@ -178,7 +178,7 @@ module bpred ( (`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 - (`C_SUPPORTED & (cjal | cjalr) & ((PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)); + (`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01))); assign PredInstrClassF = InstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | PredInstrClassF[2] | From e0ca23cdd67788bf44a373660cdd8390fb967db1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 26 Jan 2023 12:19:33 -0600 Subject: [PATCH 18/38] Fixed another bug with the compressed instruction class decode. --- pipelined/src/ifu/brpred/bpred.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index b55738ae8..38fd39bc3 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -28,7 +28,7 @@ `include "wally-config.vh" -`define INSTR_CLASS_PRED 1 +`define INSTR_CLASS_PRED 0 module bpred ( input logic clk, reset, @@ -168,7 +168,7 @@ module bpred ( assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | - (`C_SUPPORTED & CompressedOpcF == 5'h0e); + (`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7); assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return (PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5 From bbb47fc94344a9b9d387045d6669860e9e2513cb Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 26 Jan 2023 13:21:16 -0600 Subject: [PATCH 19/38] Changed the performance counters to track different data. Now rather than tracking jump(r) we track jump(r) and taken branches. --- pipelined/regression/wave.do | 35 +++++++++++++++++----- pipelined/src/ifu/brpred/bpred.sv | 36 +++++++++++++++++++++-- pipelined/src/ifu/ifu.sv | 3 +- pipelined/src/privileged/csr.sv | 3 +- pipelined/src/privileged/csrc.sv | 3 +- pipelined/src/privileged/privileged.sv | 3 +- pipelined/src/wally/wallypipelinedcore.sv | 5 ++-- 7 files changed, 72 insertions(+), 16 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index ccc5928a5..1e34435a5 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -1,4 +1,5 @@ onerror {resume} +quietly virtual signal -install /testbench/dut/core/ifu/bpred/bpred { /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF[11:7]} rd quietly WaveActivateNextPane {} 0 add wave -noupdate /testbench/clk add wave -noupdate /testbench/reset @@ -36,11 +37,11 @@ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW -add wave -noupdate -group {instruction pipeline} /testbench/InstrFName -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM +add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF add wave -noupdate -group PCS /testbench/dut/core/PCF add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD @@ -567,8 +568,28 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PtrQ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PopF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PushE add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RASPCF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RepairD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/CompressedOpcF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/InstrClassF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjal +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cj +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjr +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjalr +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BTBPredPCWrongM +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetWrongE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD +add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {117097 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {48955828 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -584,4 +605,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {117047 ns} {117181 ns} +WaveRestoreZoom {48955732 ns} {48955990 ns} diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 38fd39bc3..6af314646 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -55,6 +55,7 @@ module bpred ( input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br + output logic JumpOrTakenBranchM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br // Report branch prediction status output logic BPPredWrongE, // Prediction is wrong @@ -82,7 +83,18 @@ module bpred ( logic [`XLEN-1:0] PCNext0F; logic [`XLEN-1:0] PCCorrectE; logic [3:0] WrongPredInstrClassD; + + +//************ new resolve issues + logic BTBTargetWrongE; + logic RASTargetWrongE; + logic JumpOrTakenBranchE; + + + logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE; + + // Part 1 branch direction prediction // look into the 2 port Sram model. something is wrong. if (`BPTYPE == "BPTWOBIT") begin:Predictor @@ -200,6 +212,7 @@ module bpred ( flopenrc #(4) InstrClassRegM(clk, reset, FlushM, ~StallM, InstrClassE, InstrClassM); flopenrc #(4) InstrClassRegW(clk, reset, FlushW, ~StallW, InstrClassM, InstrClassW); flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM); + flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM); // branch predictor flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM, @@ -234,9 +247,13 @@ module bpred ( assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | BPPredClassNonCFIWrongE; // If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter. - assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE; + //assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE; + //assign BTBPredPCWrongE = TargetWrongE & (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PCSrcE; + assign BTBPredPCWrongE = BTBTargetWrongE; + // similar with RAS. Over counts ras if the class prediction was wrong. - assign RASPredPCWrongE = InstrClassE[2] & PredictionPCWrongE; + //assign RASPredPCWrongE = TargetWrongE & InstrClassE[2] & PCSrcE; + assign RASPredPCWrongE = RASTargetWrongE; // Finally if the real instruction class is non CFI but the predictor said it was we need to count. assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE; @@ -260,10 +277,23 @@ module bpred ( // end // performance counters - // 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) + // 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) // Correct now // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) // 3. target ras (ras target wrong / class[2]) // 4. direction (br dir wrong / class[0]) + assign BTBTargetWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE; + assign RASTargetWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE; + + assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1] | InstrClassE[3]; + + flopenrc #(`XLEN) BTBTargetDReg(clk, reset, FlushD, ~StallD, PredPCF, PredPCD); + flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, PredPCD, PredPCE); + + flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); + flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); + + + endmodule diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 26227bb9b..9be88d568 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -60,6 +60,7 @@ module ifu ( output logic [`XLEN-1:0] PCM, // Memory stage instruction address // branch predictor output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br + output logic JumpOrTakenBranchM, output logic DirPredictionWrongM, // Prediction direction is wrong output logic BTBPredPCWrongM, // Prediction target wrong output logic RASPredPCWrongM, // RAS prediction is wrong @@ -327,7 +328,7 @@ module ifu ( .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE, - .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, + .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM); end else begin : bpred diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index d6118e203..9a91d371e 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -62,6 +62,7 @@ module csr #(parameter input logic RASPredPCWrongM, input logic PredictionInstrClassWrongM, input logic [3:0] InstrClassM, + input logic JumpOrTakenBranchM, // actual instruction class input logic DCacheMiss, input logic DCacheAccess, input logic ICacheMiss, @@ -255,7 +256,7 @@ module csr #(parameter if (`ZICOUNTERS_SUPPORTED) begin:counters csrc counters(.clk, .reset, .StallE, .StallM, .FlushM, .InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM, - .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, + .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, .JumpOrTakenBranchM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .CSRAdrM, .PrivilegeModeW, .CSRWriteValM, .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW, diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index de5743858..83e3ccdfe 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -49,6 +49,7 @@ module csrc #(parameter input logic RASPredPCWrongM, input logic PredictionInstrClassWrongM, input logic [3:0] InstrClassM, + input logic JumpOrTakenBranchM, // actual instruction class input logic DCacheMiss, input logic DCacheAccess, input logic ICacheMiss, @@ -87,7 +88,7 @@ module csrc #(parameter assign CounterEvent[4] = DirPredictionWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction assign CounterEvent[6] = BTBPredPCWrongM & InstrValidNotFlushedM; // branch predictor wrong target - assign CounterEvent[7] = (InstrClassM[3] | InstrClassM[1]) & InstrValidNotFlushedM; // jump instructions + assign CounterEvent[7] = JumpOrTakenBranchM & InstrValidNotFlushedM; // jump or taken branch instructions assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address assign CounterEvent[9] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 32ef2eb56..c3f321753 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -51,6 +51,7 @@ module privileged ( input logic RASPredPCWrongM, // return adddress stack guessed wrong target input logic PredictionInstrClassWrongM, // branch predictor guessed wrong instruction class input logic [3:0] InstrClassM, // actual instruction class + input logic JumpOrTakenBranchM, // actual instruction class input logic DCacheMiss, // data cache miss input logic DCacheAccess, // data cache accessed (hit or miss) input logic ICacheMiss, // instruction cache miss @@ -124,7 +125,7 @@ module privileged ( .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, - .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, + .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .JumpOrTakenBranchM, .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM, .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 2b71851f5..c6f5240a3 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -161,6 +161,7 @@ module wallypipelinedcore ( logic BigEndianM; logic FCvtIntE; logic CommittedF; + logic JumpOrTakenBranchM; // Bit manipulation unit logic [`XLEN-1:0] BMUResultE; // Bit manipuation result BMU -> IEU @@ -177,7 +178,7 @@ module wallypipelinedcore ( .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, // Mem .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM, - .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, + .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, // Faults out .IllegalBaseInstrFaultD, .InstrPageFaultF, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM, @@ -291,7 +292,7 @@ module wallypipelinedcore ( .FRegWriteM, .LoadStallD, .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, - .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM, + .InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM, .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, From 6c86c0389c16eede5f474d15f2cfd0677b003663 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 27 Jan 2023 11:34:45 -0600 Subject: [PATCH 20/38] Very hacky. But I think gshare is now correct with respect to repair on instruction class miss prediction. --- pipelined/regression/wave.do | 30 +++++++++++++++++-- pipelined/src/ifu/brpred/bpred.sv | 2 +- pipelined/src/ifu/brpred/speculativegshare.sv | 19 ++++++++---- 3 files changed, 42 insertions(+), 9 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 1e34435a5..bfa161dad 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -588,8 +588,34 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF +add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF +add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD +add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE +add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM +add wave -noupdate -expand -group ghr -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF +add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD +add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE +add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {48955828 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {2337 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -605,4 +631,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {48955732 ns} {48955990 ns} +WaveRestoreZoom {2195 ns} {2479 ns} diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 6af314646..3fd021574 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -28,7 +28,7 @@ `include "wally-config.vh" -`define INSTR_CLASS_PRED 0 +`define INSTR_CLASS_PRED 1 module bpred ( input logic clk, reset, diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index b72aacb44..691693af6 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -51,7 +51,8 @@ module speculativegshare logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; - logic [k-1:0] GHRF; + logic [k-1:0] GHRF, OldGHRF; + logic OldGHRExtraF; logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; logic [k-1:0] GHRNextF; logic [k:-1] GHRNextD, OldGHRD; @@ -105,17 +106,23 @@ module speculativegshare satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); // GHR pipeline - assign GHRNextF = FlushD ? GHRNextD[k:1] : + assign GHRNextF = FlushD ? (BranchInstrE ? GHRNextD[k:1] : GHRNextD[k-1:0]) : BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : GHRF; - flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); + flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF); + flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF); + assign GHRF = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right + WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-1:0], OldGHRExtraF} : // shift left **** missing bit + OldGHRF[k:0]; assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]}; + flopenr #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD); - assign GHRD = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right - WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left - OldGHRD[k:0]; + //assign GHRD = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right + // WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left + // OldGHRD[k:0]; + assign GHRD = OldGHRD[k:0]; assign GHRNextE = FlushE ? GHRNextM : GHRD; flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE); From cf49c7ddc12f7862643707bda3cc0cc33d4c13f6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 27 Jan 2023 13:13:55 -0600 Subject: [PATCH 21/38] Found issue with branch predictor. --- pipelined/src/ifu/brpred/speculativegshare.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 691693af6..00a49ce24 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -113,8 +113,8 @@ module speculativegshare flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF); flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF); assign GHRF = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right - WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-1:0], OldGHRExtraF} : // shift left **** missing bit - OldGHRF[k:0]; + WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF} : // shift left **** missing bit + OldGHRF[k-1:0]; assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]}; From 121fbd9646bd0797b3f0fdf12cac929390d0f4a7 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 27 Jan 2023 15:28:31 -0600 Subject: [PATCH 22/38] Removed pessimistic x propagation issue for wally32priv test in the branch predictor. --- pipelined/src/ifu/brpred/speculativegshare.sv | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 00a49ce24..f1810f627 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -106,9 +106,21 @@ module speculativegshare satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); // GHR pipeline + // this version fails the regression test do to pessimistic x propagation. +/* -----\/----- EXCLUDED -----\/----- assign GHRNextF = FlushD ? (BranchInstrE ? GHRNextD[k:1] : GHRNextD[k-1:0]) : BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : GHRF; + -----/\----- EXCLUDED -----/\----- */ + + always_comb begin + if(FlushD) begin + if(BranchInstrE) GHRNextF = GHRNextD[k:1]; + else GHRNextF = GHRNextD[k-1:0]; + end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]}; + else GHRNextF = GHRF; + end + flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF); flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF); From a953954909142baadfcaf0572fe6bba75aa5bfd3 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 27 Jan 2023 16:40:20 -0600 Subject: [PATCH 23/38] Clarified gshare bp. --- pipelined/src/ifu/brpred/speculativegshare.sv | 21 +++++++------------ 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index f1810f627..85cb3654c 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -55,7 +55,7 @@ module speculativegshare logic OldGHRExtraF; logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; logic [k-1:0] GHRNextF; - logic [k:-1] GHRNextD, OldGHRD; + logic [k:0] GHRNextD; logic [k:0] GHRNextE, GHRNextM, GHRNextW; logic [k-1:0] IndexNextF, IndexF; logic [k-1:0] IndexD, IndexE; @@ -107,11 +107,9 @@ module speculativegshare // GHR pipeline // this version fails the regression test do to pessimistic x propagation. -/* -----\/----- EXCLUDED -----\/----- - assign GHRNextF = FlushD ? (BranchInstrE ? GHRNextD[k:1] : GHRNextD[k-1:0]) : - BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : - GHRF; - -----/\----- EXCLUDED -----/\----- */ + // assign GHRNextF = FlushD ? (BranchInstrE ? GHRNextD[k:1] : GHRNextD[k-1:0]) : + // BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : + // GHRF; always_comb begin if(FlushD) begin @@ -121,20 +119,15 @@ module speculativegshare else GHRNextF = GHRF; end - flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF); flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF); assign GHRF = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right - WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF} : // shift left **** missing bit + WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF}: // shift left OldGHRF[k-1:0]; - assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]}; + assign GHRNextD = FlushD ? {GHRNextE} : {DirPredictionF[1], GHRF}; - flopenr #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD); - //assign GHRD = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right - // WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left - // OldGHRD[k:0]; - assign GHRD = OldGHRD[k:0]; + flopenr #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); assign GHRNextE = FlushE ? GHRNextM : GHRD; flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE); From 3f25123c6358edabf3fa3d7486ce05e542d29853 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 28 Jan 2023 16:14:19 -0600 Subject: [PATCH 24/38] Possible fix for speculative gshare. --- pipelined/regression/wave.do | 78 ++++++++++--------- pipelined/src/ifu/brpred/bpred.sv | 2 +- pipelined/src/ifu/brpred/speculativegshare.sv | 43 +++++----- 3 files changed, 68 insertions(+), 55 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index bfa161dad..b2d2cfd2f 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -61,10 +61,10 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/Inst add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName -add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM -add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM -add wave -noupdate -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM add wave -noupdate -group {WriteBack stage} /testbench/PCW add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName @@ -99,6 +99,7 @@ add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf @@ -573,12 +574,6 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassE add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/CompressedOpcF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/InstrClassF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjal -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cj -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjr -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/DirectClassDecode/cjalr add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BTBPredPCWrongM @@ -588,34 +583,47 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF +add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE +add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF +add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE +add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM +add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE +add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF +add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD +add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE +add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM +add wave -noupdate -expand -group {branch direction} -expand -group ghr -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF +add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD +add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE +add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM +add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextW +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM +add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF -add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF -add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD -add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE -add wave -noupdate -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM -add wave -noupdate -expand -group ghr -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCNextF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TableBTBPredictionF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredPCF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/SelBPPredF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE -add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF -add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD -add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE -add wave -noupdate -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM -add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRF TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {2337 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {5845 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -631,4 +639,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {2195 ns} {2479 ns} +WaveRestoreZoom {5721 ns} {5893 ns} diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 3fd021574..6af314646 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -28,7 +28,7 @@ `include "wally-config.vh" -`define INSTR_CLASS_PRED 1 +`define INSTR_CLASS_PRED 0 module bpred ( input logic clk, reset, diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 85cb3654c..649800975 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -53,10 +53,10 @@ module speculativegshare logic [k-1:0] GHRF, OldGHRF; logic OldGHRExtraF; - logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; - logic [k-1:0] GHRNextF; - logic [k:0] GHRNextD; - logic [k:0] GHRNextE, GHRNextM, GHRNextW; + logic [k-1:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; + logic [k-1:0] GHRNextF; + logic [k-1:0] GHRNextD; + logic [k-1:0] GHRNextE, GHRNextM, GHRNextW; logic [k-1:0] IndexNextF, IndexF; logic [k-1:0] IndexD, IndexE; @@ -113,31 +113,36 @@ module speculativegshare always_comb begin if(FlushD) begin - if(BranchInstrE) GHRNextF = GHRNextD[k:1]; - else GHRNextF = GHRNextD[k-1:0]; + //if(BranchInstrE) GHRNextF = {PCSrcE, GHRNextD[k-1:1]}; + //else GHRNextF = GHRNextD[k-1:0]; + GHRNextF = GHRNextD[k-1:0]; end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]}; else GHRNextF = GHRF; end - - flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF); - flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF); - assign GHRF = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right - WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF}: // shift left - OldGHRF[k-1:0]; + + flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); + //flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF); + //flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF); +// assign GHRF = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right +// WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF}: // shift left +// OldGHRF[k-1:0]; - assign GHRNextD = FlushD ? {GHRNextE} : {DirPredictionF[1], GHRF}; + //assign GHRNextD = FlushD ? {GHRNextE} : {DirPredictionF[1], GHRF[k-1:1]}; + assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0]; - flopenr #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); + flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); - assign GHRNextE = FlushE ? GHRNextM : GHRD; - flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE); - assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE; + assign GHRNextE = DirPredictionWrongE & BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} : // if the branch is not flushed and was mispredicted + FlushE ? GHRNextM : // branch is flushed + GHRD; + flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE); + //assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE; assign GHRNextM = FlushM ? GHRNextW : GHRE; - flopenr #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); + flopenr #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); assign GHRNextW = FlushW ? GHRW : GHRM; - flopenr #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW); + flopenr #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW); assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; From b52990e2ceeb9bb97eab97ee545573098c105928 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 28 Jan 2023 16:42:19 -0600 Subject: [PATCH 25/38] Possible workign instruction class prediction repair. --- pipelined/src/ifu/brpred/speculativegshare.sv | 24 +++++++++---------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 649800975..7760cbef9 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -52,7 +52,7 @@ module speculativegshare logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; logic [k-1:0] GHRF, OldGHRF; - logic OldGHRExtraF; + logic GHRExtraF; logic [k-1:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; logic [k-1:0] GHRNextF; logic [k-1:0] GHRNextD; @@ -113,30 +113,28 @@ module speculativegshare always_comb begin if(FlushD) begin - //if(BranchInstrE) GHRNextF = {PCSrcE, GHRNextD[k-1:1]}; - //else GHRNextF = GHRNextD[k-1:0]; GHRNextF = GHRNextD[k-1:0]; end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]}; else GHRNextF = GHRF; end flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); - //flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF); - //flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF); -// assign GHRF = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right -// WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF}: // shift left -// OldGHRF[k-1:0]; - - //assign GHRNextD = FlushD ? {GHRNextE} : {DirPredictionF[1], GHRF[k-1:1]}; - assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0]; + flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRF[0], GHRExtraF); + + // use with out instruction class prediction + //assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0]; + // with instruction class prediction + assign GHRNextD = FlushD ? GHRNextE[k-1:0] : + WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right + WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], GHRExtraF}: // shift left + GHRF[k-1:0]; flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); - assign GHRNextE = DirPredictionWrongE & BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} : // if the branch is not flushed and was mispredicted + assign GHRNextE = BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} : // if the branch is not flushed FlushE ? GHRNextM : // branch is flushed GHRD; flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE); - //assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE; assign GHRNextM = FlushM ? GHRNextW : GHRE; flopenr #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); From 3ddf95ac6e3d63ed890b5a3f11223cbefc28fc24 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 28 Jan 2023 17:00:50 -0600 Subject: [PATCH 26/38] Found an issue where the btb was not forwarding the valid bit! --- pipelined/src/ifu/brpred/btb.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index 9b6c66b85..20500226a 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -56,6 +56,7 @@ module btb logic [`XLEN-1:0] PredPCD; logic [3:0] PredInstrClassD; // *** copy of reg outside module logic UpdateEn; + logic TablePredValidF; // hashing function for indexing the PC // We have Depth bits to index, but XLEN bits as the input. @@ -93,9 +94,11 @@ module btb end else if ((UpdateEn) & ~StallM & ~FlushM) begin ValidBits[PCEIndex] <= #1 |InstrClassE; end - PredValidF = ValidBits[PCNextFIndex]; + TablePredValidF = ValidBits[PCNextFIndex]; end + assign PredValidF = MatchXF ? 1'b1 : TablePredValidF; + assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE; // An optimization may be using a PC relative address. From 684a7214cbacc3509f778cbe6e6825e9d0a4f137 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 28 Jan 2023 17:50:46 -0600 Subject: [PATCH 27/38] Added another performance counter to track overall branch miss-predictions. --- pipelined/regression/wave.do | 6 ++++-- pipelined/src/ifu/brpred/bpred.sv | 2 +- pipelined/src/ifu/ifu.sv | 3 ++- pipelined/src/privileged/csr.sv | 3 ++- pipelined/src/privileged/csrc.sv | 4 +++- pipelined/src/privileged/privileged.sv | 11 ++++++----- pipelined/src/wally/wallypipelinedcore.sv | 6 +++--- pipelined/testbench/testbench.sv | 3 ++- 8 files changed, 23 insertions(+), 15 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index b2d2cfd2f..cdae10c6b 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -531,6 +531,7 @@ add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -lab add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} +add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {Branch Predictor Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} @@ -622,8 +623,9 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRF +add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {5845 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {217131 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -639,4 +641,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {5721 ns} {5893 ns} +WaveRestoreZoom {135840 ns} {362253 ns} diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 6af314646..639dbcd50 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -59,6 +59,7 @@ module bpred ( // Report branch prediction status output logic BPPredWrongE, // Prediction is wrong + output logic BPPredWrongM, // Prediction is wrong output logic DirPredictionWrongM, // Prediction direction is wrong output logic BTBPredPCWrongM, // Prediction target wrong output logic RASPredPCWrongM, // RAS prediction is wrong @@ -79,7 +80,6 @@ module bpred ( logic SelBPPredF; logic [`XLEN-1:0] BPPredPCF; - logic BPPredWrongM; logic [`XLEN-1:0] PCNext0F; logic [`XLEN-1:0] PCCorrectE; logic [3:0] WrongPredInstrClassD; diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 9be88d568..242fb6944 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -51,6 +51,7 @@ module ifu ( input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address output logic [`XLEN-1:0] PCE, // Execution stage instruction address output logic BPPredWrongE, // Prediction is wrong + output logic BPPredWrongM, // Prediction is wrong // Mem output logic CommittedF, // I$ or bus memory operation started, delay interrupts input logic [`XLEN-1:0] UnalignedPCNextF, // The next PCF, but not aligned to 2 bytes. @@ -328,7 +329,7 @@ module ifu ( .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE, - .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, + .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .BPPredWrongM, .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM); end else begin : bpred diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 9a91d371e..ef4d73cb2 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -61,6 +61,7 @@ module csr #(parameter input logic BTBPredPCWrongM, input logic RASPredPCWrongM, input logic PredictionInstrClassWrongM, + input logic BPPredWrongM, // branch predictor is wrong input logic [3:0] InstrClassM, input logic JumpOrTakenBranchM, // actual instruction class input logic DCacheMiss, @@ -256,7 +257,7 @@ module csr #(parameter if (`ZICOUNTERS_SUPPORTED) begin:counters csrc counters(.clk, .reset, .StallE, .StallM, .FlushM, .InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM, - .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, .JumpOrTakenBranchM, + .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, .JumpOrTakenBranchM, .BPPredWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .CSRAdrM, .PrivilegeModeW, .CSRWriteValM, .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW, diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index 83e3ccdfe..bd5ede793 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -48,6 +48,7 @@ module csrc #(parameter input logic BTBPredPCWrongM, input logic RASPredPCWrongM, input logic PredictionInstrClassWrongM, + input logic BPPredWrongM, // branch predictor is wrong input logic [3:0] InstrClassM, input logic JumpOrTakenBranchM, // actual instruction class input logic DCacheMiss, @@ -96,7 +97,8 @@ module csrc #(parameter assign CounterEvent[12] = DCacheMiss; // data cache miss assign CounterEvent[13] = ICacheAccess; // instruction cache access assign CounterEvent[14] = ICacheMiss; // instruction cache miss - assign CounterEvent[`COUNTERS-1:15] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions + assign CounterEvent[15] = BPPredWrongM; // branch predictor wrong + assign CounterEvent[`COUNTERS-1:16] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions end // Counter update and write logic diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index c3f321753..29d65f131 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -46,10 +46,11 @@ module privileged ( // processor events for performance counter logging input logic FRegWriteM, // instruction will write floating-point registers input logic LoadStallD, // load instruction is stalling - input logic DirPredictionWrongM, // branch predictor guessed wrong directoin - input logic BTBPredPCWrongM, // branch predictor guessed wrong target - input logic RASPredPCWrongM, // return adddress stack guessed wrong target - input logic PredictionInstrClassWrongM, // branch predictor guessed wrong instruction class + input logic DirPredictionWrongM, // branch predictor guessed wrong directoin + input logic BTBPredPCWrongM, // branch predictor guessed wrong target + input logic RASPredPCWrongM, // return adddress stack guessed wrong target + input logic PredictionInstrClassWrongM, // branch predictor guessed wrong instruction class + input logic BPPredWrongM, // branch predictor is wrong input logic [3:0] InstrClassM, // actual instruction class input logic JumpOrTakenBranchM, // actual instruction class input logic DCacheMiss, // data cache miss @@ -124,7 +125,7 @@ module privileged ( .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, - .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, + .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredWrongM, .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .JumpOrTakenBranchM, .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index c6f5240a3..e2f04682a 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -141,7 +141,7 @@ module wallypipelinedcore ( logic LSUHWRITE; logic LSUHREADY; - logic BPPredWrongE; + logic BPPredWrongE, BPPredWrongM; logic DirPredictionWrongM; logic BTBPredPCWrongM; logic RASPredPCWrongM; @@ -175,7 +175,7 @@ module wallypipelinedcore ( .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE, .ICacheAccess, .ICacheMiss, // Execute - .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, + .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, .BPPredWrongM, // Mem .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM, .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM, @@ -290,7 +290,7 @@ module wallypipelinedcore ( .RetM, .TrapM, .sfencevmaM, .InstrValidM, .CommittedM, .CommittedF, .FRegWriteM, .LoadStallD, - .DirPredictionWrongM, .BTBPredPCWrongM, + .DirPredictionWrongM, .BTBPredPCWrongM, .BPPredWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, .InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM, .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 5456ce8b9..1e373de57 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -424,7 +424,8 @@ logic [3:0] dummy; "D Cache Access", "D Cache Miss", "I Cache Access", - "I Cache Miss"}; + "I Cache Miss", + "Br Pred Wrong"}; always @(negedge clk) begin if(DCacheFlushStart & ~DCacheFlushDone) begin for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin From 6945eaf045507b97f175f36374b934d74cfaa6d8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 28 Jan 2023 17:56:56 -0600 Subject: [PATCH 28/38] Fixed bug with the new csr. --- pipelined/src/privileged/csrc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index bd5ede793..94dbcaf48 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -97,7 +97,7 @@ module csrc #(parameter assign CounterEvent[12] = DCacheMiss; // data cache miss assign CounterEvent[13] = ICacheAccess; // instruction cache access assign CounterEvent[14] = ICacheMiss; // instruction cache miss - assign CounterEvent[15] = BPPredWrongM; // branch predictor wrong + assign CounterEvent[15] = BPPredWrongM & InstrValidNotFlushedM; // branch predictor wrong assign CounterEvent[`COUNTERS-1:16] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions end From 9e3074689d161a6e83210795ccbeeb9344fbc94a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 00:33:40 -0600 Subject: [PATCH 29/38] Fixed another bug with the speculative gshare with instruction class prediction. --- pipelined/regression/wave.do | 6 ++++-- pipelined/src/ifu/brpred/speculativegshare.sv | 4 ++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index cdae10c6b..a17bc502e 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -584,6 +584,8 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongM add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE @@ -625,7 +627,7 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/Fl add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRF add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {217131 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {296884 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -641,4 +643,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {135840 ns} {362253 ns} +WaveRestoreZoom {18545889 ns} {18546113 ns} diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 7760cbef9..6cfb56894 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -112,7 +112,7 @@ module speculativegshare // GHRF; always_comb begin - if(FlushD) begin + if(FlushD | DirPredictionWrongE) begin GHRNextF = GHRNextD[k-1:0]; end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]}; else GHRNextF = GHRF; @@ -124,7 +124,7 @@ module speculativegshare // use with out instruction class prediction //assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0]; // with instruction class prediction - assign GHRNextD = FlushD ? GHRNextE[k-1:0] : + assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] : WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], GHRExtraF}: // shift left GHRF[k-1:0]; From c8df460b2842f098a1215ce72599f5391108a967 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 00:49:23 -0600 Subject: [PATCH 30/38] Fixed bug with the btb's valid bit not beind held on a stall. --- pipelined/src/ifu/brpred/btb.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index 20500226a..b8c5c6bcd 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -94,7 +94,7 @@ module btb end else if ((UpdateEn) & ~StallM & ~FlushM) begin ValidBits[PCEIndex] <= #1 |InstrClassE; end - TablePredValidF = ValidBits[PCNextFIndex]; + if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex]; end assign PredValidF = MatchXF ? 1'b1 : TablePredValidF; From 250a8df7c3112bc5e6f3aad30711f9fe8c02bb5b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 00:56:11 -0600 Subject: [PATCH 31/38] Updated testbench for branch logger. --- pipelined/testbench/testbench.sv | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 1e373de57..1c2fbb1f0 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -32,8 +32,8 @@ `include "wally-config.vh" `include "tests.vh" -`define PrintHPMCounters 0 -`define BPRED_LOGGER 0 +`define PrintHPMCounters 1 +`define BPRED_LOGGER 1 module testbench; parameter DEBUG=0; @@ -484,11 +484,13 @@ logic [3:0] dummy; if (`BPRED_LOGGER) begin string direction; int file; + logic PCScrM; + flopenrc #(1) PCSrcMReg(clk, reset, FlushM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM); initial file = $fopen("branch.log", "w"); always @(posedge clk) begin if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin - direction = dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcM ? "t" : "n"; + direction = PCSrcM ? "t" : "n"; $fwrite(file, "%h %s\n", dut.core.PCM, direction); end end From 6afd7f4fac3b43d2e43ae5c106b6d1ff39321a0d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 00:58:50 -0600 Subject: [PATCH 32/38] Fixed bug in the branch logger. --- pipelined/testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 1c2fbb1f0..1acb8f6a4 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -485,7 +485,7 @@ logic [3:0] dummy; string direction; int file; logic PCScrM; - flopenrc #(1) PCSrcMReg(clk, reset, FlushM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM); + flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM); initial file = $fopen("branch.log", "w"); always @(posedge clk) begin From 5c83de4c463290cf919ea9aef8714f1abfb97194 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 00:59:59 -0600 Subject: [PATCH 33/38] Fixed another bug with the branch logger. --- pipelined/testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 1acb8f6a4..8d974f0c0 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -485,7 +485,7 @@ logic [3:0] dummy; string direction; int file; logic PCScrM; - flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM); + flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM); initial file = $fopen("branch.log", "w"); always @(posedge clk) begin From 49a7d10914309c6c2bff0599916ac5809b89b280 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 01:00:52 -0600 Subject: [PATCH 34/38] Fixed typo in testbench branch logger. --- pipelined/testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 8d974f0c0..fd83c79b1 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -484,7 +484,7 @@ logic [3:0] dummy; if (`BPRED_LOGGER) begin string direction; int file; - logic PCScrM; + logic PCSrcM; flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM); initial file = $fopen("branch.log", "w"); From 5fb3a669b15a52d84ea73ac4b2c21e740b064294 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 14:17:45 -0600 Subject: [PATCH 35/38] Updated benchmark parsing script. --- bin/parseHPMC.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index 00dcb308c..35bb9c82e 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -45,7 +45,7 @@ def ComputeBranchTargetMissRate(benchmark): 'Computes and inserts branch target miss prediction rate.' # *** this is wrong in the verilog test bench (nameString, opt, dataDict) = benchmark - branchTargetMissRate = 100.0 * int(dataDict['Br Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump, JR, ret']) + int(dataDict['ret'])) + branchTargetMissRate = 100.0 * int(dataDict['Br Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump, JR, Jal']) + int(dataDict['ret'])) dataDict['BTMR'] = branchTargetMissRate def ComputeRASMissRate(benchmark): From 244885d3fab49b4e81ac04eb562812116c7fa345 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 15:03:25 -0600 Subject: [PATCH 36/38] Found bug in gshare. --- pipelined/config/rv32gc/wally-config.vh | 3 ++- pipelined/src/ifu/brpred/bpred.sv | 2 +- pipelined/src/ifu/brpred/speculativegshare.sv | 9 +++------ pipelined/testbench/testbench.sv | 6 +++--- 4 files changed, 9 insertions(+), 11 deletions(-) diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 4d346e5a6..1a1bec35c 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -132,7 +132,8 @@ `define PLIC_UART_ID 10 `define BPRED_ENABLED 1 -`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index 639dbcd50..497d59876 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -28,7 +28,7 @@ `include "wally-config.vh" -`define INSTR_CLASS_PRED 0 +`define INSTR_CLASS_PRED 1 module bpred ( input logic clk, reset, diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 6cfb56894..c41282d59 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -51,16 +51,15 @@ module speculativegshare logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; - logic [k-1:0] GHRF, OldGHRF; + logic [k-1:0] GHRF; logic GHRExtraF; - logic [k-1:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; + logic [k-1:0] GHRD, GHRE, GHRM, GHRW; logic [k-1:0] GHRNextF; logic [k-1:0] GHRNextD; logic [k-1:0] GHRNextE, GHRNextM, GHRNextW; logic [k-1:0] IndexNextF, IndexF; logic [k-1:0] IndexD, IndexE; - logic [`XLEN-1:0] PCW; logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; @@ -126,7 +125,7 @@ module speculativegshare // with instruction class prediction assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] : WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right - WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], GHRExtraF}: // shift left + WrongPredInstrClassD[0] & ~BranchInstrD ? {GHRF[k-2:0], GHRExtraF}: // shift left GHRF[k-1:0]; flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); @@ -144,6 +143,4 @@ module speculativegshare assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; - flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); - endmodule diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index fd83c79b1..db36d9379 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -32,8 +32,8 @@ `include "wally-config.vh" `include "tests.vh" -`define PrintHPMCounters 1 -`define BPRED_LOGGER 1 +`define PrintHPMCounters 0 +`define BPRED_LOGGER 0 module testbench; parameter DEBUG=0; @@ -408,7 +408,7 @@ logic [3:0] dummy; end // always @ (negedge clk) - if(`PrintHPMCounters) begin + if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin integer HPMCindex; string HPMCnames[] = '{"Mcycle", "------", From 2a336cfb715faf5002e6da3c172b2a98f5e17a23 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 15:06:35 -0600 Subject: [PATCH 37/38] Gshare cleanup. --- pipelined/src/ifu/brpred/speculativegshare.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index c41282d59..e38561fb1 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -106,7 +106,7 @@ module speculativegshare // GHR pipeline // this version fails the regression test do to pessimistic x propagation. - // assign GHRNextF = FlushD ? (BranchInstrE ? GHRNextD[k:1] : GHRNextD[k-1:0]) : + // assign GHRNextF = FlushD | DirPredictionWrongE ? GHRNextD[k-1:0] : // BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : // GHRF; From 7c8b2b685ff0f2d743f0fd845ca8b283c651b8cb Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 29 Jan 2023 15:07:45 -0600 Subject: [PATCH 38/38] gshare cleanup. --- pipelined/src/ifu/brpred/speculativegshare.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index e38561fb1..7f696c452 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -35,7 +35,6 @@ module speculativegshare input logic reset, input logic StallF, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, -// input logic [`XLEN-1:0] LookUpPC, output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update