diff --git a/.gitignore b/.gitignore
index 3a8e8be91..3b0234c18 100644
--- a/.gitignore
+++ b/.gitignore
@@ -98,3 +98,8 @@ tests/custom/crt0/*.a
 fpga/src/sdc/*
 fpga/src/sdc.tar.gz
 fpga/src/CopiedFiles_do_not_add_to_repo/*
+/pipelined/regression/branch.log
+/fpga/generator/sim/imp-funcsim.v
+/fpga/generator/sim/imp-timesim.sdf
+/fpga/generator/sim/imp-timesim.v
+/fpga/generator/sim/syn-funcsim.v
diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py
index 00dcb308c..35bb9c82e 100755
--- a/bin/parseHPMC.py
+++ b/bin/parseHPMC.py
@@ -45,7 +45,7 @@ def ComputeBranchTargetMissRate(benchmark):
     'Computes and inserts branch target miss prediction rate.'
     # *** this is wrong in the verilog test bench
     (nameString, opt, dataDict) = benchmark
-    branchTargetMissRate = 100.0 * int(dataDict['Br Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump, JR, ret']) + int(dataDict['ret']))
+    branchTargetMissRate = 100.0 * int(dataDict['Br Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump, JR, Jal']) + int(dataDict['ret']))
     dataDict['BTMR'] = branchTargetMissRate
 
 def ComputeRASMissRate(benchmark):
diff --git a/gitflow.txt b/gitflow.txt
index 57d79333b..57300830a 100644
--- a/gitflow.txt
+++ b/gitflow.txt
@@ -48,3 +48,6 @@ Create pull request
    1. git pull upstream main          # fetch and merge the upstream openhwgroup/cvw into your local clone
    3. git push                        # sync your fork with the upstream and clone
         
+
+If the pull request need changes, modify accordingly, commit, and push changes back to the fork.
+The pull request will automatically update.
diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh
index 9814a79ee..69ea4b5b2 100644
--- a/pipelined/config/rv32gc/wally-config.vh
+++ b/pipelined/config/rv32gc/wally-config.vh
@@ -132,7 +132,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 1
-`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
 
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/config/rv32imc/wally-config.vh b/pipelined/config/rv32imc/wally-config.vh
index db0e974ad..727a50d57 100644
--- a/pipelined/config/rv32imc/wally-config.vh
+++ b/pipelined/config/rv32imc/wally-config.vh
@@ -132,7 +132,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 0
-`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPRED_SIZE 10
 
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh
index d0877c075..818030f12 100644
--- a/pipelined/config/rv64gc/wally-config.vh
+++ b/pipelined/config/rv64gc/wally-config.vh
@@ -135,9 +135,7 @@
 `define PLIC_UART_ID 10
 
 `define BPRED_SUPPORTED 1
-//`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
-`define BPRED_TYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
-//`define BPRED_TYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
+`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
 `define BPRED_SIZE 10
 
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do
index be29ed870..a17bc502e 100644
--- a/pipelined/regression/wave.do
+++ b/pipelined/regression/wave.do
@@ -1,4 +1,5 @@
 onerror {resume}
+quietly virtual signal -install /testbench/dut/core/ifu/bpred/bpred { /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF[11:7]} rd
 quietly WaveActivateNextPane {} 0
 add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
@@ -36,17 +37,17 @@ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/
 add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
 add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
 add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
-add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
-add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
-add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
-add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
-add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
-add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF
-add wave -noupdate -expand -group PCS /testbench/dut/core/PCF
-add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD
-add wave -noupdate -expand -group PCS /testbench/dut/core/PCE
-add wave -noupdate -expand -group PCS /testbench/dut/core/PCM
-add wave -noupdate -expand -group PCS /testbench/PCW
+add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
+add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
+add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
+add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
+add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
+add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -group PCS /testbench/dut/core/PCF
+add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
+add wave -noupdate -group PCS /testbench/dut/core/PCE
+add wave -noupdate -group PCS /testbench/dut/core/PCM
+add wave -noupdate -group PCS /testbench/PCW
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
 add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
 add wave -noupdate -group {Decode Stage} /testbench/InstrDName
@@ -85,29 +86,20 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
 add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
 add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
 add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
+add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
+add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
+add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
+add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
+add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
+add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
+add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
+add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
 add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
 add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
 add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
@@ -148,20 +140,15 @@ add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
 add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
 add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
 add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
-add wave -noupdate -group AHB -expand -group multicontroller -color Gold /testbench/dut/core/ebu/ebu/CurrState
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUReq
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUReq
-add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/both
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSave
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFURestore
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUDisable
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect
 add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect
-add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/BeatCount
-add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/FinalBeat
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
-add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/Threshold
 add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
 add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS
 add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR
@@ -463,10 +450,6 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/P
 add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
 add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
 add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
-add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
-add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
-add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
-add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF
 add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF
 add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
 add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
@@ -484,7 +467,6 @@ add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
 add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss
 add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
 add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
-add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF
 add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
 add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
 add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
@@ -549,6 +531,7 @@ add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -lab
 add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
 add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
 add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
+add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {Branch Predictor Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
 add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
 add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
 add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
@@ -571,7 +554,6 @@ add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD3E
 add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE
 add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE
 add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/Funct3E
-add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/MDUE
 add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/W64E
 add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/X
 add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Y
@@ -584,27 +566,68 @@ add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions
 add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD
 add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD
 add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchNextX
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchD
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchM
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchW
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrW
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrM
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionF
-add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionW
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PtrQ
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PopF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PushE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RASPCF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RepairD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BTBPredPCWrongM
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD
+add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongM
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
+add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
+add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
+add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE
+add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
+add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
+add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE
+add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
+add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
+add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
+add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
+add wave -noupdate -expand -group {branch direction} -expand -group ghr -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
+add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
+add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD
+add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE
+add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM
+add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextW
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
+add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCNextF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TableBTBPredictionF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredPCF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/SelBPPredF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
+add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRF
+add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {116741 ns} 0}
+WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {5919 ns} 1} {{Cursor 5} {296884 ns} 0}
 quietly wave cursor active 5
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 194
@@ -620,4 +643,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {118528 ns} {128752 ns}
+WaveRestoreZoom {18545889 ns} {18546113 ns}
diff --git a/pipelined/src/ifu/bpred/RAsPredictor.sv b/pipelined/src/ifu/bpred/RAsPredictor.sv
index ae5b31999..d345a5b0c 100644
--- a/pipelined/src/ifu/bpred/RAsPredictor.sv
+++ b/pipelined/src/ifu/bpred/RAsPredictor.sv
@@ -1,13 +1,14 @@
 ///////////////////////////////////////////
 // RASPredictor.sv
 //
-// Written: Ross Thomposn
-// Email: ross1728@gmail.com
-// Created: February 15, 2021
-// Modified: 
+// Written: Ross Thomposn ross1728@gmail.com
+// Created: 15 February 2021
+// Modified: 25 January 2023
 //
 // Purpose: 2 bit saturating counter predictor with parameterized table depth.
 // 
+// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@@ -28,48 +29,59 @@
 
 `include "wally-config.vh"
 
-module RASPredictor #(parameter StackSize = 16) (
+module RASPredictor #(parameter int StackSize = 16 )(
   input  logic             clk,
-  input  logic 				     reset,
-  input  logic 				     PopF,
-  output logic [`XLEN-1:0] RASPCF,
-  input  logic [3:0] 		   WrongPredInstrClassD,
-  input  logic [3:0] 		   InstrClassD,
-  input  logic 				     PushE,
-  input  logic 				     incr,
-  input  logic [`XLEN-1:0] PCLinkE
-);
+  input  logic 			   reset, 
+  input  logic 			   StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
+  input  logic [3:0] 	   WrongPredInstrClassD,                      // Prediction class is wrong
+  input  logic [3:0] 	   InstrClassD, InstrClassE, PredInstrClassF, // Instr class
+  input  logic [`XLEN-1:0] PCLinkE,                                   // PC of instruction after a jal
+  output logic [`XLEN-1:0] RASPCF                                     // Top of the stack
+   );
 
-  // *** need to update so it either doesn't push until the memory stage
-  // or need to repair flushed push.
-  // *** need to repair popped and then flushed returns.
   logic                     CounterEn;
   localparam Depth = $clog2(StackSize);
 
   logic [Depth-1:0]         PtrD, PtrQ, PtrP1, PtrM1;
   logic [StackSize-1:0]     [`XLEN-1:0] memory;
   integer        index;
-  
-  assign CounterEn = PopF | PushE | incr | WrongPredInstrClassD[2];
 
-  assign PtrD = PopF | InstrClassD[2] ? PtrM1 : PtrP1;
+  logic 		 PopF;
+  logic 		 PushE;
+  logic 		 RepairD;
+  logic 		 IncrRepairD, DecRepairD;
+  
+  logic 		 DecrementPtr;
+  
+  assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD;
+
+  assign RepairD = ((WrongPredInstrClassD[2]) & ~StallE & ~FlushE) |  // Wrong class undo increment or decrement.
+				   (~StallE & FlushE & InstrClassD[2]) | // ret in decode flushed
+				   (~StallM & FlushM & InstrClassE[2]) ; // ret in execution flushed
+  
+  assign IncrRepairD = (~StallE & FlushE & InstrClassD[2]) | // ret in decode flushed
+					   (~StallM & FlushM & InstrClassE[2]) | // ret in execution flushed
+					   (WrongPredInstrClassD[2] & ~InstrClassD[2] & ~StallE & ~FlushE); // Guessed it was a ret, but its not
+
+  assign DecRepairD =  (WrongPredInstrClassD[2] & InstrClassD[2] & ~StallE & ~FlushE); // Guessed non ret but is a ret.
+  
+  assign PushE = InstrClassE[3] & ~StallM & ~FlushM;
+    
+  assign CounterEn = PopF | PushE | RepairD;
+
+  assign DecrementPtr = (PopF | DecRepairD) & ~IncrRepairD;
+  mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, PtrD);
 
   assign PtrM1 = PtrQ - 1'b1;
   assign PtrP1 = PtrQ + 1'b1;
-  // may have to handle a PushE and an incr at the same time.
-  // *** what happens if jal is executing and there is a return being flushed in Decode?
 
-  flopenr #(Depth) PTR(.clk(clk),
-      .reset(reset),
-      .en(CounterEn),
-      .d(PtrD),
-      .q(PtrQ));
+  flopenr #(Depth) PTR(clk, reset, CounterEn, PtrD, PtrQ);
 
   // RAS must be reset. 
   always_ff @ (posedge clk) begin
     if(reset) begin
       for(index=0; index<StackSize; index++)
- memory[index] <= {`XLEN{1'b0}};
+		memory[index] <= {`XLEN{1'b0}};
     end else if(PushE) begin
       memory[PtrP1] <= #1 PCLinkE;
     end
diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv
index 22889bb3d..bdb489245 100644
--- a/pipelined/src/ifu/bpred/bpred.sv
+++ b/pipelined/src/ifu/bpred/bpred.sv
@@ -28,6 +28,8 @@
 
 `include "wally-config.vh"
 
+`define INSTR_CLASS_PRED 1
+
 module bpred (
   input  logic             clk, reset,
   input  logic             StallF, StallD, StallE, StallM, StallW,
@@ -46,39 +48,53 @@ module bpred (
   input  logic [`XLEN-1:0] PCE,                       // Execution stage instruction address
   input  logic [`XLEN-1:0] PCM,                       // Memory stage instruction address
 
+  input logic [31:0]       PostSpillInstrRawF,        // Instruction
+
   // Branch and jump outcome
-  input  logic             PCSrcE,                    // Executation stage branch is taken
-  input  logic [`XLEN-1:0] IEUAdrE,                   // The branch/jump target address
-  input  logic [`XLEN-1:0] PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
+  input logic              PCSrcE,                    // Executation stage branch is taken
+  input logic [`XLEN-1:0]  IEUAdrE,                   // The branch/jump target address
+  input logic [`XLEN-1:0]  PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
   output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
+  output logic             JumpOrTakenBranchM,        // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
 
   // Report branch prediction status
   output logic             BPPredWrongE,              // Prediction is wrong
+  output logic             BPPredWrongM,              // Prediction is wrong
   output logic             DirPredictionWrongM,       // Prediction direction is wrong
   output logic             BTBPredPCWrongM,           // Prediction target wrong
   output logic             RASPredPCWrongM,           // RAS prediction is wrong
   output logic             PredictionInstrClassWrongM // Class prediction is wrong
-);
+  );
 
-  logic                     BTBValidF;
+  logic                     PredValidF;
   logic [1:0]               DirPredictionF;
 
-  logic [3:0]               PredInstrClassF, PredInstrClassD, PredInstrClassE;
-  logic [`XLEN-1:0]         BTBPredPCF, RASPCF;
+  logic [3:0]               BTBPredInstrClassF, PredInstrClassF, PredInstrClassD, PredInstrClassE;
+  logic [`XLEN-1:0]         PredPCF, RASPCF;
   logic                     TargetWrongE;
   logic                     FallThroughWrongE;
   logic                     PredictionPCWrongE;
   logic                     PredictionInstrClassWrongE;
-  logic [3:0]               InstrClassD, InstrClassE, InstrClassW;
+  logic [3:0]               InstrClassF, InstrClassD, InstrClassE, InstrClassW;
   logic                     DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
   
   logic                     SelBPPredF;
   logic [`XLEN-1:0]         BPPredPCF;
-  logic                     BPPredWrongM;
   logic [`XLEN-1:0]         PCNext0F;
   logic [`XLEN-1:0] 		PCCorrectE;
   logic [3:0] 				WrongPredInstrClassD;
+
+
+//************ new resolve issues  
+  logic BTBTargetWrongE;
+  logic RASTargetWrongE;
+  logic JumpOrTakenBranchE;
   
+  
+
+  logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE;
+
+
   // Part 1 branch direction prediction
   // look into the 2 port Sram model. something is wrong. 
   if (`BPRED_TYPE == "BPTWOBIT") begin:Predictor
@@ -95,11 +111,11 @@ module bpred (
     speculativeglobalhistory #(10) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
       .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
-      .BranchInstrW(InstrClassW[0]), .PCSrcE);
-    
+      .BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE);
+	    
   end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor
     gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
-      .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
+      .PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE,
       .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
 
   end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor
@@ -128,43 +144,65 @@ module bpred (
   // 1) A direction (1 = Taken, 0 = Not Taken)
   // 2) Any information which is necessary for the predictor to build its next state.
   // For a 2 bit table this is the prediction count.
-  assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & BTBValidF) | 
-         PredInstrClassF[2] |
-         (PredInstrClassF[1] & BTBValidF) ;
 
   // Part 2 Branch target address prediction
   // *** For now the BTB will house the direct and indirect targets
 
-  btb TargetPredictor(.clk(clk),
-          .reset(reset),
-          .*, // Stalls and flushes
-          .PCNextF,
-          .BTBPredPCF,
-          .InstrClass(PredInstrClassF),
-          .Valid(BTBValidF),
-          // update
-          .UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE),
-          .PCE,
+  btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM,
+          .PCNextF, .PCF, .PCD, .PCE,
+          .PredPCF,
+          .BTBPredInstrClassF,
+          .PredValidF,
+          .PredictionInstrClassWrongE,
           .IEUAdrE,
-          .UpdateInvalid(PredictionInstrClassWrongE),
           .InstrClassE);
 
   // Part 3 RAS
   // *** need to add the logic to restore RAS on flushes.  We will use incr for this.
   // *** needs to include flushX
-  RASPredictor RASPredictor(.clk(clk),
-       .reset(reset),
-       .PopF(PredInstrClassF[2] & ~StallF),
-							.WrongPredInstrClassD,
-							.InstrClassD,
-       .RASPCF,
-       .PushE(InstrClassE[3] & ~StallE),
-       .incr(1'b0),
-       .PCLinkE);
+  RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+							.PredInstrClassF, .InstrClassD, .InstrClassE,
+							.WrongPredInstrClassD, .RASPCF, .PCLinkE);
 
-  assign BPPredPCF = PredInstrClassF[2] ? RASPCF : BTBPredPCF;
+  assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF;
 
   // the branch predictor needs a compact decoding of the instruction class.
+  if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode
+	logic [4:0] CompressedOpcF;
+	logic [3:0] InstrClassF;
+	logic 		cjal, cj, cjr, cjalr;
+	
+	assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]};
+
+	assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32;
+	assign cj = CompressedOpcF == 5'h0d;
+	assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
+	assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
+	
+	assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | 
+							(`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7);
+	
+	assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
+							(PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5
+							(`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) ));
+	
+	assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5
+							(`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
+	
+	assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5
+							(`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
+	assign PredInstrClassF = InstrClassF;
+	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | 
+						PredInstrClassF[2] |
+						(PredInstrClassF[1]) ;
+  end else begin
+	assign PredInstrClassF = BTBPredInstrClassF;
+	assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | 
+						PredInstrClassF[2] |
+						(PredInstrClassF[1] & PredValidF) ;
+  end
+  
+
   assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
   assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
   assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
@@ -174,6 +212,7 @@ module bpred (
   flopenrc #(4) InstrClassRegM(clk, reset,  FlushM, ~StallM, InstrClassE, InstrClassM);
   flopenrc #(4) InstrClassRegW(clk, reset,  FlushW, ~StallW, InstrClassM, InstrClassW);
   flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM);
+  flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM);
 
   // branch predictor
   flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM, 
@@ -208,9 +247,13 @@ module bpred (
   assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | BPPredClassNonCFIWrongE;
 
   // If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter.
-  assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1]) & PredictionPCWrongE;
-  // similar with RAS
-  assign RASPredPCWrongE = InstrClassE[2] & PredictionPCWrongE;
+  //assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE;
+  //assign BTBPredPCWrongE = TargetWrongE & (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PCSrcE;
+  assign BTBPredPCWrongE = BTBTargetWrongE;
+  
+  // similar with RAS. Over counts ras if the class prediction was wrong.
+  //assign RASPredPCWrongE = TargetWrongE & InstrClassE[2] & PCSrcE;
+  assign RASPredPCWrongE = RASTargetWrongE;
   // Finally if the real instruction class is non CFI but the predictor said it was we need to count.
   assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE;
 
@@ -232,5 +275,25 @@ module bpred (
   //  end else begin
   //	assign NextValidPCE = PCE;
   //  end
+
+  // performance counters
+  // 1. class         (class wrong / minstret) (PredictionInstrClassWrongM / csr)                    // Correct now
+  // 2. target btb    (btb target wrong / class[0,1,3])  (btb target wrong / (br + j + jal)
+  // 3. target ras    (ras target wrong / class[2])
+  // 4. direction     (br dir wrong / class[0])
+
+  assign BTBTargetWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE;
+  assign RASTargetWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE;
+
+  assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1] | InstrClassE[3];
+  
+  flopenrc #(`XLEN) BTBTargetDReg(clk, reset, FlushD, ~StallD, PredPCF, PredPCD);
+  flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, PredPCD, PredPCE);
+
+  flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
+  flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
+
+  
+  
   
 endmodule
diff --git a/pipelined/src/ifu/bpred/btb.sv b/pipelined/src/ifu/bpred/btb.sv
index c228964da..02c77fab9 100644
--- a/pipelined/src/ifu/bpred/btb.sv
+++ b/pipelined/src/ifu/bpred/btb.sv
@@ -30,79 +30,80 @@
 
 `include "wally-config.vh"
 
-module btb #(parameter Depth = 10) (
+module btb #(parameter int Depth = 10 ) (
   input  logic             clk,
   input  logic             reset,
-  input  logic             StallF, StallE,
-  input  logic [`XLEN-1:0] PCNextF,
-  output logic [`XLEN-1:0] BTBPredPCF,
-  output logic [3:0]       InstrClass,
-  output logic             Valid,
+  input  logic             StallF, StallD, StallM, FlushD, FlushM,
+  input  logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE,                 // PC at various stages
+  output logic [`XLEN-1:0] PredPCF,                                // BTB's guess at PC
+  output logic [3:0]       BTBPredInstrClassF,                        // BTB's guess at instruction class
+  output logic             PredValidF,                             // BTB's guess is valid
   // update
-  input  logic             UpdateEN,
-  input  logic [`XLEN-1:0] PCE,
-  input  logic [`XLEN-1:0] IEUAdrE,
-  input  logic [3:0]       InstrClassE,
-  input  logic             UpdateInvalid
+  input  logic             PredictionInstrClassWrongE,             // BTB's instruction class guess was wrong
+  input  logic [`XLEN-1:0] IEUAdrE,                                // Branch/jump target address to insert into btb
+  input  logic [3:0]       InstrClassE                             // Instruction class to insert into btb
 );
 
   localparam TotalDepth = 2 ** Depth;
   logic [TotalDepth-1:0]    ValidBits;
-  logic [Depth-1:0]         PCNextFIndex, PCEIndex, PCNextFIndexQ, PCEIndexQ;
-  logic                     UpdateENQ;
+  logic [Depth-1:0]         PCNextFIndex, PCFIndex, PCDIndex, PCEIndex;
   logic [`XLEN-1:0] 		ResetPC;
-
-
+  logic 					MatchF, MatchD, MatchE, MatchNextX, MatchXF;
+  logic [`XLEN+3:0] 		ForwardBTBPrediction, ForwardBTBPredictionF;
+  logic [`XLEN+3:0] 		TableBTBPredictionF;
+  logic [`XLEN-1:0] 		PredPCD;  
+  logic [3:0] 				PredInstrClassD;  // *** copy of reg outside module
+  logic 					UpdateEn;
+  logic 					TablePredValidF;
+    
   // hashing function for indexing the PC
   // We have Depth bits to index, but XLEN bits as the input.
   // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if
   // using compressed instructions.  XOR bit 1 with the MSB of index.
+  assign PCFIndex = {PCF[Depth+1] ^ PCF[1], PCF[Depth:2]};
+  assign PCDIndex = {PCD[Depth+1] ^ PCD[1], PCD[Depth:2]};
   assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]};
-  assign ResetPC = `RESET_VECTOR;
-  assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]};  
-  //assign PCNextFIndex = {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]};  
 
-  flopenr #(Depth) PCEIndexReg(.clk(clk),
-        .reset(reset),
-        .en(~StallE),
-        .d(PCEIndex),
-        .q(PCEIndexQ));
+  // must output a valid PC and valid bit during reset.  Because only PCF, not PCNextF is reset, PCNextF is invalid
+  // during reset.  The BTB must produce a non X PC1NextF to allow the simulation to run.
+  // While thie mux could be included in IFU it is not necessary for the IROM/I$/bus.
+  // For now it is optimal to leave it here.
+  assign ResetPC = `RESET_VECTOR;
+  assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; 
+
+  assign MatchF = PCNextFIndex == PCFIndex;
+  assign MatchD = PCNextFIndex == PCDIndex;
+  assign MatchE = PCNextFIndex == PCEIndex;
+  assign MatchNextX = MatchF | MatchD | MatchE;
   
-  // The valid bit must be resetable.
+  flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
+
+  assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} :
+                                MatchD ? {PredInstrClassD, PredPCD} :
+                                {InstrClassE, IEUAdrE} ;
+
+  flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
+
+  assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF;
+
   always_ff @ (posedge clk) begin
     if (reset) begin
       ValidBits <= #1 {TotalDepth{1'b0}};
-    end else 
-    if (UpdateENQ) begin
-      ValidBits[PCEIndexQ] <= #1 ~ UpdateInvalid;
+    end else if ((UpdateEn) & ~StallM & ~FlushM) begin
+      ValidBits[PCEIndex] <= #1 |InstrClassE;
     end
+	if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex];
   end
-  assign Valid = ValidBits[PCNextFIndexQ];
 
+  assign PredValidF = MatchXF ? 1'b1 : TablePredValidF;
+  
+  assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE;
 
-  flopenr #(1) UpdateENReg(.clk(clk),
-     .reset(reset),
-     .en(~StallF),
-     .d(UpdateEN),
-     .q(UpdateENQ));
-
-
-  flopenr #(Depth) LookupPCIndexReg(.clk(clk),
-        .reset(reset),
-        .en(~StallF),
-        .d(PCNextFIndex),
-        .q(PCNextFIndexQ));
-
-
-
-  // the BTB contains the target address.
-  // Another optimization may be using a PC relative address.
-  // *** need to add forwarding.
-
-  // *** optimize for byte write enables
-
+  // An optimization may be using a PC relative address.
   ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
-    .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}),
-     .ce2(~StallE), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1));
+    .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
+     .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1));
+
+  flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {BTBPredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD});
 
 endmodule
diff --git a/pipelined/src/ifu/bpred/globalhistory.sv b/pipelined/src/ifu/bpred/globalhistory.sv
index a8493a8d4..e951a0151 100644
--- a/pipelined/src/ifu/bpred/globalhistory.sv
+++ b/pipelined/src/ifu/bpred/globalhistory.sv
@@ -44,7 +44,7 @@ module globalhistory #(parameter k = 10) (
   logic [1:0]              DirPredictionD, DirPredictionE;
   logic [1:0]              NewDirPredictionE, NewDirPredictionM;
 
-  logic [k-1:0]            GHRF, GHRD, GHRE, GHRM, GHR;
+  logic [k-1:0]            GHRF, GHRD, GHRE, GHR;
   logic [k-1:0]            GHRNext;
   logic                    PCSrcM;
   
@@ -53,9 +53,9 @@ module globalhistory #(parameter k = 10) (
     .ce1(~StallF), .ce2(~StallM & ~FlushM),
     .ra1(GHR),
     .rd1(DirPredictionF),
-    .wa2(GHRM),
-    .wd2(NewDirPredictionM),
-    .we2(BranchInstrM & ~StallM & ~FlushM),
+    .wa2(GHRE),
+    .wd2(NewDirPredictionE),
+    .we2(BranchInstrE & ~StallM & ~FlushM),
     .bwe2(1'b1));
 
   flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
@@ -74,7 +74,6 @@ module globalhistory #(parameter k = 10) (
   flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
   flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
   flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
-  flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
 
 
 endmodule
diff --git a/pipelined/src/ifu/bpred/gshare.sv b/pipelined/src/ifu/bpred/gshare.sv
index 2fb0c6eaf..fde1a0825 100644
--- a/pipelined/src/ifu/bpred/gshare.sv
+++ b/pipelined/src/ifu/bpred/gshare.sv
@@ -33,32 +33,31 @@ module gshare #(parameter k = 10) (
   input logic             reset,
   input logic             StallF, StallD, StallE, StallM, 
   input logic             FlushD, FlushE, FlushM,
-//   input logic [`XLEN-1:0] LookUpPC,
   output logic [1:0]      DirPredictionF, 
   output logic            DirPredictionWrongE,
   // update
-  input logic [`XLEN-1:0] PCNextF, PCM,
+  input logic [`XLEN-1:0] PCNextF, PCE,
   input logic             BranchInstrE, BranchInstrM, PCSrcE
 );
 
-  logic [k-1:0]            IndexNextF, IndexM;
+  logic [k-1:0]            IndexNextF, IndexE;
   logic [1:0]              DirPredictionD, DirPredictionE;
   logic [1:0]              NewDirPredictionE, NewDirPredictionM;
 
-  logic [k-1:0]            GHRF, GHRD, GHRE, GHRM, GHR;
+  logic [k-1:0]            GHRF, GHRD, GHRE, GHR;
   logic [k-1:0]            GHRNext;
   logic                    PCSrcM;
 
   assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
-  assign IndexM = GHRM & {PCM[k+1] ^ PCM[1], PCM[k:2]};
+  assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]};
   
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
     .ce1(~StallF), .ce2(~StallM & ~FlushM),
     .ra1(IndexNextF),
     .rd1(DirPredictionF),
-    .wa2(IndexM),
-    .wd2(NewDirPredictionM),
-    .we2(BranchInstrM & ~StallM & ~FlushM),
+    .wa2(IndexE),
+    .wd2(NewDirPredictionE),
+    .we2(BranchInstrE & ~StallM & ~FlushM),
     .bwe2(1'b1));
 
   flopenrc #(2) PredictionRegD(clk, reset,  FlushD, ~StallD, DirPredictionF, DirPredictionD);
@@ -76,7 +75,6 @@ module gshare #(parameter k = 10) (
   flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
   flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
   flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
-  flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
 
 
 endmodule
diff --git a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv b/pipelined/src/ifu/bpred/speculativeglobalhistory.sv
index 232351c86..47203dbdd 100644
--- a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv
+++ b/pipelined/src/ifu/bpred/speculativeglobalhistory.sv
@@ -33,57 +33,60 @@ module speculativeglobalhistory #(parameter k = 10) (
   input logic             reset,
   input logic             StallF, StallD, StallE, StallM, StallW, 
   input logic             FlushD, FlushE, FlushM, FlushW,
-//   input logic [`XLEN-1:0] LookUpPC,
   output logic [1:0]      DirPredictionF, 
   output logic            DirPredictionWrongE,
   // update
   input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
-  input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, 
+  input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
+  input logic [3:0]       WrongPredInstrClassD, 
   input logic             PCSrcE
 );
 
-  logic                    MatchF, MatchD, MatchE, MatchM, MatchW;
+  logic                    MatchF, MatchD, MatchE;
   logic                    MatchNextX, MatchXF;
 
   logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
-  logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW;
+  logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE;
 
   logic [k-1:0]            GHRF;
   logic [k:0]              GHRD, OldGHRE, GHRE, GHRM, GHRW;
   logic [k-1:0]            GHRNextF;
-  logic [k:0]              GHRNextD, GHRNextE, GHRNextM, GHRNextW;
-  logic                    PCSrcM, PCSrcW;
+  logic [k:-1] 			   GHRNextD, OldGHRD;
+  logic [k:0]              GHRNextE, GHRNextM, GHRNextW;
+  logic [k-1:0]            IndexNextF, IndexF;
+  logic [k-1:0]            IndexD, IndexE;
+  
   logic [`XLEN-1:0]        PCW;
 
   logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
   
+  assign IndexNextF = GHRNextF;
+  assign IndexF = GHRF;
+  assign IndexD = GHRD[k-1:0];
+  assign IndexE = GHRE[k-1:0];
       
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
-    .ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
-    .ra1(GHRNextF),
+    .ce1(~StallF | reset), .ce2(~StallM & ~FlushM),
+    .ra1(IndexNextF),
     .rd1(TableDirPredictionF),
-    .wa2(GHRW[k-1:0]),
-    .wd2(NewDirPredictionW),
-    .we2(BranchInstrW & ~StallW & ~FlushW),
+    .wa2(IndexE),
+    .wd2(NewDirPredictionE),
+    .we2(BranchInstrE & ~StallM & ~FlushM),
     .bwe2(1'b1));
 
   // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
-  //  and then register for use in the Fetch stage.
-  assign MatchF = BranchInstrF & ~FlushD & (GHRNextF == GHRF);
-  assign MatchD = BranchInstrD & ~FlushE & (GHRNextF == GHRD[k-1:0]);
-  assign MatchE = BranchInstrE & ~FlushM & (GHRNextF == GHRE[k-1:0]);
-  assign MatchM = BranchInstrM & ~FlushW & (GHRNextF == GHRM[k-1:0]);
-  assign MatchW = BranchInstrW & (GHRNextF == GHRW[k-1:0]);
-  assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW;
+  // and then register for use in the Fetch stage.
+  assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
+  assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
+  assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
+  assign MatchNextX = MatchF | MatchD | MatchE;
 
   flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
 
   assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
                                    MatchD ? NewDirPredictionD :
-                                   MatchE ? NewDirPredictionE :
-                                   MatchM ? NewDirPredictionM :
-                                   NewDirPredictionW;
-
+                                   NewDirPredictionE ;
+  
   flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
 
   assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
@@ -93,16 +96,11 @@ module speculativeglobalhistory #(parameter k = 10) (
   flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
 
   // New prediction pipeline
-  satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF));
+  assign NewDirPredictionF = {DirPredictionF[1], DirPredictionF[1]};
+  
   flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
   satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
-  flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
-  flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW);
 
-  // PCSrc pipeline
-  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
-  flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
-  
   // GHR pipeline
   assign GHRNextF = FlushD ?  GHRNextD[k:1] :
                     BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
@@ -110,8 +108,11 @@ module speculativeglobalhistory #(parameter k = 10) (
 
   flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
   
-  assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF};
-  flopenr  #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
+  assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]};
+  flopenr  #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD);
+  assign GHRD = WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right
+				WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left
+				OldGHRD[k:0];
 
   assign GHRNextE = FlushE ? GHRNextM : GHRD;
   flopenr  #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv
index 98b590bed..e4d624382 100644
--- a/pipelined/src/ifu/bpred/speculativegshare.sv
+++ b/pipelined/src/ifu/bpred/speculativegshare.sv
@@ -28,37 +28,35 @@
 
 `include "wally-config.vh"
 
-module speculativegshare #(parameter k = 10) (
-  input  logic             clk,
-  input  logic             reset,
-  input  logic             StallF, StallD, StallE, StallM, StallW, 
-  input  logic             FlushD, FlushE, FlushM, FlushW,
-//   input logic [`XLEN-1:0] LookUpPC,
-  output logic [1:0]       DirPredictionF, 
-  output logic             DirPredictionWrongE,
+module speculativegshare #(parameter int k = 10 ) (
+  input logic             clk,
+  input logic             reset,
+  input logic             StallF, StallD, StallE, StallM, StallW, 
+  input logic             FlushD, FlushE, FlushM, FlushW,
+  output logic [1:0]      DirPredictionF, 
+  output logic            DirPredictionWrongE,
   // update
-  input  logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
-  input  logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
-  input  logic [3:0]       WrongPredInstrClassD, 
-  input  logic             PCSrcE
+  input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
+  input logic             BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
+  input logic [3:0]       WrongPredInstrClassD, 
+  input logic             PCSrcE
 );
 
-  logic                    MatchF, MatchD, MatchE, MatchM;
+  logic                    MatchF, MatchD, MatchE;
   logic                    MatchNextX, MatchXF;
 
   logic [1:0]              TableDirPredictionF, DirPredictionD, DirPredictionE;
-  logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM;
+  logic [1:0]              NewDirPredictionF, NewDirPredictionD, NewDirPredictionE;
 
   logic [k-1:0]            GHRF;
-  logic [k:0]              GHRD, OldGHRE, GHRE, GHRM, GHRW;
-  logic [k-1:0]            GHRNextF;
-  logic [k:-1] 			   GHRNextD, OldGHRD;
-  logic [k:0]              GHRNextE, GHRNextM, GHRNextW;
+  logic 				   GHRExtraF;
+  logic [k-1:0] 		   GHRD, GHRE, GHRM, GHRW;
+  logic [k-1:0] 		   GHRNextF;
+  logic [k-1:0] 		   GHRNextD;
+  logic [k-1:0] 		   GHRNextE, GHRNextM, GHRNextW;
   logic [k-1:0]            IndexNextF, IndexF;
-  logic [k-1:0]            IndexD, IndexE, IndexM;
+  logic [k-1:0]            IndexD, IndexE;
   
-  logic                    PCSrcM, PCSrcW;
-  logic [`XLEN-1:0]        PCW;
 
   logic [1:0]              ForwardNewDirPrediction, ForwardDirPredictionF;
   
@@ -66,15 +64,14 @@ module speculativegshare #(parameter k = 10) (
   assign IndexF = GHRF        ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
   assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
   assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
-  assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
       
   ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
-    .ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
+    .ce1(~StallF | reset), .ce2(~StallM & ~FlushM),
     .ra1(IndexNextF),
     .rd1(TableDirPredictionF),
-    .wa2(IndexM),
-    .wd2(NewDirPredictionM),
-    .we2(BranchInstrM & ~StallW & ~FlushW),
+    .wa2(IndexE),
+    .wd2(NewDirPredictionE),
+    .we2(BranchInstrE & ~StallM & ~FlushM),
     .bwe2(1'b1));
 
   // if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
@@ -82,15 +79,13 @@ module speculativegshare #(parameter k = 10) (
   assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
   assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
   assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
-  assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
-  assign MatchNextX = MatchF | MatchD | MatchE | MatchM;
+  assign MatchNextX = MatchF | MatchD | MatchE;
 
   flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
 
   assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
                                    MatchD ? NewDirPredictionD :
-                                   MatchE ? NewDirPredictionE :
-                                   NewDirPredictionM;
+                                   NewDirPredictionE ;
   
   flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
 
@@ -105,37 +100,44 @@ module speculativegshare #(parameter k = 10) (
   
   flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
   satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
-  flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
 
-  // PCSrc pipeline
-  flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
-  flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
-  
   // GHR pipeline
-  assign GHRNextF = FlushD ?  GHRNextD[k:1] :
-                    BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
-                    GHRF;
+  // this version fails the regression test do to pessimistic x propagation.
+  // assign GHRNextF = FlushD | DirPredictionWrongE ?  GHRNextD[k-1:0] :
+  //                  BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
+  //                  GHRF;
 
-  flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
-  
-  assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]};
-  flopenr  #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD);
-  assign GHRD = WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right
-				WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left
-				OldGHRD[k:0];
+  always_comb begin
+	if(FlushD | DirPredictionWrongE) begin
+	  GHRNextF = GHRNextD[k-1:0];
+	end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]};
+	else GHRNextF = GHRF;
+  end
 
-  assign GHRNextE = FlushE ? GHRNextM : GHRD;
-  flopenr  #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
-  assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
+  flopenr  #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);	
+  flopenr  #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRF[0], GHRExtraF);
+
+  // use with out instruction class prediction
+  //assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0];
+  // with instruction class prediction
+  assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] :
+					WrongPredInstrClassD[0] & BranchInstrD  ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right
+  					WrongPredInstrClassD[0] & ~BranchInstrD ? {GHRF[k-2:0], GHRExtraF}:       // shift left
+					GHRF[k-1:0];
+
+  flopenr  #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
+
+  assign GHRNextE = BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} :   // if the branch is not flushed
+					FlushE ? GHRNextM :                                // branch is flushed
+					GHRD;
+  flopenr  #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE);
 
   assign GHRNextM = FlushM ? GHRNextW : GHRE;
-  flopenr  #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
+  flopenr  #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
 
   assign GHRNextW = FlushW ? GHRW : GHRM;
-  flopenr  #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW);
+  flopenr  #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW);
   
   assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
 
-  flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
-
 endmodule
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 3e3e59743..79f16c59a 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -51,6 +51,7 @@ module ifu (
   input  logic [`XLEN-1:0] 	IEUAdrE,                                  // The branch/jump target address
   output logic [`XLEN-1:0] 	PCE,                                      // Execution stage instruction address
   output logic 				BPPredWrongE,                             // Prediction is wrong
+  output logic 				BPPredWrongM,                             // Prediction is wrong
   // Mem
   output logic              CommittedF,                               // I$ or bus memory operation started, delay interrupts
   input  logic [`XLEN-1:0] 	UnalignedPCNextF,                         // The next PCF, but not aligned to 2 bytes. 
@@ -60,6 +61,7 @@ module ifu (
   output logic [`XLEN-1:0] 	PCM,                                      // Memory stage instruction address
   // branch predictor
   output logic [3:0] 		InstrClassM,                              // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
+  output logic              JumpOrTakenBranchM,
   output logic 				DirPredictionWrongM,                      // Prediction direction is wrong
   output logic 				BTBPredPCWrongM,                          // Prediction target wrong
   output logic 				RASPredPCWrongM,                          // RAS prediction is wrong
@@ -115,7 +117,7 @@ module ifu (
   logic [31:0] NextInstrD, NextInstrE;                                // Instruction into the next stage after possible stage flush
 
 
-  logic 					   CacheableF;                            // PMA indicates isntruction address is cacheable
+  logic 					   CacheableF;                            // PMA indicates instruction address is cacheable
   logic 					   SelNextSpillF;                         // In a spill, stall pipeline and gate local stallF
   logic 					   BusStall;                              // Bus interface busy with multicycle operation
   logic 					   ICacheStallF;                          // I$ busy with multicycle operation
@@ -327,7 +329,7 @@ module ifu (
                 .StallF, .StallD, .StallE, .StallM, .StallW,
                 .FlushD, .FlushE, .FlushM, .FlushW,
                 .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE,
-                .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE,
+                .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .BPPredWrongM,
                 .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM);
 
   end else begin : bpred
diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv
index d6118e203..ef4d73cb2 100644
--- a/pipelined/src/privileged/csr.sv
+++ b/pipelined/src/privileged/csr.sv
@@ -61,7 +61,9 @@ module csr #(parameter
   input  logic             BTBPredPCWrongM,
   input  logic             RASPredPCWrongM,
   input  logic             PredictionInstrClassWrongM,
+  input  logic             BPPredWrongM,                              // branch predictor is wrong
   input  logic [3:0]       InstrClassM,
+  input  logic             JumpOrTakenBranchM,                               // actual instruction class
   input  logic             DCacheMiss,
   input  logic             DCacheAccess,
   input  logic             ICacheMiss,
@@ -255,7 +257,7 @@ module csr #(parameter
   if (`ZICOUNTERS_SUPPORTED) begin:counters
     csrc  counters(.clk, .reset, .StallE, .StallM, .FlushM,
       .InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
-      .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
+      .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, .JumpOrTakenBranchM, .BPPredWrongM,
       .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
       .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
       .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv
index de5743858..94dbcaf48 100644
--- a/pipelined/src/privileged/csrc.sv
+++ b/pipelined/src/privileged/csrc.sv
@@ -48,7 +48,9 @@ module csrc #(parameter
   input  logic 	            BTBPredPCWrongM,
   input  logic 	            RASPredPCWrongM,
   input  logic 	            PredictionInstrClassWrongM,
+  input  logic              BPPredWrongM,                              // branch predictor is wrong
   input  logic [3:0]        InstrClassM,
+  input  logic              JumpOrTakenBranchM,                               // actual instruction class
   input  logic 	            DCacheMiss,
   input  logic 	            DCacheAccess,
   input  logic 	            ICacheMiss,
@@ -87,7 +89,7 @@ module csrc #(parameter
     assign CounterEvent[4] = DirPredictionWrongM & InstrValidNotFlushedM;               // Branch predictor wrong direction
     assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM;                    // branch instruction
     assign CounterEvent[6] = BTBPredPCWrongM & InstrValidNotFlushedM;                   // branch predictor wrong target
-    assign CounterEvent[7] = (InstrClassM[3] | InstrClassM[1]) & InstrValidNotFlushedM; // jump instructions
+    assign CounterEvent[7] = JumpOrTakenBranchM & InstrValidNotFlushedM;                // jump or taken branch instructions
     assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM;                   // return address stack wrong address
     assign CounterEvent[9] = InstrClassM[2] & InstrValidNotFlushedM;                    // return instructions
     assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM;       // instruction class predictor wrong
@@ -95,7 +97,8 @@ module csrc #(parameter
     assign CounterEvent[12] = DCacheMiss;                                               // data cache miss
     assign CounterEvent[13] = ICacheAccess;                                             // instruction cache access
     assign CounterEvent[14] = ICacheMiss;                                               // instruction cache miss
-    assign CounterEvent[`COUNTERS-1:15] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
+	assign CounterEvent[15] = BPPredWrongM & InstrValidNotFlushedM;                     // branch predictor wrong
+    assign CounterEvent[`COUNTERS-1:16] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
   end
   
   // Counter update and write logic
diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv
index 32ef2eb56..29d65f131 100644
--- a/pipelined/src/privileged/privileged.sv
+++ b/pipelined/src/privileged/privileged.sv
@@ -46,11 +46,13 @@ module privileged (
   // processor events for performance counter logging
   input  logic             FRegWriteM,                                // instruction will write floating-point registers
   input  logic             LoadStallD,                                // load instruction is stalling
-  input  logic 		         DirPredictionWrongM,                       // branch predictor guessed wrong directoin
-  input  logic 		         BTBPredPCWrongM,                           // branch predictor guessed wrong target
-  input  logic 		         RASPredPCWrongM,                           // return adddress stack guessed wrong target
-  input  logic 		         PredictionInstrClassWrongM,                // branch predictor guessed wrong instruction class
+  input  logic 		         DirPredictionWrongM,                     // branch predictor guessed wrong directoin
+  input  logic 		         BTBPredPCWrongM,                         // branch predictor guessed wrong target
+  input  logic 		         RASPredPCWrongM,                         // return adddress stack guessed wrong target
+  input  logic 		         PredictionInstrClassWrongM,              // branch predictor guessed wrong instruction class
+  input  logic             BPPredWrongM,                              // branch predictor is wrong
   input  logic [3:0]       InstrClassM,                               // actual instruction class
+  input  logic             JumpOrTakenBranchM,                               // actual instruction class
   input  logic             DCacheMiss,                                // data cache miss
   input  logic             DCacheAccess,                              // data cache accessed (hit or miss)
   input  logic             ICacheMiss,                                // instruction cache miss
@@ -123,8 +125,8 @@ module privileged (
     .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM,
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
     .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD,
-    .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, 
-    .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
+    .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredWrongM,
+    .PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .JumpOrTakenBranchM,
     .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,
     .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
     .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,
diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv
index b50746477..aae48f29d 100644
--- a/pipelined/src/wally/wallypipelinedcore.sv
+++ b/pipelined/src/wally/wallypipelinedcore.sv
@@ -140,7 +140,7 @@ module wallypipelinedcore (
   logic                          LSUHWRITE;
   logic                          LSUHREADY;
   
-  logic                          BPPredWrongE;
+  logic                          BPPredWrongE, BPPredWrongM;
   logic                          DirPredictionWrongM;
   logic                          BTBPredPCWrongM;
   logic                          RASPredPCWrongM;
@@ -160,7 +160,8 @@ module wallypipelinedcore (
   logic                          BigEndianM;
   logic                          FCvtIntE;
   logic                          CommittedF;
-   
+  logic 						 JumpOrTakenBranchM;
+  
   // instruction fetch unit: PC, branch prediction, instruction cache
   ifu ifu(.clk, .reset,
     .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
@@ -169,10 +170,10 @@ module wallypipelinedcore (
     .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
     .ICacheAccess, .ICacheMiss,
     // Execute
-    .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, 
+    .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE,  .BPPredWrongM, 
     // Mem
     .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
-    .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM,
+    .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM,
     .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
     // Faults out
     .IllegalBaseInstrFaultD, .InstrPageFaultF, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
@@ -284,9 +285,9 @@ module wallypipelinedcore (
       .RetM, .TrapM, .sfencevmaM,
       .InstrValidM, .CommittedM, .CommittedF,
       .FRegWriteM, .LoadStallD,
-      .DirPredictionWrongM, .BTBPredPCWrongM,
+      .DirPredictionWrongM, .BTBPredPCWrongM, .BPPredWrongM,
       .RASPredPCWrongM, .PredictionInstrClassWrongM,
-      .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
+      .InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
       .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
       .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, 
       .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 73b6c1845..0696367da 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -408,7 +408,7 @@ logic [3:0] dummy;
     end // always @ (negedge clk)
 
 
-  if(`PrintHPMCounters) begin
+  if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin
     integer HPMCindex;
     string  HPMCnames[] = '{"Mcycle",
                             "------",
@@ -424,7 +424,8 @@ logic [3:0] dummy;
                             "D Cache Access",
                             "D Cache Miss",
                             "I Cache Access",
-                            "I Cache Miss"};
+                            "I Cache Miss",
+							"Br Pred Wrong"};
     always @(negedge clk) begin
       if(DCacheFlushStart & ~DCacheFlushDone) begin
         for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin
@@ -483,11 +484,13 @@ logic [3:0] dummy;
       if (`BPRED_LOGGER) begin
         string direction;
         int    file;
+		logic  PCSrcM;
+		flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
         initial
           file = $fopen("branch.log", "w");
         always @(posedge clk) begin
            if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
-             direction = dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcM ? "t" : "n";
+             direction = PCSrcM ? "t" : "n";
              $fwrite(file, "%h %s\n", dut.core.PCM, direction);
            end
         end