From 76dccbad9194f7b1ec669e3f3ce063c151e13c1e Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 8 Feb 2022 12:40:02 +0000 Subject: [PATCH] Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail --- pipelined/testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 47337630b..e1a362741 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -256,7 +256,7 @@ logic [3:0] dummy; if (signature[i] !== sig & //if (signature[i] !== dut.core.lsu.dtim.ram.RAM[testadr+i] & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin // ***i+1? - if ((signature[i] !== '0 & signature[i+4] != 'x)) begin + if ((signature[i] !== '0 | signature[i+4] !== 'x)) begin // if (signature[i+4] !== 'bx | (signature[i] !== 32'hFFFFFFFF & signature[i] !== 32'h00000000)) begin // report errors unless they are garbage at the end of the sim // kind of hacky test for garbage right now