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This commit is contained in:
slmnemo 2022-05-17 01:03:09 +00:00
parent 8851ddd905
commit 7656e3031c
3 changed files with 19 additions and 7 deletions
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4
pipelined/config/rv64gc/wally-config.vh
View File

@ -131,8 +131,8 @@
`define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10
`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
`define TWO_BIT_PRELOAD "../config/shared/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/shared/BTBPredictor.txt"
`define BPRED_ENABLED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0

20
pipelined/testbench/testbench.sv
View File

@ -327,11 +327,23 @@ logic [3:0] dummy;
.done(DCacheFlushDone));
// initialize the branch predictor
if (`BPRED_ENABLED == 1)
if (`BPRED_ENABLED == 1)
initial begin
$readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
$readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);
end
integer adrindex;
// Initializing all zeroes into the branch predictor memory.
for(adrindex = 0; adrindex < 1024; adrindex++) begin
force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
end
#1;
for(adrindex = 0; adrindex < 1024; adrindex++) begin
release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
end
// $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
// $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);
end
endmodule
module riscvassertions;

2
pipelined/testbench/tests.vh
View File

@ -962,7 +962,7 @@ string imperas32f[] = '{
"rv64i_m/I/andi-01", "6010",
"rv64i_m/I/auipc-01", "2010",
"rv64i_m/I/beq-01", "47010",
"rv64i_m/I/bge-01", "46010",
"rv64i_m/I/bge-01", "47010",
"rv64i_m/I/bgeu-01", "56010",
"rv64i_m/I/blt-01", "4d010",
"rv64i_m/I/bltu-01", "57010",