From 7637f3e33b99e5d8e2404f7f9f5b90d71433de81 Mon Sep 17 00:00:00 2001
From: naichewa <nwhyteaguayo@g.hmc.edu>
Date: Thu, 7 Nov 2024 10:19:55 -0800
Subject: [PATCH] Fix erroneous implicit sckcs and cssck phase delays

---
 src/uncore/spi_controller.sv | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/uncore/spi_controller.sv b/src/uncore/spi_controller.sv
index a0aab008a..7a5126f2c 100644
--- a/src/uncore/spi_controller.sv
+++ b/src/uncore/spi_controller.sv
@@ -93,6 +93,7 @@ module spi_controller (
   logic [7:0] sckcs;
   logic [7:0] intercs;
   logic [7:0] interxfr;
+  logic       Phase;
   
   logic       HasCSSCK;
   logic       HasSCKCS;
@@ -142,6 +143,7 @@ module spi_controller (
 
   assign ContinueTransmit = ~TransmitFIFOEmpty & EndOfFrame;
   assign EndTransmission = TransmitFIFOEmpty & EndOfFrame;
+  assign Phase = SckMode[0];
   
   always_ff @(posedge PCLK) begin
     if (~PRESETn) begin
@@ -166,10 +168,12 @@ module spi_controller (
       end
       
       // SPICLK Logic
+      
       if (TransmitStart) begin
         SPICLK <= SckMode[1];
-      end else if (SCLKenable & Transmitting) begin
-        SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
+      end else if (SCLKenable) begin
+        if (Phase & (NextState == TRANSMIT)) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
+        else if (Transmitting) SPICLK <= (~EndTransmission & ~DelayIsNext) ? ~SPICLK : SckMode[1];
       end
       
       // Reset divider