diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh
index 265a26b5f..71f41df2b 100644
--- a/config/rv32e/config.vh
+++ b/config/rv32e/config.vh
@@ -117,7 +117,7 @@ localparam logic VECTORED_INTERRUPTS_SUPPORTED = 0;
 localparam logic BIGENDIAN_SUPPORTED = 0;
 
 // Fetch buffer configuration
-localparam logic FETCHBUFFER_SUPPORTED = 0;
+localparam FETCHBUFFER_ENTRIES =32'd0;
 
 // TLB configuration.  Entries should be a power of 2
 localparam ITLB_ENTRIES = 32'd0;
diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh
index 4efafebe7..1c6c3b8c0 100644
--- a/config/rv32gc/config.vh
+++ b/config/rv32gc/config.vh
@@ -117,7 +117,7 @@ localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
 localparam logic BIGENDIAN_SUPPORTED = 1;
 
 // Fetch buffer configuration
-localparam logic FETCHBUFFER_SUPPORTED = 1;
+localparam FETCHBUFFER_ENTRIES = 32'd3;
 
 // TLB configuration.  Entries should be a power of 2
 localparam ITLB_ENTRIES = 32'd32;
diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh
index dbfec1709..c87a903c4 100644
--- a/config/rv32i/config.vh
+++ b/config/rv32i/config.vh
@@ -117,7 +117,7 @@ localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
 localparam logic BIGENDIAN_SUPPORTED = 0;
 
 // Fetch buffer configuration
-localparam logic FETCHBUFFER_SUPPORTED = 1;
+localparam FETCHBUFFER_ENTRIES = 32'd3;
 
 // TLB configuration.  Entries should be a power of 2
 localparam ITLB_ENTRIES = 32'd32;
diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh
index 11aa2f436..abd6a595a 100644
--- a/config/rv32imc/config.vh
+++ b/config/rv32imc/config.vh
@@ -117,7 +117,7 @@ localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
 localparam logic BIGENDIAN_SUPPORTED = 0;
 
 // Fetch buffer configuration
-localparam logic FETCHBUFFER_SUPPORTED = 1;
+localparam FETCHBUFFER_ENTRIES = 32'd3;
 
 // TLB configuration.  Entries should be a power of 2
 localparam ITLB_ENTRIES = 32'd0;
diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh
index 4d1b13c56..4208512d4 100644
--- a/config/rv64gc/config.vh
+++ b/config/rv64gc/config.vh
@@ -117,7 +117,7 @@ localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
 localparam logic BIGENDIAN_SUPPORTED = 1;
 
 // Fetch buffer configuration
-localparam logic FETCHBUFFER_SUPPORTED = 1;
+localparam FETCHBUFFER_ENTRIES = 32'd3;
 
 // TLB configuration.  Entries should be a power of 2
 localparam ITLB_ENTRIES = 32'd32;
diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh
index 51c6e52ae..bf2c94bca 100644
--- a/config/rv64i/config.vh
+++ b/config/rv64i/config.vh
@@ -117,7 +117,7 @@ localparam logic VECTORED_INTERRUPTS_SUPPORTED = 1;
 localparam logic BIGENDIAN_SUPPORTED = 0;
 
 // Fetch buffer configuration
-localparam logic FETCHBUFFER_SUPPORTED = 1;
+localparam FETCHBUFFER_ENTRIES = 32'd3;
 
 // TLB configuration.  Entries should be a power of 2
 localparam ITLB_ENTRIES = 32'd0;
diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh
index 9ab22c5ca..5d30710c1 100644
--- a/config/shared/parameter-defs.vh
+++ b/config/shared/parameter-defs.vh
@@ -45,7 +45,7 @@ localparam cvw_t P = '{
   ICACHE_WAYSIZEINBYTES :        ICACHE_WAYSIZEINBYTES,
   ICACHE_LINELENINBITS :        ICACHE_LINELENINBITS,
   CACHE_SRAMLEN : CACHE_SRAMLEN,
-  FETCHBUFFER_SUPPORTED : FETCHBUFFER_SUPPORTED,
+  FETCHBUFFER_ENTRIES : FETCHBUFFER_ENTRIES,
   IDIV_BITSPERCYCLE :        IDIV_BITSPERCYCLE,
   IDIV_ON_FPU :        IDIV_ON_FPU,
   PMP_ENTRIES :        PMP_ENTRIES,
diff --git a/src/cvw.sv b/src/cvw.sv
index 9268fe294..c6030ff31 100644
--- a/src/cvw.sv
+++ b/src/cvw.sv
@@ -75,7 +75,7 @@ typedef struct packed {
   logic         ICACHE_SUPPORTED;
 
   // Fetch Buffer Configuration
-  logic         FETCHBUFFER_SUPPORTED;
+  int         FETCHBUFFER_ENTRIES;
 
 // TLB configuration.  Entries should be a power of 2
   int           ITLB_ENTRIES;
diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index de2a50d58..9759bb79a 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -303,7 +303,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   assign IFUStallF = IFUCacheBusStallF | SelSpillNextF;
   assign GatedStallD = StallD & ~SelSpillNextF;
 
-  if (P.FETCHBUFFER_SUPPORTED) begin : fetchbuffer
+  if (P.FETCHBUFFER_ENTRIES != 0) begin : fetchbuffer
     fetchbuffer #(P) fetchbuff(.clk, .reset, .StallF, .StallD, .FlushD, .WriteData(PostSpillInstrRawF), .ReadData(InstrRawD), .FetchBufferStallF);
   end else begin
     flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv
index c0f13d8ff..951d5d86b 100644
--- a/testbench/common/riscvassertions.sv
+++ b/testbench/common/riscvassertions.sv
@@ -67,6 +67,7 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
     assert ((P.ZCD_SUPPORTED == 0) | (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");
     assert ((P.LLEN == P.XLEN) | (P.DCACHE_SUPPORTED & P.DTIM_SUPPORTED == 0)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache");
     assert ((P.ZICCLSM_SUPPORTED == 0) | (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICCLSM requires DCACHE_SUPPORTED");
+    assert ((P.FETCHBUFFER_ENTRIES == 0) | (P.FETCHBUFFER_ENTRIES >= 3)) else $fatal(1, "FETCHBUFFER_ENTRIES must be 0 (disabled) or at least 3");
   end
 
 endmodule