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fixed lint warnings for fpu and lzd

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This commit is contained in:
Katherine Parry 2021-06-05 12:06:33 -04:00
parent 49200bd922
commit 75a6097467
9 changed files with 50 additions and 44 deletions
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5
wally-pipelined/src/fpu/fctrl.sv
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@ -57,12 +57,13 @@ module fctrl (
always_comb begin always_comb begin
//checks all but FMA/store/load //checks all but FMA/store/load
IllegalFPUInstr2D = 0; IllegalFPUInstr2D = 0;
FDivStartD = 1'b0;
if(OpD == 7'b1010011) begin if(OpD == 7'b1010011) begin
casez(Funct7D) casez(Funct7D)
//compare //compare
7'b10100?? : FResultSelD = 3'b001; 7'b10100?? : FResultSelD = 3'b001;
//div/sqrt //div/sqrt
7'b0?011?? : FResultSelD = 3'b000; 7'b0?011?? : begin FResultSelD = 3'b000; FDivStartD = 1'b1; end
//add/sub //add/sub
7'b0000??? : FResultSelD = 3'b100; 7'b0000??? : FResultSelD = 3'b100;
//mult //mult
@ -129,8 +130,6 @@ module fctrl (
//this value is used enough to be shorthand //this value is used enough to be shorthand
//if op is div/sqrt - start div/sqrt
assign FDivStartD = ~|FResultSelD; // is FResultSelD == 000
//operation control for each fp operation //operation control for each fp operation
//has to be expanded over standard to account for //has to be expanded over standard to account for

26
wally-pipelined/src/fpu/fpdiv.sv
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@ -23,8 +23,8 @@
// //
// `timescale 1ps/1ps // `timescale 1ps/1ps
module fpdiv (FDivSqrtDoneM, FDivResultM, FDivFlagsM, DivDenormM, FInput1E, FInput2E, FrmE, DivOpType, FmtE, DivOvEn, DivUnEn, module fpdiv (FDivSqrtDoneE, FDivResultE, FDivFlagsE, DivDenormE, FInput1E, FInput2E, FrmE, DivOpType, FmtE, DivOvEn, DivUnEn,
FDivStartE, reset, clk, DivBusyM); FDivStartE, reset, clk, FDivBusyE);
input [63:0] FInput1E; // 1st input operand (A) input [63:0] FInput1E; // 1st input operand (A)
input [63:0] FInput2E; // 2nd input operand (B) input [63:0] FInput2E; // 2nd input operand (B)
@ -38,11 +38,11 @@ module fpdiv (FDivSqrtDoneM, FDivResultM, FDivFlagsM, DivDenormM, FInput1E, FInp
input reset; input reset;
input clk; input clk;
output [63:0] FDivResultM; // Result of operation output [63:0] FDivResultE; // Result of operation
output [4:0] FDivFlagsM; // IEEE exception flags output [4:0] FDivFlagsE; // IEEE exception flags
output DivDenormM; // DivDenormM on input or output output DivDenormE; // DivDenormE on input or output
output FDivSqrtDoneM; output FDivSqrtDoneE;
output DivBusyM; output FDivBusyE;
supply1 vdd; supply1 vdd;
supply0 vss; supply0 vss;
@ -101,7 +101,7 @@ module fpdiv (FDivSqrtDoneM, FDivResultM, FDivFlagsM, DivDenormM, FInput1E, FInp
convert_inputs_div divconv1 (Float1, Float2, FInput1E, FInput2E, DivOpType, FmtE); convert_inputs_div divconv1 (Float1, Float2, FInput1E, FInput2E, DivOpType, FmtE);
// Test for exceptions and return the "Invalid Operation" and // Test for exceptions and return the "Invalid Operation" and
// "Denormalized" Input FDivFlagsM. The "sel_inv" is used in // "Denormalized" Input FDivFlagsE. The "sel_inv" is used in
// the third pipeline stage to select the result. Also, op1_Norm // the third pipeline stage to select the result. Also, op1_Norm
// and op2_Norm are one if FInput1E and FInput2E are not zero or denormalized. // and op2_Norm are one if FInput1E and FInput2E are not zero or denormalized.
// sub is one if the effective operation is subtaction. // sub is one if the effective operation is subtaction.
@ -138,9 +138,9 @@ module fpdiv (FDivSqrtDoneM, FDivResultM, FDivFlagsM, DivDenormM, FInput1E, FInp
load_regr, load_regs, FmtE, DivOpType, exp_odd); load_regr, load_regs, FmtE, DivOpType, exp_odd);
// FSM : control divider // FSM : control divider
fsm control (FDivSqrtDoneM, load_rega, load_regb, load_regc, load_regd, fsm control (FDivSqrtDoneE, load_rega, load_regb, load_regc, load_regd,
load_regr, load_regs, sel_muxa, sel_muxb, sel_muxr, load_regr, load_regs, sel_muxa, sel_muxb, sel_muxr,
clk, reset, FDivStartE, DivOpType, DivBusyM); clk, reset, FDivStartE, DivOpType, FDivBusyE);
// Round the mantissa to a 52-bit value, with the leading one // Round the mantissa to a 52-bit value, with the leading one
// removed. The rounding units also handles special cases and // removed. The rounding units also handles special cases and
@ -152,9 +152,9 @@ module fpdiv (FDivSqrtDoneM, FDivResultM, FDivFlagsM, DivDenormM, FInput1E, FInp
q1, qm1, qp1, q0, qm0, qp0, regr_out); q1, qm1, qp1, q0, qm0, qp0, regr_out);
// Store the final result and the exception flags in registers. // Store the final result and the exception flags in registers.
flopenr #(64) rega (clk, reset, FDivSqrtDoneM, Result, FDivResultM); flopenr #(64) rega (clk, reset, FDivSqrtDoneE, Result, FDivResultE);
flopenr #(1) regb (clk, reset, FDivSqrtDoneM, DenormIO, DivDenormM); flopenr #(1) regb (clk, reset, FDivSqrtDoneE, DenormIO, DivDenormE);
flopenr #(5) regc (clk, reset, FDivSqrtDoneM, FlagsIn, FDivFlagsM); flopenr #(5) regc (clk, reset, FDivSqrtDoneE, FlagsIn, FDivFlagsE);
endmodule // fpadd endmodule // fpadd

17
wally-pipelined/src/fpu/fpu.sv
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@ -42,7 +42,7 @@ module fpu (
output logic FStallD, output logic FStallD,
output logic FWriteIntE, FWriteIntM, FWriteIntW, output logic FWriteIntE, FWriteIntM, FWriteIntW,
output logic [`XLEN-1:0] FWriteDataM, output logic [`XLEN-1:0] FWriteDataM,
output logic FDivSqrtDoneM, output logic FDivBusyE,
output logic IllegalFPUInstrD, output logic IllegalFPUInstrD,
output logic [`XLEN-1:0] FPUResultW); output logic [`XLEN-1:0] FPUResultW);
@ -73,11 +73,11 @@ module fpu (
logic [`XLEN-1:0] FLoadStoreResultM, FLoadStoreResultW; // Result for load, store, and move to int-reg instructions logic [`XLEN-1:0] FLoadStoreResultM, FLoadStoreResultW; // Result for load, store, and move to int-reg instructions
// div/sqrt signals // div/sqrt signals
logic DivDenormM, DivDenormW; logic DivDenormE, DivDenormM, DivDenormW;
logic DivOvEn, DivUnEn; logic DivOvEn, DivUnEn;
logic DivBusyM; logic [63:0] FDivResultE, FDivResultM, FDivResultW;
logic [63:0] FDivResultM, FDivResultW; logic [4:0] FDivFlagsE, FDivFlagsM, FDivFlagsW;
logic [4:0] FDivFlagsM, FDivFlagsW; logic FDivSqrtDoneE, FDivSqrtDoneM;
// FMA signals // FMA signals
logic [105:0] ProdManE, ProdManM; logic [105:0] ProdManE, ProdManM;
@ -263,6 +263,13 @@ module fpu (
flopenrc #(1) EMRegFma20(clk, reset, PipeClearEM, PipeEnableEM, YNaNE, YNaNM); flopenrc #(1) EMRegFma20(clk, reset, PipeClearEM, PipeEnableEM, YNaNE, YNaNM);
flopenrc #(1) EMRegFma21(clk, reset, PipeClearEM, PipeEnableEM, ZNaNE, ZNaNM); flopenrc #(1) EMRegFma21(clk, reset, PipeClearEM, PipeEnableEM, ZNaNE, ZNaNM);
//*****************
// fpdiv E/M pipe registers
//*****************
flopenrc #(64) EMRegDiv1(clk, reset, PipeClearEM, PipeEnableEM, FDivResultE, FDivResultM);
flopenrc #(5) EMRegDiv2(clk, reset, PipeClearEM, PipeEnableEM, FDivFlagsE, FDivFlagsM);
flopenrc #(1) EMRegDiv3(clk, reset, PipeClearEM, PipeEnableEM, DivDenormE, DivDenormM);
//***************** //*****************
// fpadd E/M pipe registers // fpadd E/M pipe registers
//***************** //*****************

4
wally-pipelined/src/fpu/fpuhazard.sv
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@ -29,7 +29,7 @@ module fpuhazard(
input logic [4:0] Adr1, Adr2, Adr3, input logic [4:0] Adr1, Adr2, Adr3,
input logic FWriteEnE, FWriteEnM, FWriteEnW, input logic FWriteEnE, FWriteEnM, FWriteEnW,
input logic [4:0] RdE, RdM, RdW, input logic [4:0] RdE, RdM, RdW,
input logic DivBusyM, input logic FDivBusyE,
input logic RegWriteD, input logic RegWriteD,
input logic [2:0] FResultSelD, FResultSelE, input logic [2:0] FResultSelD, FResultSelE,
input logic IllegalFPUInstrD, input logic IllegalFPUInstrD,
@ -46,7 +46,7 @@ module fpuhazard(
FForwardInput1D = 2'b00; FForwardInput1D = 2'b00;
FForwardInput2D = 2'b00; FForwardInput2D = 2'b00;
FForwardInput3D = 1'b0; FForwardInput3D = 1'b0;
FStallD = DivBusyM; FStallD = FDivBusyE;
if (~IllegalFPUInstrD) begin if (~IllegalFPUInstrD) begin
// if taking a value from int register // if taking a value from int register
if ((Adr1 == RdE) & (FWriteEnE | ((FResultSelE == 3'b110) & RegWriteD))) if ((Adr1 == RdE) & (FWriteEnE | ((FResultSelE == 3'b110) & RegWriteD)))

4
wally-pipelined/src/fpu/fsm.sv
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@ -48,7 +48,7 @@ module fsm (done, load_rega, load_regb, load_regc,
S25=5'd25, S26=5'd26, S27=5'd27, S25=5'd25, S26=5'd26, S27=5'd27,
S28=5'd28, S29=5'd29, S30=5'd30; S28=5'd28, S29=5'd29, S30=5'd30;
always @(posedge clk) always @(negedge clk)
begin begin
if(reset==1'b1) if(reset==1'b1)
CURRENT_STATE=S0; CURRENT_STATE=S0;
@ -245,7 +245,7 @@ module fsm (done, load_rega, load_regb, load_regc,
S10: // done S10: // done
begin begin
done = 1'b1; done = 1'b1;
divBusy = 1'b1; divBusy = 1'b0;
load_rega = 1'b0; load_rega = 1'b0;
load_regb = 1'b0; load_regb = 1'b0;
load_regc = 1'b0; load_regc = 1'b0;

26
wally-pipelined/src/generic/lzd.sv
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@ -44,7 +44,7 @@ module lzd2 (P, V, B);
assign V = B[0] | B[1]; assign V = B[0] | B[1];
assign P = B[0] & ~B[1]; assign P = B[0] & ~B[1];
endmodule // lz2 endmodule // lzd2
module lzd_hier #(parameter WIDTH=8) module lzd_hier #(parameter WIDTH=8)
(input logic [WIDTH-1:0] B, (input logic [WIDTH-1:0] B,
@ -78,8 +78,8 @@ module lzd4 (ZP, ZV, B);
output logic [1:0] ZP; output logic [1:0] ZP;
output logic ZV; output logic ZV;
lz2 l1(ZPa, ZVa, B[1:0]); lzd2 l1(ZPa, ZVa, B[1:0]);
lz2 l2(ZPb, ZVb, B[3:2]); lzd2 l2(ZPb, ZVb, B[3:2]);
assign ZP[0:0] = ZVb ? ZPb : ZPa; assign ZP[0:0] = ZVb ? ZPb : ZPa;
assign ZP[1] = ~ZVb; assign ZP[1] = ~ZVb;
@ -99,8 +99,8 @@ module lzd8 (ZP, ZV, B);
output logic [2:0] ZP; output logic [2:0] ZP;
output logic ZV; output logic ZV;
lz4 l1(ZPa, ZVa, B[3:0]); lzd4 l1(ZPa, ZVa, B[3:0]);
lz4 l2(ZPb, ZVb, B[7:4]); lzd4 l2(ZPb, ZVb, B[7:4]);
assign ZP[1:0] = ZVb ? ZPb : ZPa; assign ZP[1:0] = ZVb ? ZPb : ZPa;
assign ZP[2] = ~ZVb; assign ZP[2] = ~ZVb;
@ -120,8 +120,8 @@ module lzd16 (ZP, ZV, B);
output logic [3:0] ZP; output logic [3:0] ZP;
output logic ZV; output logic ZV;
lz8 l1(ZPa, ZVa, B[7:0]); lzd8 l1(ZPa, ZVa, B[7:0]);
lz8 l2(ZPb, ZVb, B[15:8]); lzd8 l2(ZPb, ZVb, B[15:8]);
assign ZP[2:0] = ZVb ? ZPb : ZPa; assign ZP[2:0] = ZVb ? ZPb : ZPa;
assign ZP[3] = ~ZVb; assign ZP[3] = ~ZVb;
@ -141,8 +141,8 @@ module lzd32 (ZP, ZV, B);
output logic [4:0] ZP; output logic [4:0] ZP;
output logic ZV; output logic ZV;
lz16 l1(ZPa, ZVa, B[15:0]); lzd16 l1(ZPa, ZVa, B[15:0]);
lz16 l2(ZPb, ZVb, B[31:16]); lzd16 l2(ZPb, ZVb, B[31:16]);
assign ZP[3:0] = ZVb ? ZPb : ZPa; assign ZP[3:0] = ZVb ? ZPb : ZPa;
assign ZP[4] = ~ZVb; assign ZP[4] = ~ZVb;
@ -162,8 +162,8 @@ module lzd64 (ZP, ZV, B);
output logic [5:0] ZP; output logic [5:0] ZP;
output logic ZV; output logic ZV;
lz32 l1(ZPa, ZVa, B[31:0]); lzd32 l1(ZPa, ZVa, B[31:0]);
lz32 l2(ZPb, ZVb, B[63:32]); lzd32 l2(ZPb, ZVb, B[63:32]);
assign ZP[4:0] = ZVb ? ZPb : ZPa; assign ZP[4:0] = ZVb ? ZPb : ZPa;
assign ZP[5] = ~ZVb; assign ZP[5] = ~ZVb;
@ -183,8 +183,8 @@ module lzd128 (ZP, ZV, B);
output logic [6:0] ZP; output logic [6:0] ZP;
output logic ZV; output logic ZV;
lz64 l1(ZPa, ZVa, B[64:0]); lzd64 l1(ZPa, ZVa, B[64:0]);
lz64 l2(ZPb, ZVb, B[127:63]); lzd64 l2(ZPb, ZVb, B[127:63]);
assign ZP[5:0] = ZVb ? ZPb : ZPa; assign ZP[5:0] = ZVb ? ZPb : ZPa;
assign ZP[6] = ~ZVb; assign ZP[6] = ~ZVb;

4
wally-pipelined/src/hazard/hazard.sv
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@ -33,7 +33,7 @@ module hazard(
input logic LoadStallD, MulDivStallD, CSRRdStallD, input logic LoadStallD, MulDivStallD, CSRRdStallD,
input logic DataStall, ICacheStallF, input logic DataStall, ICacheStallF,
input logic FPUStallD, input logic FPUStallD,
input logic DivBusyE, input logic DivBusyE,FDivBusyE,
// Stall & flush outputs // Stall & flush outputs
output logic StallF, StallD, StallE, StallM, StallW, output logic StallF, StallD, StallE, StallM, StallW,
output logic FlushF, FlushD, FlushE, FlushM, FlushW output logic FlushF, FlushD, FlushE, FlushM, FlushW
@ -57,7 +57,7 @@ module hazard(
assign StallFCause = CSRWritePendingDEM && ~(TrapM || RetM || BPPredWrongE); assign StallFCause = CSRWritePendingDEM && ~(TrapM || RetM || BPPredWrongE);
assign StallDCause = (LoadStallD || MulDivStallD || CSRRdStallD || FPUStallD) && ~(TrapM || RetM || BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous assign StallDCause = (LoadStallD || MulDivStallD || CSRRdStallD || FPUStallD) && ~(TrapM || RetM || BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous
assign StallECause = DivBusyE; assign StallECause = DivBusyE | FDivBusyE;
assign StallMCause = 0; assign StallMCause = 0;
assign StallWCause = DataStall || ICacheStallF; assign StallWCause = DataStall || ICacheStallF;

2
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -100,7 +100,7 @@ module wallypipelinedhart (
logic FStallD; logic FStallD;
logic FWriteIntE, FWriteIntW, FWriteIntM; logic FWriteIntE, FWriteIntW, FWriteIntM;
logic [31:0] FSROutW; logic [31:0] FSROutW;
logic FDivSqrtDoneM; logic FDivBusyE;
logic IllegalFPUInstrD, IllegalFPUInstrE; logic IllegalFPUInstrD, IllegalFPUInstrE;
logic [`XLEN-1:0] FPUResultW; logic [`XLEN-1:0] FPUResultW;

6
wally-pipelined/testbench/testbench-imperas.sv
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@ -122,6 +122,7 @@ string tests32f[] = '{
}; };
string tests64d[] = '{ string tests64d[] = '{
// "rv64d/I-FDIV-D-01", "2000",
"rv64d/I-FNMADD-D-01", "2000", "rv64d/I-FNMADD-D-01", "2000",
"rv64d/I-FNMSUB-D-01", "2000", "rv64d/I-FNMSUB-D-01", "2000",
"rv64d/I-FMSUB-D-01", "2000", "rv64d/I-FMSUB-D-01", "2000",
@ -142,13 +143,12 @@ string tests32f[] = '{
// "rv64d/I-FCVT-S-D-01", "2000", // "rv64d/I-FCVT-S-D-01", "2000",
// "rv64d/I-FCVT-W-D-01", "2000", // "rv64d/I-FCVT-W-D-01", "2000",
// "rv64d/I-FCVT-WU-D-01", "2000", // "rv64d/I-FCVT-WU-D-01", "2000",
// "rv64d/I-FDIV-D-01", "2000",
"rv64d/I-FSD-01", "2000", "rv64d/I-FSD-01", "2000",
"rv64d/I-FLD-01", "2420", "rv64d/I-FLD-01", "2420",
"rv64d/I-FMADD-D-01", "2000", "rv64d/I-FMADD-D-01", "2000",
"rv64d/I-FMUL-D-01", "2000", "rv64d/I-FMUL-D-01", "2000",
// "rv64d/I-FMV-D-X-01", "2000", "rv64d/I-FMV-D-X-01", "2000",
// "rv64d/I-FMV-X-D-01", "2000", "rv64d/I-FMV-X-D-01", "2000",
"rv64d/I-FSGNJ-D-01", "2000", "rv64d/I-FSGNJ-D-01", "2000",
"rv64d/I-FSGNJN-D-01", "2000", "rv64d/I-FSGNJN-D-01", "2000",
"rv64d/I-FSGNJX-D-01", "2000", "rv64d/I-FSGNJX-D-01", "2000",