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https://github.com/openhwgroup/cvw
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Added calibration input.
fixed HRESP duplication.
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10a3a76fe9
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@ -53,7 +53,8 @@ module wallypipelinedsocwrapper (
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input [31:0] GPIOPinsIn,
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input [31:0] GPIOPinsIn,
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output [31:0] GPIOPinsOut, GPIOPinsEn,
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output [31:0] GPIOPinsOut, GPIOPinsEn,
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input UARTSin,
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input UARTSin,
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output UARTSout
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output UARTSout,
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input ddr4_calib_complete
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);
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);
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// to instruction memory *** remove later
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// to instruction memory *** remove later
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@ -61,7 +62,7 @@ module wallypipelinedsocwrapper (
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// Uncore signals
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// Uncore signals
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wire [`AHBW-1:0] HRDATA; // from AHB mux in uncore
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wire [`AHBW-1:0] HRDATA; // from AHB mux in uncore
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wire HREADY, HRESP;
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wire HRESP;
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wire [5:0] HSELRegions;
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wire [5:0] HSELRegions;
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wire InstrAccessFaultF, DataAccessFaultM;
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wire InstrAccessFaultF, DataAccessFaultM;
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wire TimerIntM, SwIntM; // from CLINT
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wire TimerIntM, SwIntM; // from CLINT
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@ -76,7 +77,7 @@ module wallypipelinedsocwrapper (
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// wrapper for fpga
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// wrapper for fpga
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wallypipelinedsoc wallypipelinedsoc
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wallypipelinedsoc wallypipelinedsoc
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(.clk(clk),
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(.clk(clk),
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.reset(reset),
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.reset(reset | ~ddr4_calib_complete),
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.HRDATAEXT(HRDATAEXT),
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.HRDATAEXT(HRDATAEXT),
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.HREADYEXT(HREADYEXT),
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.HREADYEXT(HREADYEXT),
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.HRESPEXT(HRESPEXT),
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.HRESPEXT(HRESPEXT),
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