From 756352f1299cd6a61d587d37f2daae433227b249 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 2 Feb 2021 19:44:37 -0500 Subject: [PATCH] Minor tweaks --- wally-pipelined/src/ieu/datapath.sv | 2 +- wally-pipelined/src/privileged/csrm.sv | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv index 30603637c..bb02bad53 100644 --- a/wally-pipelined/src/ieu/datapath.sv +++ b/wally-pipelined/src/ieu/datapath.sv @@ -77,10 +77,10 @@ module datapath ( logic [`XLEN-1:0] ALUResultW; logic [`XLEN-1:0] ResultW; + // Decode stage assign Rs1D = InstrD[19:15]; assign Rs2D = InstrD[24:20]; assign RdD = InstrD[11:7]; - regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, RD1D, RD2D); extend ext(.InstrD(InstrD[31:7]), .*); diff --git a/wally-pipelined/src/privileged/csrm.sv b/wally-pipelined/src/privileged/csrm.sv index aade54b34..6e56c079b 100644 --- a/wally-pipelined/src/privileged/csrm.sv +++ b/wally-pipelined/src/privileged/csrm.sv @@ -101,9 +101,9 @@ module csrm #(parameter assign WriteMEPCM = MTrapM | (CSRMWriteM && (CSRAdrM == MEPC)); assign WriteMCAUSEM = MTrapM | (CSRMWriteM && (CSRAdrM == MCAUSE)); assign WriteMTVALM = MTrapM | (CSRMWriteM && (CSRAdrM == MTVAL)); - assign WritePMPCFG0M = MTrapM | (CSRMWriteM && (CSRAdrM == PMPCFG0)); - assign WritePMPCFG2M = MTrapM | (CSRMWriteM && (CSRAdrM == PMPCFG2)); - assign WritePMPADDR0M = MTrapM | (CSRMWriteM && (CSRAdrM == PMPADDR0)); + assign WritePMPCFG0M = (CSRMWriteM && (CSRAdrM == PMPCFG0)); + assign WritePMPCFG2M = (CSRMWriteM && (CSRAdrM == PMPCFG2)); + assign WritePMPADDR0M = (CSRMWriteM && (CSRAdrM == PMPADDR0)); assign WriteMCOUNTERENM = CSRMWriteM && (CSRAdrM == MCOUNTEREN); assign WriteMCOUNTINHIBITM = CSRMWriteM && (CSRAdrM == MCOUNTINHIBIT);