Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

wally-pipelined/config/buildroot/wally-config.vh

@@ -59,7 +59,7 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
-`define BOOTTIMBASE   32'h00000000 //only needs to go from 0x1000 to 0x2FFF, extending to a power of 2  // ***dh 3 June 2021 change this to ensure segfault on null pointer access.
+`define BOOTTIMBASE   32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
 `define BOOTTIMRANGE  32'h00003FFF
 `define CLINTBASE     32'h02000000
 `define CLINTRANGE    32'h0000FFFF

wally-pipelined/config/busybear/wally-config.vh

@@ -59,7 +59,7 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
-`define BOOTTIMBASE   32'h00000000 //only needs to go from 0x1000 to 0x2FFF, extending to a power of 2
+`define BOOTTIMBASE   32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
 `define BOOTTIMRANGE  32'h00003FFF
 `define CLINTBASE     32'h02000000
 `define CLINTRANGE    32'h0000FFFF

wally-pipelined/config/coremark/wally-config.vh

@@ -62,7 +62,7 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
-`define BOOTTIMBASE   32'h00000000
+`define BOOTTIMBASE   32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
 `define BOOTTIMRANGE  32'h00003FFF
 `define TIMBASE    32'h00000000
 `define TIMRANGE   32'hFFFFFFFF

wally-pipelined/config/coremark_bare/wally-config.vh

@@ -62,7 +62,7 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
-`define BOOTTIMBASE   32'h00000000
+`define BOOTTIMBASE   32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
 `define BOOTTIMRANGE  32'h00003FFF
 `define TIMBASE    32'h80000000
 `define TIMRANGE   32'h000FFFFF

wally-pipelined/config/rv32ic/wally-config.vh

@@ -51,6 +51,9 @@
 `define ITLB_ENTRY_BITS 5
 `define DTLB_ENTRY_BITS 5
 
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 16
+
 // Address space
 `define RESET_VECTOR 32'h80000000
 
@@ -58,7 +61,7 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
-`define BOOTTIMBASE   32'h00000000
+`define BOOTTIMBASE   32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
 `define BOOTTIMRANGE  32'h00003FFF
 `define TIMBASE       32'h80000000
 `define TIMRANGE      32'h07FFFFFF

wally-pipelined/config/rv64BP/wally-config.vh

@@ -63,7 +63,7 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
-`define BOOTTIMBASE   32'h00800000
+`define BOOTTIMBASE   32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
 `define BOOTTIMRANGE  32'h00003FFF
 `define TIMBASE       32'h00000000
 `define TIMRANGE      32'h07FFFFFF

wally-pipelined/config/rv64ic/wally-config.vh

@@ -52,6 +52,9 @@
 `define ITLB_ENTRY_BITS 5
 `define DTLB_ENTRY_BITS 5
 
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 16
+
 // Address space
 `define RESET_VECTOR 64'h0000000080000000
 
@@ -62,7 +65,7 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
-`define BOOTTIMBASE   32'h00000000
+`define BOOTTIMBASE   32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
 `define BOOTTIMRANGE  32'h00003FFF
 `define TIMBASE       32'h80000000
 `define TIMRANGE      32'h07FFFFFF

wally-pipelined/config/rv64icfd/wally-config.vh

@@ -62,7 +62,7 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
-`define BOOTTIMBASE   32'h00000000
+`define BOOTTIMBASE   32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
 `define BOOTTIMRANGE  32'h00003FFF
 `define TIMBASE    32'h80000000
 // `define TIMRANGE   32'h0007FFFF

wally-pipelined/config/rv64imc/wally-config.vh

@@ -61,7 +61,7 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
-`define BOOTTIMBASE   32'h00000000
+`define BOOTTIMBASE   32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
 `define BOOTTIMRANGE  32'h00003FFF
 `define TIMBASE    32'h80000000
 `define TIMRANGE   32'h0007FFFF

wally-pipelined/src/dmem/dmem.sv

@@ -71,7 +71,7 @@ module dmem (
   input  logic             HWRITE,
   input  logic             AtomicAccessM, WriteAccessM, ReadAccessM, // execute access is hardwired to zero in this mmu because we're only working with data in the M stage.
   input  logic [63:0]      PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem
-  input  logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], // *** this one especially has a large note attached to it in pmpchecker.
+  input  var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], // *** this one especially has a large note attached to it in pmpchecker.
 
   output  logic            PMALoadAccessFaultM, PMAStoreAccessFaultM,
   output  logic            PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa.
@@ -96,7 +96,7 @@ module dmem (
   // *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete.
   
   mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM),
-                .PageTableEntryWrite(PageTableEntryM), .PageTypeWrite(PageTypeM),
+                .PTEWriteVal(PageTableEntryM), .PageTypeWriteVal(PageTypeM),
                 .TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM),
                 .PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM),
                 .TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM),

wally-pipelined/src/ifu/ifu.sv

@@ -79,8 +79,8 @@ module ifu (
   input  logic [2:0]       HSIZE, HBURST,
   input  logic             HWRITE,
   input  logic             ExecuteAccessF, //read, write, and atomic access are all set to zero because this mmu is onlt working with instructinos in the F stage.
-  input  logic [63:0]      PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem
-  input  logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], // *** this one especially has a large note attached to it in pmpchecker.
+  input  logic [63:0]      PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so they're gonna have to come over into ifu and dmem
+  input  var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], 
 
   output logic             PMPInstrAccessFaultF, PMAInstrAccessFaultF,
   output logic             ISquashBusAccessF,
@@ -105,7 +105,7 @@ module ifu (
   // if you're allowed to parameterize outputs/ inputs existence, these are an easy delete.
 
   mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF),
-                .PageTableEntryWrite(PageTableEntryF), .PageTypeWrite(PageTypeF),
+                .PTEWriteVal(PageTableEntryF), .PageTypeWriteVal(PageTypeF),
                 .TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF),
                 .PhysicalAddress(PCPF), .TLBMiss(ITLBMissF),
                 .TLBHit(ITLBHitF), .TLBPageFault(ITLBInstrPageFaultF),

wally-pipelined/src/mmu/camline.sv

@@ -33,14 +33,14 @@ module camline #(parameter KEY_BITS = 20,
   input logic                 clk, reset,
 
   // input to check which SvMode is running
-  input logic [`SVMODE_BITS-1:0] SvMode,
+//  input logic [`SVMODE_BITS-1:0] SvMode, // *** may no longer be needed.
   
   // The requested page number to compare against the key
   input logic [KEY_BITS-1:0]  VirtualPageNumber,
 
   // Signals to write a new entry to this line
   input logic                 CAMLineWrite,
-  input logic [1:0]           PageTypeWrite,
+  input logic [1:0]           PageTypeWriteVal,
 
   // Flush this line (set valid to 0)
   input logic                 TLBFlush,
@@ -96,13 +96,8 @@ module camline #(parameter KEY_BITS = 20,
     end
   endgenerate
 
-  // When determining a match for a superpage, we might use only a portion of
-  // the input VirtualPageNumber. Unused parts of the VirtualPageNumber are
-  // zeroed in VirtualPageNumberQuery to better match with Key.
-  logic [KEY_BITS-1:0] VirtualPageNumberQuery;
-
   // On a write, update the type of the page referred to by this line.
-  flopenr #(2) pagetypeflop(clk, reset, CAMLineWrite, PageTypeWrite, PageType);
+  flopenr #(2) pagetypeflop(clk, reset, CAMLineWrite, PageTypeWriteVal, PageType);
   //mux2 #(2) pagetypemux(StoredPageType, PageTypeWrite, CAMLineWrite, PageType);
 
   // On a write, set the valid bit high and update the stored key.

wally-pipelined/src/mmu/mmu.sv

@@ -49,8 +49,8 @@ module mmu #(parameter ENTRY_BITS = 3,
   input logic  [`XLEN-1:0] VirtualAddress,
 
   // Controls for writing a new entry to the TLB
-  input logic  [`XLEN-1:0] PageTableEntryWrite,
-  input logic  [1:0]       PageTypeWrite,
+  input logic  [`XLEN-1:0] PTEWriteVal,
+  input logic  [1:0]       PageTypeWriteVal,
   input logic              TLBWrite,
 
   // Invalidate all TLB entries
@@ -70,7 +70,7 @@ module mmu #(parameter ENTRY_BITS = 3,
   input  logic             HWRITE,
   input  logic             AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
   input  logic [63:0]      PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem
-  input  logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], // *** this one especially has a large note attached to it in pmpchecker.
+  input  var logic  [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], 
 
   output logic             SquashBusAccess, // *** send to privileged unit
   output logic             PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM,

wally-pipelined/src/mmu/pmachecker.sv

@@ -28,13 +28,13 @@
 `include "wally-config.vh"
 
 module pmachecker (
-  input  logic        clk, reset,
+//  input  logic        clk, reset, // *** unused in this module and all sub modules.
 
   input  logic [31:0] HADDR,
   input  logic [2:0]  HSIZE,
-  input  logic [2:0]  HBURST,
+//  input  logic [2:0]  HBURST, //  *** in AHBlite, HBURST is hardwired to zero for single bursts only allowed. consider removing from this module if unused.
 
-  input  logic        AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
+  input  logic        AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // *** atomicaccessM is unused but might want to stay in for future use.
 
   output logic        Cacheable, Idempotent, AtomicAllowed,
   output logic        PMASquashBusAccess,
@@ -92,7 +92,7 @@ module pmachecker (
 endmodule
 
 module attributes (
-  input  logic        clk, reset,
+//  input  logic        clk, reset, // *** unused in this module and all sub modules.
 
   input  logic [31:0] Address,
 

wally-pipelined/src/mmu/pmpchecker.sv

@@ -29,7 +29,7 @@
 `include "wally-config.vh"
 
 module pmpchecker (
-  input  logic             clk, reset,
+//  input  logic             clk, reset, //*** it seems like clk, reset is also not needed here?
 
   input  logic [31:0]      HADDR,
 
@@ -48,7 +48,7 @@ module pmpchecker (
   // boundary. It would be better to store the PMP address registers in a module
   // somewhere in the CSR hierarchy and do PMP checking _within_ that module, so
   // we don't have to pass around 16 whole registers.
-  input  var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15],
+  input  var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1],
 
   input  logic             ExecuteAccessF, WriteAccessM, ReadAccessM,
 
@@ -89,9 +89,9 @@ module pmpchecker (
                       .Match(Regions[0]));
   assign ActiveRegion[0] = |PMPCFG[0][4:3];
 
-  generate
+  generate // *** only for PMP_ENTRIES > 0
     genvar i;
-    for (i = 1; i < 16; i++) begin
+    for (i = 1; i < `PMP_ENTRIES; i++) begin
       pmpadrdec pmpadrdec(.HADDR(HADDR), .AdrMode(PMPCFG[i][4:3]),
                           .CurrentPMPAdr(PMPADDR_ARRAY_REGW[i]),
                           .AdrAtLeastPreviousPMP(AboveRegion[i-1]),

wally-pipelined/src/mmu/tlb.sv

@@ -70,8 +70,8 @@ module tlb #(parameter ENTRY_BITS = 3,
   input logic  [`XLEN-1:0] VirtualAddress,
 
   // Controls for writing a new entry to the TLB
-  input logic  [`XLEN-1:0] PageTableEntryWrite,
-  input logic  [1:0]       PageTypeWrite,
+  input logic  [`XLEN-1:0] PTEWriteVal,
+  input logic  [1:0]       PageTypeWriteVal,
   input logic              TLBWrite,
 
   // Invalidate all TLB entries
@@ -94,7 +94,7 @@ module tlb #(parameter ENTRY_BITS = 3,
 
   // Index (currently random) to write the next TLB entry
   logic [ENTRY_BITS-1:0] WriteIndex;
-  logic [2**ENTRY_BITS-1:0] WriteLines; // used as the one-hot encoding of WriteIndex
+  logic [(2**ENTRY_BITS)-1:0] WriteLines; // used as the one-hot encoding of WriteIndex
 
   // Sections of the virtual and physical addresses
   logic [`VPN_BITS-1:0] VirtualPageNumber;
@@ -119,7 +119,7 @@ module tlb #(parameter ENTRY_BITS = 3,
   assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
 
   // Decode the integer encoded WriteIndex into the one-hot encoded WriteLines
-  decoder writedecoder(WriteIndex, WriteLines);
+  decoder #(ENTRY_BITS) writedecoder(WriteIndex, WriteLines);
 
   // The bus width is always the largest it could be for that XLEN. For example, vpn will be 36 bits wide in rv64
   // this, even though it could be 27 bits (SV39) or 36 bits (SV48) wide. When the value of VPN is narrower,

wally-pipelined/src/mmu/tlbcam.sv

@@ -33,8 +33,8 @@ module tlbcam #(parameter ENTRY_BITS = 3,
                  parameter SEGMENT_BITS = 10) (
   input logic                     clk, reset,
   input logic [KEY_BITS-1:0]      VirtualPageNumber,
-  input logic [1:0]               PageTypeWrite,
-  input logic [`SVMODE_BITS-1:0]  SvMode,
+  input logic [1:0]               PageTypeWriteVal,
+//  input logic [`SVMODE_BITS-1:0]  SvMode, // *** may not need to be used.
   input logic                     TLBWrite,
   input logic                     TLBFlush,
   input logic [2**ENTRY_BITS-1:0] WriteLines,
@@ -69,7 +69,7 @@ module tlbcam #(parameter ENTRY_BITS = 3,
   // In case there are multiple matches in the CAM, select only one
   // *** it might be guaranteed that the CAM will never have multiple matches.
   // If so, this is just an encoder
-  priorityencoder #(ENTRY_BITS) matchpriority(Matches, VPNIndex);
+  priorityencoder #(ENTRY_BITS) matchencoder(Matches, VPNIndex);
 
   assign CAMHit = |Matches & ~TLBFlush;
   assign HitPageType = PageTypeList[VPNIndex];

wally-pipelined/src/mmu/tlbram.sv

@@ -30,8 +30,8 @@
 module tlbram #(parameter ENTRY_BITS = 3) (
   input logic                       clk, reset,
   input logic [ENTRY_BITS-1:0]      VPNIndex,  // Index to read from
-  input logic [ENTRY_BITS-1:0]      WriteIndex,
-  input logic [`XLEN-1:0]           PageTableEntryWrite,
+//  input logic [ENTRY_BITS-1:0]      WriteIndex, // *** unused?
+  input logic [`XLEN-1:0]           PTEWriteVal,
   input logic                       TLBWrite,
   input logic [2**ENTRY_BITS-1:0]   WriteLines,
 
@@ -49,7 +49,7 @@ module tlbram #(parameter ENTRY_BITS = 3) (
     genvar i;
     for (i = 0; i < NENTRIES; i++) begin:  tlb_ram_flops
       flopenr #(`XLEN) pteflop(clk, reset, WriteLines[i] & TLBWrite,
-        PageTableEntryWrite, ram[i]);
+        PTEWriteVal, ram[i]);
     end
   endgenerate
 

wally-pipelined/src/privileged/csr.sv

@@ -60,7 +60,7 @@ module csr #(parameter
   output logic             STATUS_MXR, STATUS_SUM,
   output logic             STATUS_MPRV,
   output logic [63:0]      PMPCFG01_REGW, PMPCFG23_REGW,
-  output logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15],
+  output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1],
   input  logic [4:0]       SetFflagsM,
   output logic [2:0]       FRM_REGW, 
 //  output logic [11:0]     MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,

wally-pipelined/src/privileged/csrm.sv

@@ -93,7 +93,7 @@ module csrm #(parameter
     output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW,
     // 64-bit registers in RV64, or two 32-bit registers in RV32
     output logic [63:0]      PMPCFG01_REGW, PMPCFG23_REGW,
-    output logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15],
+    output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1],
     input  logic [11:0]      MIP_REGW, MIE_REGW,
     output logic             WriteMSTATUSM,
     output logic             IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM
@@ -171,10 +171,10 @@ module csrm #(parameter
   endgenerate
   flopenl #(32)   MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], ALL_ONES, MCOUNTINHIBIT_REGW);
 
-  // There are 16 PMPADDR registers, each of which has its own flop
+  // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
   generate
     genvar i;
-    for (i = 0; i < 16; i++) begin: pmp_flop
+    for (i = 0; i < `PMP_ENTRIES-1; i++) begin: pmp_flop
       flopenr #(`XLEN) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM, PMPADDR_ARRAY_REGW[i]);
     end
   endgenerate
@@ -221,7 +221,7 @@ module csrm #(parameter
       PMPCFG1:   CSRMReadValM = {{(`XLEN-32){1'b0}}, PMPCFG01_REGW[63:31]};
       PMPCFG2:   CSRMReadValM = PMPCFG23_REGW[`XLEN-1:0];
       PMPCFG3:   CSRMReadValM = {{(`XLEN-32){1'b0}}, PMPCFG23_REGW[63:31]};
-      PMPADDR0:  CSRMReadValM = PMPADDR_ARRAY_REGW[0];
+      PMPADDR0:  CSRMReadValM = PMPADDR_ARRAY_REGW[0]; // *** make configurable
       PMPADDR1:  CSRMReadValM = PMPADDR_ARRAY_REGW[1];
       PMPADDR2:  CSRMReadValM = PMPADDR_ARRAY_REGW[2];
       PMPADDR3:  CSRMReadValM = PMPADDR_ARRAY_REGW[3];

wally-pipelined/src/privileged/privileged.sv

@@ -68,7 +68,7 @@ module privileged (
   output logic [`XLEN-1:0] SATP_REGW,
   output logic             STATUS_MXR, STATUS_SUM,
   output logic [63:0]      PMPCFG01_REGW, PMPCFG23_REGW,
-  output logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15], //*** to be sent up through wallypipelinedhart into the pma/pmp in ifu and dmem. *** is it a bad idea to have this huge bus running all over?
+  output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1], 
   output logic [2:0]       FRM_REGW
 );
 

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -120,7 +120,7 @@ module wallypipelinedhart (
   logic             PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM;
   logic             DSquashBusAccessM, ISquashBusAccessF;
   logic [5:0]            DHSELRegionsM, IHSELRegionsF;
-  logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15]; // *** again, this is a huge bus to be sending all around.
+  var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:`PMP_ENTRIES-1];
   logic [63:0]      PMPCFG01_REGW, PMPCFG23_REGW; // signals being sent from privileged unit to pmp/pma in dmem and ifu.
   assign            HSELRegions = ExecuteAccessF ? IHSELRegionsF : DHSELRegionsM; // *** this is a pure guess on how one of these should be selected. it passes tests, but is it the right way to do this?
 

wally-pipelined/testbench/testbench-busybear.sv

@@ -167,7 +167,7 @@ module testbench();
 
   // initial loading of memories
   initial begin
-    $readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.RAM, 'h1000 >> 3);
+    $readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.RAM, 'h1000 >> 3); // load at address 0x1000, start of boot TIM
     $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.RAM);
     $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory);
     $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory);