diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index cb670b611..8249f0191 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -34,8 +34,10 @@ module datapath ( // Decode stage signals input logic [2:0] ImmSrcD, // Selects type of immediate extension input logic [31:0] InstrD, // Instruction in Decode stage - input logic [2:0] Funct3E, // Funct3 field of instruction in Execute stage // Execute stage signals + input logic [`XLEN-1:0] PCE, // PC in Execute stage + input logic [`XLEN-1:0] PCLinkE, // PC + 4 (of instruction in Execute stage) + input logic [2:0] Funct3E, // Funct3 field of instruction in Execute stage input logic StallE, FlushE, // Stall, flush Execute stage input logic [1:0] ForwardAE, ForwardBE, // Forward ALU operands from later stages input logic [2:0] ALUControlE, // Indicate operation ALU performs @@ -43,8 +45,6 @@ module datapath ( input logic ALUResultSrcE, // Selects result to pass on to Memory stage input logic JumpE, // Is a jump (j) instruction input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) - input logic [`XLEN-1:0] PCE, // PC in Execute stage - input logic [`XLEN-1:0] PCLinkE, // PC + 4 (of instruction in Execute stage) output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B @@ -77,9 +77,9 @@ module datapath ( logic [`XLEN-1:0] R1E, R2E; // Source operands read from register file logic [`XLEN-1:0] ImmExtE; // Extended immediate in Execute stage logic [`XLEN-1:0] SrcAE, SrcBE; // ALU operands - logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // ALU result, Alternative result (ImmExtE or PC+4), computed address *** According to Figure 4.12, IEUResultE should be called IEUAdrE + logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // ALU result, Alternative result (ImmExtE or PC+4), result of execution stage // Memory stage signals - logic [`XLEN-1:0] IEUResultM; // Address computed by ALU *** According to Figure 4.12, IEUResultM should be called IEUAdrM + logic [`XLEN-1:0] IEUResultM; // Result from execution stage logic [`XLEN-1:0] IFResultM; // Result from either IEU or single-cycle FPU op writing an integer register // Writeback stage signals logic [`XLEN-1:0] SCResultW; // Store Conditional result diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index 765fdca16..db0ddb2cc 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -37,6 +37,7 @@ module ieu ( // Execute stage signals input logic [`XLEN-1:0] PCE, // PC input logic [`XLEN-1:0] PCLinkE, // PC + 4 + output logic PCSrcE, // Select next PC (between PC+4 and IEUAdrE) input logic FWriteIntE, FCvtIntE, // FPU writes to integer register file, FPU converts float to int output logic [`XLEN-1:0] IEUAdrE, // Memory address output logic IntDivE, W64E, // Integer divide, RV64 W-type instruction @@ -66,29 +67,28 @@ module ieu ( input logic FlushD, FlushE, FlushM, FlushW, // Flush signals output logic FCvtIntStallD, LoadStallD, // Stall causes from IEU to hazard unit output logic MDUStallD, CSRRdStallD, StoreStallD, - output logic PCSrcE, // Select next PC (between PC+4 and IEUAdrE) output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction output logic CSRWriteFenceM // CSR write or fence instruction needs to flush subsequent instructions ); - logic [2:0] ImmSrcD; // Select type of immediate extension - logic [1:0] FlagsE; // Comparison flags ({eq, lt}) - logic [2:0] ALUControlE; // ALU Control - logic ALUSrcAE, ALUSrcBE; // ALU source operands - logic [2:0] ResultSrcW; // Source of result in Writeback stage - logic ALUResultSrcE; // ALU result - logic SCE; // Store Conditional instruction - logic FWriteIntM; // FPU writing to integer register file - logic IntDivW; // Integer divide instruction + logic [2:0] ImmSrcD; // Select type of immediate extension + logic [1:0] FlagsE; // Comparison flags ({eq, lt}) + logic [2:0] ALUControlE; // ALU control indicates function to perform + logic ALUSrcAE, ALUSrcBE; // ALU source operands + logic [2:0] ResultSrcW; // Selects result in Writeback stage + logic ALUResultSrcE; // Selects ALU result to pass on to Memory stage + logic SCE; // Store Conditional instruction + logic FWriteIntM; // FPU writing to integer register file + logic IntDivW; // Integer divide instruction - // forwarding signals - logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers - logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers - logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages - logic MemReadE, CSRReadE; // Load, CSRRead instruction - logic JumpE; // Jump instruction - logic BranchSignedE; // Branch does signed comparison on operands - logic MDUE; // Multiply/divide instruction + // Forwarding signals + logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers + logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers + logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages + logic MemReadE, CSRReadE; // Load, CSRRead instruction + logic JumpE; // Jump instruction + logic BranchSignedE; // Branch does signed comparison on operands + logic MDUE; // Multiply/divide instruction controller c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD,