From 74ffb48c0a1a21136a49c70db628f0cbb437ff76 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 2 Dec 2021 17:47:46 -0600 Subject: [PATCH] Mostly integrated FPGA flow into main branch. Not all tests passing yet. --- .../config/buildroot/wally-config.vh | 9 +- .../config/busybear/wally-config.vh | 6 +- .../config/coremark/wally-config.vh | 6 +- .../config/coremark_bare/wally-config.vh | 6 +- wally-pipelined/config/rv32g/wally-config.vh | 7 + wally-pipelined/config/rv32ic/wally-config.vh | 6 +- wally-pipelined/config/rv64BP/wally-config.vh | 6 +- wally-pipelined/config/rv64g/wally-config.vh | 7 + wally-pipelined/config/rv64ic/wally-config.vh | 6 +- wally-pipelined/regression/wally-pipelined.do | 6 +- wally-pipelined/regression/wave.do | 217 +++++++++--------- wally-pipelined/src/sdc/tb/sd_top_tb.sv | 8 + wally-pipelined/src/uncore/dtim.sv | 3 + wally-pipelined/src/uncore/uncore.sv | 2 +- wally-pipelined/testbench/testbench.sv | 20 +- 15 files changed, 187 insertions(+), 128 deletions(-) diff --git a/wally-pipelined/config/buildroot/wally-config.vh b/wally-pipelined/config/buildroot/wally-config.vh index eb2291e2b..f00eda30f 100644 --- a/wally-pipelined/config/buildroot/wally-config.vh +++ b/wally-pipelined/config/buildroot/wally-config.vh @@ -83,15 +83,12 @@ `define BOOTTIM_SUPPORTED 1'b1 `define BOOTTIM_BASE 56'h00001000 `define BOOTTIM_RANGE 56'h00000FFF - -`define TIM_SUPPORTED 1'b0 +`define TIM_SUPPORTED 1'b1 `define TIM_BASE 56'h80000000 `define TIM_RANGE 56'h07FFFFFF - -`define EXT_SUPPORTED 1'b1 +`define EXT_SUPPORTED 1'b0 `define EXT_BASE 56'h80000000 `define EXT_RANGE 56'h07FFFFFF - `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 56'h02000000 `define CLINT_RANGE 56'h0000FFFF @@ -104,7 +101,7 @@ `define PLIC_SUPPORTED 1'b1 `define PLIC_BASE 56'h0C000000 `define PLIC_RANGE 56'h03FFFFFF -`define SDC_SUPPORTED 1'b1 +`define SDC_SUPPORTED 1'b0 `define SDC_BASE 56'h00012100 `define SDC_RANGE 56'h0000001F diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh index 422da7d9e..b248c58a5 100644 --- a/wally-pipelined/config/busybear/wally-config.vh +++ b/wally-pipelined/config/busybear/wally-config.vh @@ -27,6 +27,7 @@ // include shared configuration `include "wally-shared.vh" +`define FPGA 0 `define QEMU 0 `define BUILDROOT 0 `define BUSYBEAR 1 @@ -89,6 +90,9 @@ `define TIM_SUPPORTED 1'b1 `define TIM_BASE 56'h80000000 `define TIM_RANGE 56'h07FFFFFF +`define EXT_MEM_SUPPORTED 1'b0 +`define EXT_MEM_BASE 56'h80000000 +`define EXT_MEM_RANGE 56'h07FFFFFF `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 56'h02000000 `define CLINT_RANGE 56'h0000FFFF @@ -101,7 +105,7 @@ `define PLIC_SUPPORTED 1'b1 `define PLIC_BASE 56'h0C000000 `define PLIC_RANGE 56'h03FFFFFF -`define SDC_SUPPORTED 1'b1 +`define SDC_SUPPORTED 1'b0 `define SDC_BASE 56'h00012100 `define SDC_RANGE 56'h0000001F diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh index 1c23f2fd4..ceb546ff6 100644 --- a/wally-pipelined/config/coremark/wally-config.vh +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -27,6 +27,7 @@ // include shared configuration `include "wally-shared.vh" +`define FPGA 0 `define QEMU 0 `define BUILDROOT 0 `define BUSYBEAR 0 @@ -90,6 +91,9 @@ `define TIM_SUPPORTED 1'b1 `define TIM_BASE 34'h80000000 `define TIM_RANGE 34'h07FFFFFF +`define EXT_MEM_SUPPORTED 1'b0 +`define EXT_MEM_BASE 56'h80000000 +`define EXT_MEM_RANGE 56'h07FFFFFF `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 34'h02000000 `define CLINT_RANGE 34'h0000FFFF @@ -102,7 +106,7 @@ `define PLIC_SUPPORTED 1'b1 `define PLIC_BASE 34'h0C000000 `define PLIC_RANGE 34'h03FFFFFF -`define SDC_SUPPORTED 1'b1 +`define SDC_SUPPORTED 1'b0 `define SDC_BASE 56'h00012100 `define SDC_RANGE 56'h0000001F diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index ff8852e60..ae479a25b 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -27,6 +27,7 @@ // include shared configuration `include "wally-shared.vh" +`define FPGA 0 `define QEMU 0 `define BUILDROOT 0 `define BUSYBEAR 0 @@ -94,6 +95,9 @@ `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 56'h02000000 `define CLINT_RANGE 56'h0000FFFF +`define EXT_MEM_SUPPORTED 1'b0 +`define EXT_MEM_BASE 56'h80000000 +`define EXT_MEM_RANGE 56'h07FFFFFF `define GPIO_SUPPORTED 1'b1 `define GPIO_BASE 56'h10012000 `define GPIO_RANGE 56'h000000FF @@ -103,7 +107,7 @@ `define PLIC_SUPPORTED 1'b1 `define PLIC_BASE 56'h0C000000 `define PLIC_RANGE 56'h03FFFFFF -`define SDC_SUPPORTED 1'b1 +`define SDC_SUPPORTED 1'b0 `define SDC_BASE 56'h00012100 `define SDC_RANGE 56'h0000001F diff --git a/wally-pipelined/config/rv32g/wally-config.vh b/wally-pipelined/config/rv32g/wally-config.vh index c4ce6f628..006981201 100644 --- a/wally-pipelined/config/rv32g/wally-config.vh +++ b/wally-pipelined/config/rv32g/wally-config.vh @@ -27,6 +27,7 @@ // include shared configuration `include "wally-shared.vh" +`define FPGA 0 `define QEMU 0 `define BUILDROOT 0 `define BUSYBEAR 0 @@ -84,6 +85,9 @@ `define TIM_SUPPORTED 1'b1 `define TIM_BASE 34'h80000000 `define TIM_RANGE 34'h07FFFFFF +`define EXT_MEM_SUPPORTED 1'b0 +`define EXT_MEM_BASE 34'h80000000 +`define EXT_MEM_RANGE 34'h07FFFFFF `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 34'h02000000 `define CLINT_RANGE 34'h0000FFFF @@ -96,6 +100,9 @@ `define PLIC_SUPPORTED 1'b1 `define PLIC_BASE 34'h0C000000 `define PLIC_RANGE 34'h03FFFFFF +`define SDC_SUPPORTED 1'b0 +`define SDC_BASE 34'h00012100 +`define SDC_RANGE 34'h0000001F // Bus Interface width `define AHBW 32 diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index ea36d23c6..b48417739 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -27,6 +27,7 @@ // include shared configuration `include "wally-shared.vh" +`define FPGA 0 `define QEMU 0 `define BUILDROOT 0 `define BUSYBEAR 0 @@ -84,6 +85,9 @@ `define TIM_SUPPORTED 1'b1 `define TIM_BASE 34'h80000000 `define TIM_RANGE 34'h07FFFFFF +`define EXT_MEM_SUPPORTED 1'b0 +`define EXT_MEM_BASE 34'h80000000 +`define EXT_MEM_RANGE 34'h07FFFFFF `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 34'h02000000 `define CLINT_RANGE 34'h0000FFFF @@ -96,7 +100,7 @@ `define PLIC_SUPPORTED 1'b1 `define PLIC_BASE 34'h0C000000 `define PLIC_RANGE 34'h03FFFFFF -`define SDC_SUPPORTED 1'b1 +`define SDC_SUPPORTED 1'b0 `define SDC_BASE 34'h00012100 `define SDC_RANGE 34'h0000001F diff --git a/wally-pipelined/config/rv64BP/wally-config.vh b/wally-pipelined/config/rv64BP/wally-config.vh index 76a2b6f5a..246901583 100644 --- a/wally-pipelined/config/rv64BP/wally-config.vh +++ b/wally-pipelined/config/rv64BP/wally-config.vh @@ -28,6 +28,7 @@ `include "wally-shared.vh" // RV32 or RV64: XLEN = 32 or 64 +`define FPGA 0 `define QEMU 0 `define BUILDROOT 0 `define BUSYBEAR 0 @@ -89,6 +90,9 @@ `define TIM_SUPPORTED 1'b1 `define TIM_BASE 56'h80000000 `define TIM_RANGE 56'h07FFFFFF +`define EXT_MEM_SUPPORTED 1'b0 +`define EXT_MEM_BASE 56'h80000000 +`define EXT_MEM_RANGE 56'h07FFFFFF `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 56'h02000000 `define CLINT_RANGE 56'h0000FFFF @@ -101,7 +105,7 @@ `define PLIC_SUPPORTED 1'b1 `define PLIC_BASE 56'h0C000000 `define PLIC_RANGE 56'h03FFFFFF -`define SDC_SUPPORTED 1'b1 +`define SDC_SUPPORTED 1'b0 `define SDC_BASE 56'h00012100 `define SDC_RANGE 56'h0000001F diff --git a/wally-pipelined/config/rv64g/wally-config.vh b/wally-pipelined/config/rv64g/wally-config.vh index d0ead2cdc..d8378ab96 100644 --- a/wally-pipelined/config/rv64g/wally-config.vh +++ b/wally-pipelined/config/rv64g/wally-config.vh @@ -27,6 +27,7 @@ // include shared configuration `include "wally-shared.vh" +`define FPGA 0 `define QEMU 0 `define BUILDROOT 0 `define BUSYBEAR 0 @@ -90,6 +91,9 @@ `define TIM_SUPPORTED 1'b1 `define TIM_BASE 56'h80000000 `define TIM_RANGE 56'h7FFFFFFF +`define EXT_MEM_SUPPORTED 1'b0 +`define EXT_MEM_BASE 56'h80000000 +`define EXT_MEM_RANGE 56'h07FFFFFF `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 56'h02000000 `define CLINT_RANGE 56'h0000FFFF @@ -102,6 +106,9 @@ `define PLIC_SUPPORTED 1'b1 `define PLIC_BASE 56'h0C000000 `define PLIC_RANGE 56'h03FFFFFF +`define SDC_SUPPORTED 1'b0 +`define SDC_BASE 56'h00012100 +`define SDC_RANGE 56'h0000001F // Test modes diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index c6991e3b0..afd2e8d61 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -27,6 +27,7 @@ // include shared configuration `include "wally-shared.vh" +`define FPGA 0 `define QEMU 0 `define BUILDROOT 0 `define BUSYBEAR 0 @@ -90,6 +91,9 @@ `define TIM_SUPPORTED 1'b1 `define TIM_BASE 56'h80000000 `define TIM_RANGE 56'h7FFFFFFF +`define EXT_MEM_SUPPORTED 1'b0 +`define EXT_MEM_BASE 56'h80000000 +`define EXT_MEM_RANGE 56'h07FFFFFF `define CLINT_SUPPORTED 1'b1 `define CLINT_BASE 56'h02000000 `define CLINT_RANGE 56'h0000FFFF @@ -102,7 +106,7 @@ `define PLIC_SUPPORTED 1'b1 `define PLIC_BASE 56'h0C000000 `define PLIC_RANGE 56'h03FFFFFF -`define SDC_SUPPORTED 1'b1 +`define SDC_SUPPORTED 1'b0 `define SDC_BASE 56'h00012100 `define SDC_RANGE 56'h0000001F diff --git a/wally-pipelined/regression/wally-pipelined.do b/wally-pipelined/regression/wally-pipelined.do index 50177ae2f..620e72257 100644 --- a/wally-pipelined/regression/wally-pipelined.do +++ b/wally-pipelined/regression/wally-pipelined.do @@ -37,13 +37,15 @@ vlib work #} # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals -vlog -lint +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 +vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 vopt +acc work.testbench -G TEST=$2 -o workopt vsim workopt view wave -- display input and output signals as hexidecimal values -do ./wave-dos/peripheral-waves.do +#do ./wave-dos/peripheral-waves.do +add log -recursive /* +do wave.do -- Run the Simulation #run 3600 diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index a14ad4dfa..8bff207f1 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -4,115 +4,116 @@ add wave -noupdate /testbench/clk add wave -noupdate /testbench/reset add wave -noupdate /testbench/test add wave -noupdate /testbench/memfilename -add wave -noupdate /testbench/dut/wallypipelinedsoc/hart/SATP_REGW -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/wallypipelinedsoc/hart/ifu/PCE +add wave -noupdate /testbench/dut/hart/SATP_REGW +add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName +add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -expand -group {Execution Stage} /testbench/dut/wallypipelinedsoc/hart/ifu/InstrE -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/wallypipelinedsoc/hart/priv/trap/InstrValidM -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/wallypipelinedsoc/hart/PCM +add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/wallypipelinedsoc/hart/InstrM -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/wallypipelinedsoc/hart/lsu/MemAdrM -add wave -noupdate /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ResultM -add wave -noupdate /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ResultW -add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/EcallFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/StorePageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/hart/priv/trap/InterruptM -add wave -noupdate -group HDU -group interrupts /testbench/dut/wallypipelinedsoc/hart/priv/trap/PendingIntsM -add wave -noupdate -group HDU -group interrupts /testbench/dut/wallypipelinedsoc/hart/priv/trap/CommittedM -add wave -noupdate -group HDU -group interrupts /testbench/dut/wallypipelinedsoc/hart/priv/trap/InstrValidM -add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/BPPredWrongE -add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/CSRWritePendingDEM -add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/RetM -add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/TrapM -add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/LoadStallD -add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/StoreStallD -add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/ICacheStallF -add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/hzu/LSUStall -add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/hart/MulDivStallD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/hart/hzu/FlushF -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/hart/FlushD -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/hart/FlushE -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/hart/FlushM -add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/hart/FlushW -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/hart/StallF -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/hart/StallD -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/hart/StallE -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/hart/StallM -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/hart/StallW -add wave -noupdate -group Bpred -color Orange /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]} -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM +add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM +add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR +add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF +add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} +add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]} +add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check} -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong -add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel -add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext -add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN -add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr -add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0 -add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1 -add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1 -add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BPPredF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BTBValidF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BPInstrClassF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BTBPredPCF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/RASPCF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/TargetPredictor/TargetPC -add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BPPredE -add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/PCSrcE -add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BPPredDirWrongE -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/TargetPredictor/UpdateEN -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/TargetPredictor/UpdatePC -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget -add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr -add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PCE -add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1 -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/TargetWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/FallThroughWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/PredictionPCWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/InstrClassE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/PredictionInstrClassWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/hart/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -group {instruction pipeline} /testbench/InstrFName -add wave -noupdate -group {instruction pipeline} /testbench/dut/wallypipelinedsoc/hart/ifu/icache/FinalInstrRawF -add wave -noupdate -group {instruction pipeline} /testbench/dut/wallypipelinedsoc/hart/ifu/InstrD -add wave -noupdate -group {instruction pipeline} /testbench/dut/wallypipelinedsoc/hart/ifu/InstrE -add wave -noupdate -group {instruction pipeline} /testbench/dut/wallypipelinedsoc/hart/ifu/InstrM -add wave -noupdate -group {instruction pipeline} /testbench/InstrW -add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/PCNextF -add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/PCF -add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/PCPlus2or4F -add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/BPPredPCF -add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/PCNext0F -add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/PCNext1F -add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/SelBPPredF -add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/BPPredWrongE -add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/hart/ifu/PrivilegedChangePCM -add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/hart/ifu/InstrD +add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI +add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI +add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI +add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight +add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong +add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel +add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext +add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN +add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr +add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0 +add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1 +add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN +add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup +add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF +add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1 +add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/hart/ifu/bpred/bpred/BPPredF +add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBValidF +add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPInstrClassF +add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBPredPCF +add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/RASPCF +add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex +add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/TargetPC +add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/hart/ifu/bpred/bpred/BPPredE +add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/hart/ifu/bpred/bpred/PCSrcE +add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/hart/ifu/bpred/bpred/BPPredDirWrongE +add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex +add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget +add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateEN +add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePC +add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget +add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr +add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PCE +add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1 +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/TargetWrongE +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/FallThroughWrongE +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionPCWrongE +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/InstrClassE +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionInstrClassWrongE +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE +add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE +add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE +add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM +add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrW +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE +add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM +add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD add wave -noupdate -group {Decode Stage} /testbench/InstrDName add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD @@ -535,7 +536,7 @@ add wave -noupdate /testbench/dut/hart/ifu/icache/PCTagF add wave -noupdate /testbench/dut/hart/ifu/icache/PCPSpillF add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheReadEn TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 6} {598422 ns} 0} {{Cursor 3} {603500 ns} 1} +WaveRestoreCursors {{Cursor 6} {122378 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 297 @@ -551,4 +552,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {209690 ns} {1301658 ns} +WaveRestoreZoom {122227 ns} {122479 ns} diff --git a/wally-pipelined/src/sdc/tb/sd_top_tb.sv b/wally-pipelined/src/sdc/tb/sd_top_tb.sv index 21ce7fd5b..5a3f54939 100644 --- a/wally-pipelined/src/sdc/tb/sd_top_tb.sv +++ b/wally-pipelined/src/sdc/tb/sd_top_tb.sv @@ -44,6 +44,11 @@ module sd_top_tb(); logic o_DATA_VALID; logic o_LAST_NIBBLE; logic [4095:0] ReadData; + logic o_SD_RESTARTING; + logic [2:0] o_ERROR_CODE_Q; + logic o_FATAL_ERROR; + + // Driver wire PAD; @@ -63,6 +68,9 @@ module sd_top_tb(); .o_SD_CLK(o_SD_CLK), .i_BLOCK_ADDR(i_BLOCK_ADDR), .o_READY_FOR_READ(o_READY_FOR_READ), + .o_SD_RESTARTING(o_SD_RESTARTING), + .o_ERROR_CODE_Q(o_ERROR_CODE_Q), + .o_FATAL_ERROR(o_FATAL_ERROR), .i_READ_REQUEST(i_READ_REQUEST), .o_DATA_TO_CORE(o_DATA_TO_CORE), .ReadData(ReadData), diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv index b01182f76..0ebededc9 100644 --- a/wally-pipelined/src/uncore/dtim.sv +++ b/wally-pipelined/src/uncore/dtim.sv @@ -51,6 +51,8 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") ( initial begin //$readmemh(PRELOAD, RAM); +/* -----\/----- EXCLUDED -----\/----- + // FPGA only RAM[0] = 64'h94e1819300002197; RAM[1] = 64'h4281420141014081; RAM[2] = 64'h4481440143814301; @@ -93,6 +95,7 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") ( RAM[39] = 64'h1047278367498082; RAM[40] = 64'h67c98082dfed8b85; RAM[41] = 64'h0000808210a7a023; + -----/\----- EXCLUDED -----/\----- */ end assign initTrans = HREADY & HSELTim & (HTRANS != 2'b00); diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv index 7766abb39..8e3998e90 100644 --- a/wally-pipelined/src/uncore/uncore.sv +++ b/wally-pipelined/src/uncore/uncore.sv @@ -157,7 +157,7 @@ module uncore ( HSELUARTD & HRESPUART | HSELSDC & HRESPSDC; - assign HREADY = HSELTimD & HREADTim | + assign HREADY = HSELTimD & HREADYTim | HSELEXTD & HREADYEXT | HSELCLINTD & HREADYCLINT | HSELPLICD & HREADYPLIC | diff --git a/wally-pipelined/testbench/testbench.sv b/wally-pipelined/testbench/testbench.sv index ee806286c..14a7b8d56 100644 --- a/wally-pipelined/testbench/testbench.sv +++ b/wally-pipelined/testbench/testbench.sv @@ -129,6 +129,16 @@ logic [3:0] dummy; logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic UARTSin, UARTSout; + logic SDCCLK; + logic SDCCmdIn; + logic SDCCmdOut; + logic SDCCmdOE; + logic [3:0] SDCDatIn; + + logic HREADY; + logic HSELEXT; + + // instantiate device to be tested assign GPIOPinsIn = 0; assign UARTSin = 1; @@ -165,7 +175,7 @@ logic [3:0] dummy; // *** broken because DTIM also drives RAM if (`TESTSBP) begin for (i=MemStartAddr; i