diff --git a/wally-pipelined/regression/wally-buildroot-batch.do b/wally-pipelined/regression/wally-buildroot-batch.do
index c16655e1e..bca3ca35e 100644
--- a/wally-pipelined/regression/wally-buildroot-batch.do
+++ b/wally-pipelined/regression/wally-buildroot-batch.do
@@ -25,7 +25,7 @@ vlib work-buildroot
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
-vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../src/*/*.sv -suppress 2583
+vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
# start and run simulation
diff --git a/wally-pipelined/regression/wally-buildroot.do b/wally-pipelined/regression/wally-buildroot.do
index 452ba54d4..1f4a15a5c 100644
--- a/wally-pipelined/regression/wally-buildroot.do
+++ b/wally-pipelined/regression/wally-buildroot.do
@@ -25,7 +25,7 @@ vlib work-buildroot
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
-vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../src/*/*.sv -suppress 2583
+vlog +incdir+../config/buildroot +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
# start and run simulation
@@ -34,10 +34,15 @@ vopt +acc work.testbench -o workopt
vsim workopt -suppress 8852,12070
+run 100 ns
+add log -r /*
#-- Run the Simulation
-run -all
-do ./wave-dos/linux-waves.do
-run -all
+#run -all
+#do ./wave-dos/linux-waves.do
+#run 60 ms
+do wave.do
+#run -all
+
exec ./slack-notifier/slack-notifier.py
##quit
diff --git a/wally-pipelined/regression/wally-busybear-batch.do b/wally-pipelined/regression/wally-busybear-batch.do
index e9beed4ce..1bcc164ea 100644
--- a/wally-pipelined/regression/wally-busybear-batch.do
+++ b/wally-pipelined/regression/wally-busybear-batch.do
@@ -26,7 +26,7 @@ vlib work_busybear
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
-vlog -work work_busybear +incdir+../config/busybear +incdir+../config/shared ../testbench/testbench-linux.sv ../src/*/*.sv -suppress 2583
+vlog -work work_busybear +incdir+../config/busybear +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
# start and run simulation
diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do
index 204d1c4e4..9a567402a 100644
--- a/wally-pipelined/regression/wally-busybear.do
+++ b/wally-pipelined/regression/wally-busybear.do
@@ -26,7 +26,7 @@ vlib work-busybear
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
-vlog +incdir+../config/busybear +incdir+../config/shared ../testbench/testbench-linux.sv ../src/*/*.sv -suppress 2583
+vlog +incdir+../config/busybear +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
# start and run simulation
diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do
index 1c54f015f..401da0d6d 100644
--- a/wally-pipelined/regression/wally-coremark_bare.do
+++ b/wally-pipelined/regression/wally-coremark_bare.do
@@ -28,7 +28,7 @@ vlib work
# because vsim will run vopt
# default to config/coremark, but allow this to be overridden at the command line. For example:
-vlog +incdir+../config/coremark_bare +incdir+../config/shared ../testbench/testbench-coremark_bare.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583
+vlog +incdir+../config/coremark_bare +incdir+../config/shared ../testbench/testbench-coremark_bare.sv ../testbench/common/*.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
diff --git a/wally-pipelined/regression/wally-pipelined-batch-muldiv.do b/wally-pipelined/regression/wally-pipelined-batch-muldiv.do
index c1d6410f6..cef5619eb 100644
--- a/wally-pipelined/regression/wally-pipelined-batch-muldiv.do
+++ b/wally-pipelined/regression/wally-pipelined-batch-muldiv.do
@@ -30,9 +30,9 @@ vlib work_$2
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined-batch.do ../config/rv32ic rv32ic
switch $argc {
- 0 {vlog +incdir+../config/rv64imc +incdir+../config/shared ../testbench/testbench-imperas-div.sv ../src/*/*.sv -suppress 2583}
- 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas-div.sv ../src/*/*.sv -suppress 2583}
- 2 {vlog -work work_$2 +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas-div.sv ../src/*/*.sv -suppress 2583}
+ 0 {vlog +incdir+../config/rv64imc +incdir+../config/shared ../testbench/testbench-imperas-div.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
+ 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas-div.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
+ 2 {vlog -work work_$2 +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas-div.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
}
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
diff --git a/wally-pipelined/regression/wally-pipelined-batch-rv32icfd.do b/wally-pipelined/regression/wally-pipelined-batch-rv32icfd.do
index 00ad9f080..048663194 100644
--- a/wally-pipelined/regression/wally-pipelined-batch-rv32icfd.do
+++ b/wally-pipelined/regression/wally-pipelined-batch-rv32icfd.do
@@ -29,9 +29,9 @@ vlib work_$2
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
switch $argc {
- 0 {vlog +incdir+../config/rv32icfd +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
- 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
- 2 {vlog -work work_$2 +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
+ 0 {vlog +incdir+../config/rv32icfd +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
+ 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
+ 2 {vlog -work work_$2 +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
}
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
diff --git a/wally-pipelined/regression/wally-pipelined-batch-rv64icfd.do b/wally-pipelined/regression/wally-pipelined-batch-rv64icfd.do
index e6e158ebd..efa90d038 100644
--- a/wally-pipelined/regression/wally-pipelined-batch-rv64icfd.do
+++ b/wally-pipelined/regression/wally-pipelined-batch-rv64icfd.do
@@ -30,9 +30,9 @@ vlib work_$2
# default to config/rv64icfd, but allow this to be overridden at the command line. For example:
# do wally-pipelined-batch.do ../config/rv32ic rv32ic
switch $argc {
- 0 {vlog +incdir+../config/rv64icfd +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
- 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
- 2 {vlog -work work_$2 +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
+ 0 {vlog +incdir+../config/rv64icfd +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
+ 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
+ 2 {vlog -work work_$2 +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
}
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
diff --git a/wally-pipelined/regression/wally-pipelined-batch.do b/wally-pipelined/regression/wally-pipelined-batch.do
index 1e67b836e..28b866973 100644
--- a/wally-pipelined/regression/wally-pipelined-batch.do
+++ b/wally-pipelined/regression/wally-pipelined-batch.do
@@ -30,9 +30,9 @@ vlib work_$2
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined-batch.do ../config/rv32ic rv32ic
switch $argc {
- 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
- 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
- 2 {vlog -work work_$2 +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
+ 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
+ 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
+ 2 {vlog -work work_$2 +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
}
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
diff --git a/wally-pipelined/regression/wally-pipelined-muldiv.do b/wally-pipelined/regression/wally-pipelined-muldiv.do
index 746ba1163..f40d0c5d5 100644
--- a/wally-pipelined/regression/wally-pipelined-muldiv.do
+++ b/wally-pipelined/regression/wally-pipelined-muldiv.do
@@ -30,8 +30,8 @@ vlib work
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined.do ../config/rv32ic
switch $argc {
- 0 {vlog +incdir+../config/rv64imc +incdir+../config/shared ../testbench/testbench-imperas-div.sv ../src/*/*.sv -suppress 2583}
- 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas-div.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
+ 0 {vlog +incdir+../config/rv64imc +incdir+../config/shared ../testbench/testbench-imperas-div.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
+ 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas-div.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
}
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
diff --git a/wally-pipelined/regression/wally-pipelined-ross.do b/wally-pipelined/regression/wally-pipelined-ross.do
index 15a515de5..a8c15c4e7 100644
--- a/wally-pipelined/regression/wally-pipelined-ross.do
+++ b/wally-pipelined/regression/wally-pipelined-ross.do
@@ -30,8 +30,8 @@ vlib work
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined.do ../config/rv32ic
switch $argc {
- 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
- 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
+ 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
+ 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
}
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
diff --git a/wally-pipelined/regression/wally-pipelined-rv32icfd.do b/wally-pipelined/regression/wally-pipelined-rv32icfd.do
index eb3f3e127..0a1f49056 100644
--- a/wally-pipelined/regression/wally-pipelined-rv32icfd.do
+++ b/wally-pipelined/regression/wally-pipelined-rv32icfd.do
@@ -30,8 +30,8 @@ vlib work
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined.do ../config/rv32ic
switch $argc {
- 0 {vlog +incdir+../config/rv32icfd +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
- 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
+ 0 {vlog +incdir+../config/rv32icfd +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
+ 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
}
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
diff --git a/wally-pipelined/regression/wally-pipelined-rv64icfd.do b/wally-pipelined/regression/wally-pipelined-rv64icfd.do
index 39f62903f..3b9fcfc68 100644
--- a/wally-pipelined/regression/wally-pipelined-rv64icfd.do
+++ b/wally-pipelined/regression/wally-pipelined-rv64icfd.do
@@ -30,8 +30,8 @@ vlib work
# default to config/rv64icfd, but allow this to be overridden at the command line. For example:
# do wally-pipelined.do ../config/rv32ic
switch $argc {
- 0 {vlog +incdir+../config/rv64icfd +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
- 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
+ 0 {vlog +incdir+../config/rv64icfd +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
+ 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
}
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
diff --git a/wally-pipelined/regression/wally-pipelined.do b/wally-pipelined/regression/wally-pipelined.do
index f1faffa73..861657308 100644
--- a/wally-pipelined/regression/wally-pipelined.do
+++ b/wally-pipelined/regression/wally-pipelined.do
@@ -30,8 +30,8 @@ vlib work
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined.do ../config/rv32ic
switch $argc {
- 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
- 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
+ 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
+ 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
}
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
diff --git a/wally-pipelined/regression/wally-privileged.do b/wally-pipelined/regression/wally-privileged.do
index 21507c461..b0b8186ff 100644
--- a/wally-pipelined/regression/wally-privileged.do
+++ b/wally-pipelined/regression/wally-privileged.do
@@ -30,8 +30,8 @@ vlib work
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
# do wally-pipelined.do ../config/rv32ic
switch $argc {
- 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
- 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583}
+ 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
+ 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench-imperas.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583}
}
# start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
diff --git a/wally-pipelined/testbench/function_radix.sv b/wally-pipelined/testbench/common/function_radix.sv
similarity index 100%
rename from wally-pipelined/testbench/function_radix.sv
rename to wally-pipelined/testbench/common/function_radix.sv
diff --git a/wally-pipelined/testbench/common/instrNameDecTB.sv b/wally-pipelined/testbench/common/instrNameDecTB.sv
new file mode 100644
index 000000000..ba2c9bba1
--- /dev/null
+++ b/wally-pipelined/testbench/common/instrNameDecTB.sv
@@ -0,0 +1,260 @@
+// decode the instruction name, to help the test bench
+module instrNameDecTB(
+ input logic [31:0] instr,
+ output string name);
+
+ logic [6:0] op;
+ logic [2:0] funct3;
+ logic [6:0] funct7;
+ logic [11:0] imm;
+ logic [4:0] rs2;
+
+ assign op = instr[6:0];
+ assign funct3 = instr[14:12];
+ assign funct7 = instr[31:25];
+ assign imm = instr[31:20];
+ assign rs2 = instr[24:20];
+
+ // it would be nice to add the operands to the name
+ // create another variable called decoded
+
+ always_comb
+ casez({op, funct3})
+ 10'b0000000_000: name = "BAD";
+ 10'b0000011_000: name = "LB";
+ 10'b0000011_001: name = "LH";
+ 10'b0000011_010: name = "LW";
+ 10'b0000011_011: name = "LD";
+ 10'b0000011_100: name = "LBU";
+ 10'b0000011_101: name = "LHU";
+ 10'b0000011_110: name = "LWU";
+ 10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH";
+ else name = "ADDI";
+ 10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
+ else name = "ILLEGAL";
+ 10'b0010011_010: name = "SLTI";
+ 10'b0010011_011: name = "SLTIU";
+ 10'b0010011_100: name = "XORI";
+ 10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI";
+ else if (funct7[6:1] == 6'b010000) name = "SRAI";
+ else name = "ILLEGAL";
+ 10'b0010011_110: name = "ORI";
+ 10'b0010011_111: name = "ANDI";
+ 10'b0010111_???: name = "AUIPC";
+ 10'b0100011_000: name = "SB";
+ 10'b0100011_001: name = "SH";
+ 10'b0100011_010: name = "SW";
+ 10'b0100011_011: name = "SD";
+ 10'b0011011_000: name = "ADDIW";
+ 10'b0011011_001: name = "SLLIW";
+ 10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW";
+ else if (funct7 == 7'b0100000) name = "SRAIW";
+ else name = "ILLEGAL";
+ 10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW";
+ else if (funct7 == 7'b0100000) name = "SUBW";
+ else if (funct7 == 7'b0000001) name = "MULW";
+ else name = "ILLEGAL";
+ 10'b0111011_001: if (funct7 == 7'b0000000) name = "SLLW";
+ else if (funct7 == 7'b0000001) name = "DIVW";
+ else name = "ILLEGAL";
+ 10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW";
+ else if (funct7 == 7'b0100000) name = "SRAW";
+ else if (funct7 == 7'b0000001) name = "DIVUW";
+ else name = "ILLEGAL";
+ 10'b0111011_110: if (funct7 == 7'b0000001) name = "REMW";
+ else name = "ILLEGAL";
+ 10'b0111011_111: if (funct7 == 7'b0000001) name = "REMUW";
+ else name = "ILLEGAL";
+ 10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
+ else if (funct7 == 7'b0000001) name = "MUL";
+ else if (funct7 == 7'b0100000) name = "SUB";
+ else name = "ILLEGAL";
+ 10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL";
+ else if (funct7 == 7'b0000001) name = "MULH";
+ else name = "ILLEGAL";
+ 10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT";
+ else if (funct7 == 7'b0000001) name = "MULHSU";
+ else name = "ILLEGAL";
+ 10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU";
+ else if (funct7 == 7'b0000001) name = "MULHU";
+ else name = "ILLEGAL";
+ 10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR";
+ else if (funct7 == 7'b0000001) name = "DIV";
+ else name = "ILLEGAL";
+ 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
+ else if (funct7 == 7'b0000001) name = "DIVU";
+ else if (funct7 == 7'b0100000) name = "SRA";
+ else name = "ILLEGAL";
+ 10'b0110011_110: if (funct7 == 7'b0000000) name = "OR";
+ else if (funct7 == 7'b0000001) name = "REM";
+ else name = "ILLEGAL";
+ 10'b0110011_111: if (funct7 == 7'b0000000) name = "AND";
+ else if (funct7 == 7'b0000001) name = "REMU";
+ else name = "ILLEGAL";
+ 10'b0110111_???: name = "LUI";
+ 10'b1100011_000: name = "BEQ";
+ 10'b1100011_001: name = "BNE";
+ 10'b1100011_100: name = "BLT";
+ 10'b1100011_101: name = "BGE";
+ 10'b1100011_110: name = "BLTU";
+ 10'b1100011_111: name = "BGEU";
+ 10'b1100111_000: name = "JALR";
+ 10'b1101111_???: name = "JAL";
+ 10'b1110011_000: if (imm == 0) name = "ECALL";
+ else if (imm == 1) name = "EBREAK";
+ else if (imm == 2) name = "URET";
+ else if (imm == 258) name = "SRET";
+ else if (imm == 770) name = "MRET";
+ else if (funct7 == 9) name = "SFENCE.VMA";
+ else name = "ILLEGAL";
+ 10'b1110011_001: name = "CSRRW";
+ 10'b1110011_010: name = "CSRRS";
+ 10'b1110011_011: name = "CSRRC";
+ 10'b1110011_101: name = "CSRRWI";
+ 10'b1110011_110: name = "CSRRSI";
+ 10'b1110011_111: name = "CSRRCI";
+ 10'b0101111_010: if (funct7[6:2] == 5'b00010) name = "LR.W";
+ else if (funct7[6:2] == 5'b00011) name = "SC.W";
+ else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.W";
+ else if (funct7[6:2] == 5'b00000) name = "AMOADD.W";
+ else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.W";
+ else if (funct7[6:2] == 5'b01100) name = "AMOAND.W";
+ else if (funct7[6:2] == 5'b01000) name = "AMOOR.W";
+ else if (funct7[6:2] == 5'b10000) name = "AMOMIN.W";
+ else if (funct7[6:2] == 5'b10100) name = "AMOMAX.W";
+ else if (funct7[6:2] == 5'b11000) name = "AMOMINU.W";
+ else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.W";
+ else name = "ILLEGAL";
+ 10'b0101111_011: if (funct7[6:2] == 5'b00010) name = "LR.D";
+ else if (funct7[6:2] == 5'b00011) name = "SC.D";
+ else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.D";
+ else if (funct7[6:2] == 5'b00000) name = "AMOADD.D";
+ else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.D";
+ else if (funct7[6:2] == 5'b01100) name = "AMOAND.D";
+ else if (funct7[6:2] == 5'b01000) name = "AMOOR.D";
+ else if (funct7[6:2] == 5'b10000) name = "AMOMIN.D";
+ else if (funct7[6:2] == 5'b10100) name = "AMOMAX.D";
+ else if (funct7[6:2] == 5'b11000) name = "AMOMINU.D";
+ else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D";
+ else name = "ILLEGAL";
+ 10'b0001111_???: name = "FENCE";
+ 10'b1000011_???: name = "FMADD";
+ 10'b1000111_???: name = "FMSUB";
+ 10'b1001011_???: name = "FNMSUB";
+ 10'b1001111_???: name = "FNMADD";
+ 10'b1010011_000: if (funct7[6:2] == 5'b00000) name = "FADD";
+ else if (funct7[6:2] == 5'b00001) name = "FSUB";
+ else if (funct7[6:2] == 5'b00010) name = "FMUL";
+ else if (funct7[6:2] == 5'b00011) name = "FDIV";
+ else if (funct7[6:2] == 5'b01011) name = "FSQRT";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
+ else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
+ else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
+ else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
+ else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
+ else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
+ else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
+ else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
+ else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
+ else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
+ else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
+ else if (funct7 == 7'b1110000 && rs2 == 5'b00000) name = "FMV.X.W";
+ else if (funct7 == 7'b1111000 && rs2 == 5'b00000) name = "FMV.W.X";
+ else if (funct7 == 7'b1110001 && rs2 == 5'b00000) name = "FMV.X.D"; // DOUBLE
+ else if (funct7 == 7'b1111001 && rs2 == 5'b00000) name = "FMV.D.X"; // DOUBLE
+ else if (funct7[6:2] == 5'b00100) name = "FSGNJ";
+ else if (funct7[6:2] == 5'b00101) name = "FMIN";
+ else if (funct7[6:2] == 5'b10100) name = "FLE";
+ else name = "ILLEGAL";
+ 10'b1010011_001: if (funct7[6:2] == 5'b00000) name = "FADD";
+ else if (funct7[6:2] == 5'b00001) name = "FSUB";
+ else if (funct7[6:2] == 5'b00010) name = "FMUL";
+ else if (funct7[6:2] == 5'b00011) name = "FDIV";
+ else if (funct7[6:2] == 5'b01011) name = "FSQRT";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
+ else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
+ else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
+ else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
+ else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
+ else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
+ else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
+ else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
+ else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
+ else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
+ else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
+ else if (funct7[6:2] == 5'b00100) name = "FSGNJN";
+ else if (funct7[6:2] == 5'b00101) name = "FMAX";
+ else if (funct7[6:2] == 5'b10100) name = "FLT";
+ else if (funct7[6:2] == 5'b11100) name = "FCLASS";
+ else name = "ILLEGAL";
+ 10'b1010011_010: if (funct7[6:2] == 5'b00000) name = "FADD";
+ else if (funct7[6:2] == 5'b00001) name = "FSUB";
+ else if (funct7[6:2] == 5'b00010) name = "FMUL";
+ else if (funct7[6:2] == 5'b00011) name = "FDIV";
+ else if (funct7[6:2] == 5'b01011) name = "FSQRT";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
+ else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
+ else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
+ else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
+ else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
+ else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
+ else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
+ else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
+ else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
+ else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
+ else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
+ else if (funct7[6:2] == 5'b00100) name = "FSGNJX";
+ else if (funct7[6:2] == 5'b10100) name = "FEQ";
+ else name = "ILLEGAL";
+ 10'b1010011_???: if (funct7[6:2] == 5'b00000) name = "FADD";
+ else if (funct7[6:2] == 5'b00001) name = "FSUB";
+ else if (funct7[6:2] == 5'b00010) name = "FMUL";
+ else if (funct7[6:2] == 5'b00011) name = "FDIV";
+ else if (funct7[6:2] == 5'b01011) name = "FSQRT";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
+ else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
+ else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
+ else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
+ else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
+ else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
+ else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
+ else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
+ else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
+ else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
+ else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
+ else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
+ else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
+ else name = "ILLEGAL";
+ 10'b0000111_010: name = "FLW";
+ 10'b0100111_010: name = "FSW";
+ 10'b0000111_011: name = "FLD";
+ 10'b0100111_011: name = "FSD";
+ default: name = "ILLEGAL";
+ endcase
+endmodule
diff --git a/wally-pipelined/testbench/common/instrTrackerTB.sv b/wally-pipelined/testbench/common/instrTrackerTB.sv
new file mode 100644
index 000000000..0283f6502
--- /dev/null
+++ b/wally-pipelined/testbench/common/instrTrackerTB.sv
@@ -0,0 +1,17 @@
+module instrTrackerTB(
+ input logic clk, reset, FlushE,
+ input logic [31:0] InstrF, InstrD,
+ input logic [31:0] InstrE, InstrM,
+ input logic [31:0] InstrW,
+// output logic [31:0] InstrW,
+ output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
+
+ // stage Instr to Writeback for visualization
+ // flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
+
+ instrNameDecTB fdec(InstrF, InstrFName);
+ instrNameDecTB ddec(InstrD, InstrDName);
+ instrNameDecTB edec(InstrE, InstrEName);
+ instrNameDecTB mdec(InstrM, InstrMName);
+ instrNameDecTB wdec(InstrW, InstrWName);
+endmodule
diff --git a/wally-pipelined/testbench/common/logging.sv b/wally-pipelined/testbench/common/logging.sv
new file mode 100644
index 000000000..bb87accea
--- /dev/null
+++ b/wally-pipelined/testbench/common/logging.sv
@@ -0,0 +1,10 @@
+module logging(
+ input logic clk, reset,
+ input logic [31:0] HADDR,
+ input logic [1:0] HTRANS);
+
+ always @(posedge clk)
+ if (HTRANS != 2'b00 && HADDR == 0)
+ $display("%t Warning: access to memory address 0\n", $realtime);
+endmodule
+
diff --git a/wally-pipelined/testbench/testbench-coremark.sv b/wally-pipelined/testbench/testbench-coremark.sv
index 6c0f81934..82a41d837 100644
--- a/wally-pipelined/testbench/testbench-coremark.sv
+++ b/wally-pipelined/testbench/testbench-coremark.sv
@@ -92,129 +92,3 @@ module testbench();
endmodule
/* verilator lint_on STMTDLY */
/* verilator lint_on WIDTH */
-module instrTrackerTB(
- input logic clk, reset, FlushE,
- input logic [31:0] InstrF, InstrD,
- input logic [31:0] InstrE, InstrM,
- input logic [31:0] InstrW,
- output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
-
- // stage Instr to Writeback for visualization
- instrNameDecTB fdec(InstrF, InstrFName);
- instrNameDecTB ddec(InstrD, InstrDName);
- instrNameDecTB edec(InstrE, InstrEName);
- instrNameDecTB mdec(InstrM, InstrMName);
- instrNameDecTB wdec(InstrW, InstrWName);
-endmodule
-// decode the instruction name, to help the test bench
-module instrNameDecTB(
- input logic [31:0] instr,
- output string name);
- logic [6:0] op;
- logic [2:0] funct3;
- logic [6:0] funct7;
- logic [11:0] imm;
- assign op = instr[6:0];
- assign funct3 = instr[14:12];
- assign funct7 = instr[31:25];
- assign imm = instr[31:20];
- // it would be nice to add the operands to the name
- // create another variable called decoded
- always_comb
- casez({op, funct3})
- 10'b0000000_000: name = "BAD";
- 10'b0000011_000: name = "LB";
- 10'b0000011_001: name = "LH";
- 10'b0000011_010: name = "LW";
- 10'b0000011_011: name = "LD";
- 10'b0000011_100: name = "LBU";
- 10'b0000011_101: name = "LHU";
- 10'b0000011_110: name = "LWU";
- 10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH";
- else name = "ADDI";
- 10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
- else name = "ILLEGAL";
- 10'b0010011_010: name = "SLTI";
- 10'b0010011_011: name = "SLTIU";
- 10'b0010011_100: name = "XORI";
- 10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI";
- else if (funct7[6:1] == 6'b010000) name = "SRAI";
- else name = "ILLEGAL";
- 10'b0010011_110: name = "ORI";
- 10'b0010011_111: name = "ANDI";
- 10'b0010111_???: name = "AUIPC";
- 10'b0100011_000: name = "SB";
- 10'b0100011_001: name = "SH";
- 10'b0100011_010: name = "SW";
- 10'b0100011_011: name = "SD";
- 10'b0011011_000: name = "ADDIW";
- 10'b0011011_001: name = "SLLIW";
- 10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW";
- else if (funct7 == 7'b0100000) name = "SRAIW";
- else name = "ILLEGAL";
- 10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW";
- else if (funct7 == 7'b0100000) name = "SUBW";
- else if (funct7 == 7'b0000001) name = "MULW";
- else name = "ILLEGAL";
- 10'b0111011_001: if (funct7 == 7'b0000000) name = "SLLW";
- else if (funct7 == 7'b0000001) name = "DIVW";
- else name = "ILLEGAL";
- 10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW";
- else if (funct7 == 7'b0100000) name = "SRAW";
- else if (funct7 == 7'b0000001) name = "DIVUW";
- else name = "ILLEGAL";
- 10'b0111011_110: if (funct7 == 7'b0000001) name = "REMW";
- else name = "ILLEGAL";
- 10'b0111011_111: if (funct7 == 7'b0000001) name = "REMUW";
- else name = "ILLEGAL";
- 10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
- else if (funct7 == 7'b0000001) name = "MUL";
- else if (funct7 == 7'b0100000) name = "SUB";
- else name = "ILLEGAL";
- 10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL";
- else if (funct7 == 7'b0000001) name = "MULH";
- else name = "ILLEGAL";
- 10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT";
- else if (funct7 == 7'b0000001) name = "MULHSU";
- else name = "ILLEGAL";
- 10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU";
- else if (funct7 == 7'b0000001) name = "MULHU";
- else name = "ILLEGAL";
- 10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR";
- else if (funct7 == 7'b0000001) name = "DIV";
- else name = "ILLEGAL";
- 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
- else if (funct7 == 7'b0000001) name = "DIVU";
- else if (funct7 == 7'b0100000) name = "SRA";
- else name = "ILLEGAL";
- 10'b0110011_110: if (funct7 == 7'b0000000) name = "OR";
- else if (funct7 == 7'b0000001) name = "REM";
- else name = "ILLEGAL";
- 10'b0110011_111: if (funct7 == 7'b0000000) name = "AND";
- else if (funct7 == 7'b0000001) name = "REMU";
- else name = "ILLEGAL";
- 10'b0110111_???: name = "LUI";
- 10'b1100011_000: name = "BEQ";
- 10'b1100011_001: name = "BNE";
- 10'b1100011_100: name = "BLT";
- 10'b1100011_101: name = "BGE";
- 10'b1100011_110: name = "BLTU";
- 10'b1100011_111: name = "BGEU";
- 10'b1100111_000: name = "JALR";
- 10'b1101111_???: name = "JAL";
- 10'b1110011_000: if (imm == 0) name = "ECALL";
- else if (imm == 1) name = "EBREAK";
- else if (imm == 2) name = "URET";
- else if (imm == 258) name = "SRET";
- else if (imm == 770) name = "MRET";
- else name = "ILLEGAL";
- 10'b1110011_001: name = "CSRRW";
- 10'b1110011_010: name = "CSRRS";
- 10'b1110011_011: name = "CSRRC";
- 10'b1110011_101: name = "CSRRWI";
- 10'b1110011_110: name = "CSRRSI";
- 10'b1110011_111: name = "CSRRCI";
- 10'b0001111_???: name = "FENCE";
- default: name = "ILLEGAL";
- endcase
-endmodule
diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv
index 9c9a4f252..90003e98d 100644
--- a/wally-pipelined/testbench/testbench-coremark_bare.sv
+++ b/wally-pipelined/testbench/testbench-coremark_bare.sv
@@ -110,129 +110,3 @@ module testbench();
endmodule
/* verilator lint_on STMTDLY */
/* verilator lint_on WIDTH */
-module instrTrackerTB(
- input logic clk, reset, FlushE,
- input logic [31:0] InstrF, InstrD,
- input logic [31:0] InstrE, InstrM,
- input logic [31:0] InstrW,
- output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
-
- // stage Instr to Writeback for visualization
- instrNameDecTB fdec(InstrF, InstrFName);
- instrNameDecTB ddec(InstrD, InstrDName);
- instrNameDecTB edec(InstrE, InstrEName);
- instrNameDecTB mdec(InstrM, InstrMName);
- instrNameDecTB wdec(InstrW, InstrWName);
-endmodule
-// decode the instruction name, to help the test bench
-module instrNameDecTB(
- input logic [31:0] instr,
- output string name);
- logic [6:0] op;
- logic [2:0] funct3;
- logic [6:0] funct7;
- logic [11:0] imm;
- assign op = instr[6:0];
- assign funct3 = instr[14:12];
- assign funct7 = instr[31:25];
- assign imm = instr[31:20];
- // it would be nice to add the operands to the name
- // create another variable called decoded
- always_comb
- casez({op, funct3})
- 10'b0000000_000: name = "BAD";
- 10'b0000011_000: name = "LB";
- 10'b0000011_001: name = "LH";
- 10'b0000011_010: name = "LW";
- 10'b0000011_011: name = "LD";
- 10'b0000011_100: name = "LBU";
- 10'b0000011_101: name = "LHU";
- 10'b0000011_110: name = "LWU";
- 10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH";
- else name = "ADDI";
- 10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
- else name = "ILLEGAL";
- 10'b0010011_010: name = "SLTI";
- 10'b0010011_011: name = "SLTIU";
- 10'b0010011_100: name = "XORI";
- 10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI";
- else if (funct7[6:1] == 6'b010000) name = "SRAI";
- else name = "ILLEGAL";
- 10'b0010011_110: name = "ORI";
- 10'b0010011_111: name = "ANDI";
- 10'b0010111_???: name = "AUIPC";
- 10'b0100011_000: name = "SB";
- 10'b0100011_001: name = "SH";
- 10'b0100011_010: name = "SW";
- 10'b0100011_011: name = "SD";
- 10'b0011011_000: name = "ADDIW";
- 10'b0011011_001: name = "SLLIW";
- 10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW";
- else if (funct7 == 7'b0100000) name = "SRAIW";
- else name = "ILLEGAL";
- 10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW";
- else if (funct7 == 7'b0100000) name = "SUBW";
- else if (funct7 == 7'b0000001) name = "MULW";
- else name = "ILLEGAL";
- 10'b0111011_001: if (funct7 == 7'b0000000) name = "SLLW";
- else if (funct7 == 7'b0000001) name = "DIVW";
- else name = "ILLEGAL";
- 10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW";
- else if (funct7 == 7'b0100000) name = "SRAW";
- else if (funct7 == 7'b0000001) name = "DIVUW";
- else name = "ILLEGAL";
- 10'b0111011_110: if (funct7 == 7'b0000001) name = "REMW";
- else name = "ILLEGAL";
- 10'b0111011_111: if (funct7 == 7'b0000001) name = "REMUW";
- else name = "ILLEGAL";
- 10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
- else if (funct7 == 7'b0000001) name = "MUL";
- else if (funct7 == 7'b0100000) name = "SUB";
- else name = "ILLEGAL";
- 10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL";
- else if (funct7 == 7'b0000001) name = "MULH";
- else name = "ILLEGAL";
- 10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT";
- else if (funct7 == 7'b0000001) name = "MULHSU";
- else name = "ILLEGAL";
- 10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU";
- else if (funct7 == 7'b0000001) name = "MULHU";
- else name = "ILLEGAL";
- 10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR";
- else if (funct7 == 7'b0000001) name = "DIV";
- else name = "ILLEGAL";
- 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
- else if (funct7 == 7'b0000001) name = "DIVU";
- else if (funct7 == 7'b0100000) name = "SRA";
- else name = "ILLEGAL";
- 10'b0110011_110: if (funct7 == 7'b0000000) name = "OR";
- else if (funct7 == 7'b0000001) name = "REM";
- else name = "ILLEGAL";
- 10'b0110011_111: if (funct7 == 7'b0000000) name = "AND";
- else if (funct7 == 7'b0000001) name = "REMU";
- else name = "ILLEGAL";
- 10'b0110111_???: name = "LUI";
- 10'b1100011_000: name = "BEQ";
- 10'b1100011_001: name = "BNE";
- 10'b1100011_100: name = "BLT";
- 10'b1100011_101: name = "BGE";
- 10'b1100011_110: name = "BLTU";
- 10'b1100011_111: name = "BGEU";
- 10'b1100111_000: name = "JALR";
- 10'b1101111_???: name = "JAL";
- 10'b1110011_000: if (imm == 0) name = "ECALL";
- else if (imm == 1) name = "EBREAK";
- else if (imm == 2) name = "URET";
- else if (imm == 258) name = "SRET";
- else if (imm == 770) name = "MRET";
- else name = "ILLEGAL";
- 10'b1110011_001: name = "CSRRW";
- 10'b1110011_010: name = "CSRRS";
- 10'b1110011_011: name = "CSRRC";
- 10'b1110011_101: name = "CSRRWI";
- 10'b1110011_110: name = "CSRRSI";
- 10'b1110011_111: name = "CSRRCI";
- 10'b0001111_???: name = "FENCE";
- default: name = "ILLEGAL";
- endcase
-endmodule
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index b3ccaf586..54adf864c 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -156,7 +156,7 @@ string tests32f[] = '{
};
string tests64a[] = '{
- //"rv64a/WALLY-AMO", "2110",
+ "rv64a/WALLY-AMO", "2110",
"rv64a/WALLY-LRSC", "2110"
};
@@ -216,7 +216,6 @@ string tests32f[] = '{
string tests64i[] = '{
//"rv64i/WALLY-PIPELINE-100K", "f7ff0",
- //"rv64i/WALLY-LOAD", "11bf0",
"rv64i/I-ADD-01", "3000",
"rv64i/I-ADDI-01", "3000",
"rv64i/I-ADDIW-01", "3000",
@@ -314,7 +313,7 @@ string tests32f[] = '{
};
string tests32a[] = '{
- //"rv64a/WALLY-AMO", "2110",
+ "rv32a/WALLY-AMO", "2110",
"rv32a/WALLY-LRSC", "2110"
};
@@ -767,296 +766,6 @@ endmodule
/* verilator lint_on STMTDLY */
/* verilator lint_on WIDTH */
-module instrTrackerTB(
- input logic clk, reset, FlushE,
- input logic [31:0] InstrF, InstrD,
- input logic [31:0] InstrE, InstrM,
- input logic [31:0] InstrW,
-// output logic [31:0] InstrW,
- output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
-
- // stage Instr to Writeback for visualization
- // flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
-
- instrNameDecTB fdec(InstrF, InstrFName);
- instrNameDecTB ddec(InstrD, InstrDName);
- instrNameDecTB edec(InstrE, InstrEName);
- instrNameDecTB mdec(InstrM, InstrMName);
- instrNameDecTB wdec(InstrW, InstrWName);
-endmodule
-
-// decode the instruction name, to help the test bench
-module instrNameDecTB(
- input logic [31:0] instr,
- output string name);
-
- logic [6:0] op;
- logic [2:0] funct3;
- logic [6:0] funct7;
- logic [11:0] imm;
- logic [4:0] rs2;
-
- assign op = instr[6:0];
- assign funct3 = instr[14:12];
- assign funct7 = instr[31:25];
- assign imm = instr[31:20];
- assign rs2 = instr[24:20];
-
- // it would be nice to add the operands to the name
- // create another variable called decoded
-
- always_comb
- casez({op, funct3})
- 10'b0000000_000: name = "BAD";
- 10'b0000011_000: name = "LB";
- 10'b0000011_001: name = "LH";
- 10'b0000011_010: name = "LW";
- 10'b0000011_011: name = "LD";
- 10'b0000011_100: name = "LBU";
- 10'b0000011_101: name = "LHU";
- 10'b0000011_110: name = "LWU";
- 10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH";
- else name = "ADDI";
- 10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
- else name = "ILLEGAL";
- 10'b0010011_010: name = "SLTI";
- 10'b0010011_011: name = "SLTIU";
- 10'b0010011_100: name = "XORI";
- 10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI";
- else if (funct7[6:1] == 6'b010000) name = "SRAI";
- else name = "ILLEGAL";
- 10'b0010011_110: name = "ORI";
- 10'b0010011_111: name = "ANDI";
- 10'b0010111_???: name = "AUIPC";
- 10'b0100011_000: name = "SB";
- 10'b0100011_001: name = "SH";
- 10'b0100011_010: name = "SW";
- 10'b0100011_011: name = "SD";
- 10'b0011011_000: name = "ADDIW";
- 10'b0011011_001: name = "SLLIW";
- 10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW";
- else if (funct7 == 7'b0100000) name = "SRAIW";
- else name = "ILLEGAL";
- 10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW";
- else if (funct7 == 7'b0100000) name = "SUBW";
- else if (funct7 == 7'b0000001) name = "MULW";
- else name = "ILLEGAL";
- 10'b0111011_001: if (funct7 == 7'b0000000) name = "SLLW";
- else if (funct7 == 7'b0000001) name = "DIVW";
- else name = "ILLEGAL";
- 10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW";
- else if (funct7 == 7'b0100000) name = "SRAW";
- else if (funct7 == 7'b0000001) name = "DIVUW";
- else name = "ILLEGAL";
- 10'b0111011_110: if (funct7 == 7'b0000001) name = "REMW";
- else name = "ILLEGAL";
- 10'b0111011_111: if (funct7 == 7'b0000001) name = "REMUW";
- else name = "ILLEGAL";
- 10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
- else if (funct7 == 7'b0000001) name = "MUL";
- else if (funct7 == 7'b0100000) name = "SUB";
- else name = "ILLEGAL";
- 10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL";
- else if (funct7 == 7'b0000001) name = "MULH";
- else name = "ILLEGAL";
- 10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT";
- else if (funct7 == 7'b0000001) name = "MULHSU";
- else name = "ILLEGAL";
- 10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU";
- else if (funct7 == 7'b0000001) name = "MULHU";
- else name = "ILLEGAL";
- 10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR";
- else if (funct7 == 7'b0000001) name = "DIV";
- else name = "ILLEGAL";
- 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
- else if (funct7 == 7'b0000001) name = "DIVU";
- else if (funct7 == 7'b0100000) name = "SRA";
- else name = "ILLEGAL";
- 10'b0110011_110: if (funct7 == 7'b0000000) name = "OR";
- else if (funct7 == 7'b0000001) name = "REM";
- else name = "ILLEGAL";
- 10'b0110011_111: if (funct7 == 7'b0000000) name = "AND";
- else if (funct7 == 7'b0000001) name = "REMU";
- else name = "ILLEGAL";
- 10'b0110111_???: name = "LUI";
- 10'b1100011_000: name = "BEQ";
- 10'b1100011_001: name = "BNE";
- 10'b1100011_100: name = "BLT";
- 10'b1100011_101: name = "BGE";
- 10'b1100011_110: name = "BLTU";
- 10'b1100011_111: name = "BGEU";
- 10'b1100111_000: name = "JALR";
- 10'b1101111_???: name = "JAL";
- 10'b1110011_000: if (imm == 0) name = "ECALL";
- else if (imm == 1) name = "EBREAK";
- else if (imm == 2) name = "URET";
- else if (imm == 258) name = "SRET";
- else if (imm == 770) name = "MRET";
- else if (funct7 == 9) name = "SFENCE.VMA";
- else name = "ILLEGAL";
- 10'b1110011_001: name = "CSRRW";
- 10'b1110011_010: name = "CSRRS";
- 10'b1110011_011: name = "CSRRC";
- 10'b1110011_101: name = "CSRRWI";
- 10'b1110011_110: name = "CSRRSI";
- 10'b1110011_111: name = "CSRRCI";
- 10'b0101111_010: if (funct7[6:2] == 5'b00010) name = "LR.W";
- else if (funct7[6:2] == 5'b00011) name = "SC.W";
- else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.W";
- else if (funct7[6:2] == 5'b00000) name = "AMOADD.W";
- else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.W";
- else if (funct7[6:2] == 5'b01100) name = "AMOAND.W";
- else if (funct7[6:2] == 5'b01000) name = "AMOOR.W";
- else if (funct7[6:2] == 5'b10000) name = "AMOMIN.W";
- else if (funct7[6:2] == 5'b10100) name = "AMOMAX.W";
- else if (funct7[6:2] == 5'b11000) name = "AMOMINU.W";
- else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.W";
- else name = "ILLEGAL";
- 10'b0101111_011: if (funct7[6:2] == 5'b00010) name = "LR.D";
- else if (funct7[6:2] == 5'b00011) name = "SC.D";
- else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.D";
- else if (funct7[6:2] == 5'b00000) name = "AMOADD.D";
- else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.D";
- else if (funct7[6:2] == 5'b01100) name = "AMOAND.D";
- else if (funct7[6:2] == 5'b01000) name = "AMOOR.D";
- else if (funct7[6:2] == 5'b10000) name = "AMOMIN.D";
- else if (funct7[6:2] == 5'b10100) name = "AMOMAX.D";
- else if (funct7[6:2] == 5'b11000) name = "AMOMINU.D";
- else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D";
- else name = "ILLEGAL";
- 10'b0001111_???: name = "FENCE";
- 10'b1000011_???: name = "FMADD";
- 10'b1000111_???: name = "FMSUB";
- 10'b1001011_???: name = "FNMSUB";
- 10'b1001111_???: name = "FNMADD";
- 10'b1010011_000: if (funct7[6:2] == 5'b00000) name = "FADD";
- else if (funct7[6:2] == 5'b00001) name = "FSUB";
- else if (funct7[6:2] == 5'b00010) name = "FMUL";
- else if (funct7[6:2] == 5'b00011) name = "FDIV";
- else if (funct7[6:2] == 5'b01011) name = "FSQRT";
- else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
- else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
- else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
- else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
- else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
- else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
- else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
- else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
- else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
- else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
- else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
- else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
- else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
- else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
- else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
- else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
- else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
- else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
- else if (funct7 == 7'b1110000 && rs2 == 5'b00000) name = "FMV.X.W";
- else if (funct7 == 7'b1111000 && rs2 == 5'b00000) name = "FMV.W.X";
- else if (funct7 == 7'b1110001 && rs2 == 5'b00000) name = "FMV.X.D"; // DOUBLE
- else if (funct7 == 7'b1111001 && rs2 == 5'b00000) name = "FMV.D.X"; // DOUBLE
- else if (funct7[6:2] == 5'b00100) name = "FSGNJ";
- else if (funct7[6:2] == 5'b00101) name = "FMIN";
- else if (funct7[6:2] == 5'b10100) name = "FLE";
- else name = "ILLEGAL";
- 10'b1010011_001: if (funct7[6:2] == 5'b00000) name = "FADD";
- else if (funct7[6:2] == 5'b00001) name = "FSUB";
- else if (funct7[6:2] == 5'b00010) name = "FMUL";
- else if (funct7[6:2] == 5'b00011) name = "FDIV";
- else if (funct7[6:2] == 5'b01011) name = "FSQRT";
- else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
- else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
- else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
- else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
- else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
- else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
- else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
- else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
- else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
- else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
- else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
- else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
- else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
- else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
- else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
- else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
- else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
- else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
- else if (funct7[6:2] == 5'b00100) name = "FSGNJN";
- else if (funct7[6:2] == 5'b00101) name = "FMAX";
- else if (funct7[6:2] == 5'b10100) name = "FLT";
- else if (funct7[6:2] == 5'b11100) name = "FCLASS";
- else name = "ILLEGAL";
- 10'b1010011_010: if (funct7[6:2] == 5'b00000) name = "FADD";
- else if (funct7[6:2] == 5'b00001) name = "FSUB";
- else if (funct7[6:2] == 5'b00010) name = "FMUL";
- else if (funct7[6:2] == 5'b00011) name = "FDIV";
- else if (funct7[6:2] == 5'b01011) name = "FSQRT";
- else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
- else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
- else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
- else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
- else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
- else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
- else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
- else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
- else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
- else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
- else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
- else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
- else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
- else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
- else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
- else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
- else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
- else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
- else if (funct7[6:2] == 5'b00100) name = "FSGNJX";
- else if (funct7[6:2] == 5'b10100) name = "FEQ";
- else name = "ILLEGAL";
- 10'b1010011_???: if (funct7[6:2] == 5'b00000) name = "FADD";
- else if (funct7[6:2] == 5'b00001) name = "FSUB";
- else if (funct7[6:2] == 5'b00010) name = "FMUL";
- else if (funct7[6:2] == 5'b00011) name = "FDIV";
- else if (funct7[6:2] == 5'b01011) name = "FSQRT";
- else if (funct7 == 7'b1100000 && rs2 == 5'b00000) name = "FCVT.W.S";
- else if (funct7 == 7'b1100000 && rs2 == 5'b00001) name = "FCVT.WU.S";
- else if (funct7 == 7'b1100000 && rs2 == 5'b00010) name = "FCVT.L.S";
- else if (funct7 == 7'b1100000 && rs2 == 5'b00011) name = "FCVT.LU.S";
- else if (funct7 == 7'b1101000 && rs2 == 5'b00000) name = "FCVT.S.W";
- else if (funct7 == 7'b1101000 && rs2 == 5'b00001) name = "FCVT.S.WU";
- else if (funct7 == 7'b1101000 && rs2 == 5'b00010) name = "FCVT.S.L";
- else if (funct7 == 7'b1101000 && rs2 == 5'b00011) name = "FCVT.S.LU";
- else if (funct7 == 7'b1100001 && rs2 == 5'b00000) name = "FCVT.W.D";
- else if (funct7 == 7'b1100001 && rs2 == 5'b00001) name = "FCVT.WU.D";
- else if (funct7 == 7'b1100001 && rs2 == 5'b00010) name = "FCVT.L.D";
- else if (funct7 == 7'b1100001 && rs2 == 5'b00011) name = "FCVT.LU.D";
- else if (funct7 == 7'b1101001 && rs2 == 5'b00000) name = "FCVT.D.W";
- else if (funct7 == 7'b1101001 && rs2 == 5'b00001) name = "FCVT.D.WU";
- else if (funct7 == 7'b1101001 && rs2 == 5'b00010) name = "FCVT.D.L";
- else if (funct7 == 7'b1101001 && rs2 == 5'b00011) name = "FCVT.D.LU";
- else if (funct7 == 7'b0100000 && rs2 == 5'b00001) name = "FCVT.S.D";
- else if (funct7 == 7'b0100001 && rs2 == 5'b00000) name = "FCVT.D.S";
- else name = "ILLEGAL";
- 10'b0000111_010: name = "FLW";
- 10'b0100111_010: name = "FSW";
- 10'b0000111_011: name = "FLD";
- 10'b0100111_011: name = "FSD";
- default: name = "ILLEGAL";
- endcase
-endmodule
-
-module logging(
- input logic clk, reset,
- input logic [31:0] HADDR,
- input logic [1:0] HTRANS);
-
- always @(posedge clk)
- if (HTRANS != 2'b00 && HADDR == 0)
- $display("%t Warning: access to memory address 0\n", $realtime);
-endmodule
-
-
module DCacheFlushFSM
(input logic clk,
input logic reset,
@@ -1108,11 +817,6 @@ module DCacheFlushFSM
end
endgenerate
-/* -----\/----- EXCLUDED -----\/-----
- .Adr(((testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.CacheTagMem.StoredData[index] << tagstart)
- + (index << logblockbytelen) + (cacheWord << $clog2(`XLEN/8)))),
- -----/\----- EXCLUDED -----/\----- */
-
integer i, j, k;
always @(posedge clk) begin
diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
index e3bf013a2..051c625a9 100644
--- a/wally-pipelined/testbench/testbench-linux.sv
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -1024,134 +1024,3 @@ module testbench();
endfunction
endmodule
-//module logging(
-// input logic clk, reset,
-// input logic [31:0] dut.hart.lsu.dcache.MemPAdrM,
-// input logic [1:0] (|dut.hart.lsu.dcache.MemRWM || dut.hart.lsu.dcache.AtomicM));
-//
-// always @(posedge clk)
-// if ((|dut.hart.lsu.dcache.MemRWM || dut.hart.lsu.dcache.AtomicM) != 2'b00 && dut.hart.lsu.dcache.MemPAdrM == 0)
-// $display("Warning: access to memory address 0\n");
-//endmodule
-
-
-module instrTrackerTB(
- input logic clk, reset,
- input logic [31:0] InstrF,InstrD,InstrE,InstrM,InstrW,
- output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
- instrNameDecTB fdec(InstrF, InstrFName);
- instrNameDecTB ddec(InstrD, InstrDName);
- instrNameDecTB edec(InstrE, InstrEName);
- instrNameDecTB mdec(InstrM, InstrMName);
- instrNameDecTB wdec(InstrW, InstrWName);
-endmodule
-
-// decode the instruction name, to help the test bench
-module instrNameDecTB(
- input logic [31:0] instr,
- output string name);
-
- logic [6:0] op;
- logic [2:0] funct3;
- logic [6:0] funct7;
- logic [11:0] imm;
-
- assign op = instr[6:0];
- assign funct3 = instr[14:12];
- assign funct7 = instr[31:25];
- assign imm = instr[31:20];
-
- // it would be nice to add the operands to the name
- // create another variable called decoded
-
- always_comb
- casez({op, funct3})
- 10'b0000000_000: name = "BAD";
- 10'b0000011_000: name = "LB";
- 10'b0000011_001: name = "LH";
- 10'b0000011_010: name = "LW";
- 10'b0000011_011: name = "LD";
- 10'b0000011_100: name = "LBU";
- 10'b0000011_101: name = "LHU";
- 10'b0000011_110: name = "LWU";
- 10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH";
- else name = "ADDI";
- 10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
- else name = "ILLEGAL";
- 10'b0010011_010: name = "SLTI";
- 10'b0010011_011: name = "SLTIU";
- 10'b0010011_100: name = "XORI";
- 10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI";
- else if (funct7[6:1] == 6'b010000) name = "SRAI";
- else name = "ILLEGAL";
- 10'b0010011_110: name = "ORI";
- 10'b0010011_111: name = "ANDI";
- 10'b0010111_???: name = "AUIPC";
- 10'b0100011_000: name = "SB";
- 10'b0100011_001: name = "SH";
- 10'b0100011_010: name = "SW";
- 10'b0100011_011: name = "SD";
- 10'b0011011_000: name = "ADDIW";
- 10'b0011011_001: name = "SLLIW";
- 10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW";
- else if (funct7 == 7'b0100000) name = "SRAIW";
- else name = "ILLEGAL";
- 10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW";
- else if (funct7 == 7'b0100000) name = "SUBW";
- else name = "ILLEGAL";
- 10'b0111011_001: name = "SLLW";
- 10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW";
- else if (funct7 == 7'b0100000) name = "SRAW";
- else name = "ILLEGAL";
- 10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
- else if (funct7 == 7'b0000001) name = "MUL";
- else if (funct7 == 7'b0100000) name = "SUB";
- else name = "ILLEGAL";
- 10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL";
- else if (funct7 == 7'b0000001) name = "MULH";
- else name = "ILLEGAL";
- 10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT";
- else if (funct7 == 7'b0000001) name = "MULHSU";
- else name = "ILLEGAL";
- 10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU";
- else if (funct7 == 7'b0000001) name = "DIV";
- else name = "ILLEGAL";
- 10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR";
- else if (funct7 == 7'b0000001) name = "MUL";
- else name = "ILLEGAL";
- 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
- else if (funct7 == 7'b0000001) name = "DIVU";
- else if (funct7 == 7'b0100000) name = "SRA";
- else name = "ILLEGAL";
- 10'b0110011_110: if (funct7 == 7'b0000000) name = "OR";
- else if (funct7 == 7'b0000001) name = "REM";
- else name = "ILLEGAL";
- 10'b0110011_111: if (funct7 == 7'b0000000) name = "AND";
- else if (funct7 == 7'b0000001) name = "REMU";
- else name = "ILLEGAL";
- 10'b0110111_???: name = "LUI";
- 10'b1100011_000: name = "BEQ";
- 10'b1100011_001: name = "BNE";
- 10'b1100011_100: name = "BLT";
- 10'b1100011_101: name = "BGE";
- 10'b1100011_110: name = "BLTU";
- 10'b1100011_111: name = "BGEU";
- 10'b1100111_000: name = "JALR";
- 10'b1101111_???: name = "JAL";
- 10'b1110011_000: if (imm == 0) name = "ECALL";
- else if (imm == 1) name = "EBREAK";
- else if (imm == 2) name = "URET";
- else if (imm == 258) name = "SRET";
- else if (imm == 770) name = "MRET";
- else name = "ILLEGAL";
- 10'b1110011_001: name = "CSRRW";
- 10'b1110011_010: name = "CSRRS";
- 10'b1110011_011: name = "CSRRC";
- 10'b1110011_101: name = "CSRRWI";
- 10'b1110011_110: name = "CSRRSI";
- 10'b1110011_111: name = "CSRRCI";
- 10'b0001111_???: name = "FENCE";
- default: name = "ILLEGAL";
- endcase
-endmodule
-
diff --git a/wally-pipelined/testbench/testbench-privileged.sv b/wally-pipelined/testbench/testbench-privileged.sv
index c8ba0abea..335223b26 100644
--- a/wally-pipelined/testbench/testbench-privileged.sv
+++ b/wally-pipelined/testbench/testbench-privileged.sv
@@ -217,162 +217,3 @@ endmodule
/* verilator lint_on STMTDLY */
/* verilator lint_on WIDTH */
-module instrTrackerTBPriv(
- input logic clk, reset, FlushE,
- input logic [31:0] InstrF, InstrD,
- input logic [31:0] InstrE, InstrM,
- input logic [31:0] InstrW,
-// output logic [31:0] InstrW,
- output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
-
- // stage Instr to Writeback for visualization
- //flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
-
-
- instrNameDecTB fdec(InstrF, InstrFName);
- instrNameDecTB ddec(InstrD, InstrDName);
- instrNameDecTB edec(InstrE, InstrEName);
- instrNameDecTB mdec(InstrM, InstrMName);
- instrNameDecTB wdec(InstrW, InstrWName);
-endmodule
-
-// decode the instruction name, to help the test bench
-module instrNameDecTB(
- input logic [31:0] instr,
- output string name);
-
- logic [6:0] op;
- logic [2:0] funct3;
- logic [6:0] funct7;
- logic [11:0] imm;
-
- assign op = instr[6:0];
- assign funct3 = instr[14:12];
- assign funct7 = instr[31:25];
- assign imm = instr[31:20];
-
- // it would be nice to add the operands to the name
- // create another variable called decoded
-
- always_comb
- casez({op, funct3})
- 10'b0000000_000: name = "BAD";
- 10'b0000011_000: name = "LB";
- 10'b0000011_001: name = "LH";
- 10'b0000011_010: name = "LW";
- 10'b0000011_011: name = "LD";
- 10'b0000011_100: name = "LBU";
- 10'b0000011_101: name = "LHU";
- 10'b0000011_110: name = "LWU";
- 10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH";
- else name = "ADDI";
- 10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
- else name = "ILLEGAL";
- 10'b0010011_010: name = "SLTI";
- 10'b0010011_011: name = "SLTIU";
- 10'b0010011_100: name = "XORI";
- 10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI";
- else if (funct7[6:1] == 6'b010000) name = "SRAI";
- else name = "ILLEGAL";
- 10'b0010011_110: name = "ORI";
- 10'b0010011_111: name = "ANDI";
- 10'b0010111_???: name = "AUIPC";
- 10'b0100011_000: name = "SB";
- 10'b0100011_001: name = "SH";
- 10'b0100011_010: name = "SW";
- 10'b0100011_011: name = "SD";
- 10'b0011011_000: name = "ADDIW";
- 10'b0011011_001: name = "SLLIW";
- 10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW";
- else if (funct7 == 7'b0100000) name = "SRAIW";
- else name = "ILLEGAL";
- 10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW";
- else if (funct7 == 7'b0100000) name = "SUBW";
- else if (funct7 == 7'b0000001) name = "MULW";
- else name = "ILLEGAL";
- 10'b0111011_001: if (funct7 == 7'b0000000) name = "SLLW";
- else if (funct7 == 7'b0000001) name = "DIVW";
- else name = "ILLEGAL";
- 10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW";
- else if (funct7 == 7'b0100000) name = "SRAW";
- else if (funct7 == 7'b0000001) name = "DIVUW";
- else name = "ILLEGAL";
- 10'b0111011_110: if (funct7 == 7'b0000001) name = "REMW";
- else name = "ILLEGAL";
- 10'b0111011_111: if (funct7 == 7'b0000001) name = "REMUW";
- else name = "ILLEGAL";
- 10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
- else if (funct7 == 7'b0000001) name = "MUL";
- else if (funct7 == 7'b0100000) name = "SUB";
- else name = "ILLEGAL";
- 10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL";
- else if (funct7 == 7'b0000001) name = "MULH";
- else name = "ILLEGAL";
- 10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT";
- else if (funct7 == 7'b0000001) name = "MULHSU";
- else name = "ILLEGAL";
- 10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU";
- else if (funct7 == 7'b0000001) name = "MULHU";
- else name = "ILLEGAL";
- 10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR";
- else if (funct7 == 7'b0000001) name = "DIV";
- else name = "ILLEGAL";
- 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
- else if (funct7 == 7'b0000001) name = "DIVU";
- else if (funct7 == 7'b0100000) name = "SRA";
- else name = "ILLEGAL";
- 10'b0110011_110: if (funct7 == 7'b0000000) name = "OR";
- else if (funct7 == 7'b0000001) name = "REM";
- else name = "ILLEGAL";
- 10'b0110011_111: if (funct7 == 7'b0000000) name = "AND";
- else if (funct7 == 7'b0000001) name = "REMU";
- else name = "ILLEGAL";
- 10'b0110111_???: name = "LUI";
- 10'b1100011_000: name = "BEQ";
- 10'b1100011_001: name = "BNE";
- 10'b1100011_100: name = "BLT";
- 10'b1100011_101: name = "BGE";
- 10'b1100011_110: name = "BLTU";
- 10'b1100011_111: name = "BGEU";
- 10'b1100111_000: name = "JALR";
- 10'b1101111_???: name = "JAL";
- 10'b1110011_000: if (imm == 0) name = "ECALL";
- else if (imm == 1) name = "EBREAK";
- else if (imm == 2) name = "URET";
- else if (imm == 258) name = "SRET";
- else if (imm == 770) name = "MRET";
- else name = "ILLEGAL";
- 10'b1110011_001: name = "CSRRW";
- 10'b1110011_010: name = "CSRRS";
- 10'b1110011_011: name = "CSRRC";
- 10'b1110011_101: name = "CSRRWI";
- 10'b1110011_110: name = "CSRRSI";
- 10'b1110011_111: name = "CSRRCI";
- 10'b0101111_010: if (funct7[6:2] == 5'b00010) name = "LR.W";
- else if (funct7[6:2] == 5'b00011) name = "SC.W";
- else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.W";
- else if (funct7[6:2] == 5'b00000) name = "AMOADD.W";
- else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.W";
- else if (funct7[6:2] == 5'b01100) name = "AMOAND.W";
- else if (funct7[6:2] == 5'b01000) name = "AMOOR.W";
- else if (funct7[6:2] == 5'b10000) name = "AMOMIN.W";
- else if (funct7[6:2] == 5'b10100) name = "AMOMAX.W";
- else if (funct7[6:2] == 5'b11000) name = "AMOMINU.W";
- else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.W";
- else name = "ILLEGAL";
- 10'b0101111_011: if (funct7[6:2] == 5'b00010) name = "LR.D";
- else if (funct7[6:2] == 5'b00011) name = "SC.D";
- else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.D";
- else if (funct7[6:2] == 5'b00000) name = "AMOADD.D";
- else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.D";
- else if (funct7[6:2] == 5'b01100) name = "AMOAND.D";
- else if (funct7[6:2] == 5'b01000) name = "AMOOR.D";
- else if (funct7[6:2] == 5'b10000) name = "AMOMIN.D";
- else if (funct7[6:2] == 5'b10100) name = "AMOMAX.D";
- else if (funct7[6:2] == 5'b11000) name = "AMOMINU.D";
- else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D";
- else name = "ILLEGAL";
- 10'b0001111_???: name = "FENCE";
- default: name = "ILLEGAL";
- endcase
-endmodule