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Prepare to squash bad ahb accesses

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This commit is contained in:
Thomas Fleming 2021-04-22 15:36:45 -04:00
parent c055ab272d
commit 74fb1dccad
1 changed files with 7 additions and 1 deletions
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8
wally-pipelined/src/ebu/ahblite.sv
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@ -31,7 +31,7 @@
`include "wally-config.vh" `include "wally-config.vh"
package ahbliteState; package ahbliteState;
typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADC, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE, MMUIDLE} statetype; typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADC, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE} statetype;
endpackage endpackage
module ahblite ( module ahblite (
@ -56,6 +56,8 @@ module ahblite (
input logic MMUTranslate, MMUTranslationComplete, input logic MMUTranslate, MMUTranslationComplete,
output logic [`XLEN-1:0] MMUReadPTE, output logic [`XLEN-1:0] MMUReadPTE,
output logic MMUReady, output logic MMUReady,
// Signals from PMA checker
input logic SquashAHBAccess,
// Return from bus // Return from bus
output logic [`XLEN-1:0] ReadDataW, output logic [`XLEN-1:0] ReadDataW,
// AHB-Lite external signals // AHB-Lite external signals
@ -103,6 +105,10 @@ module ahblite (
flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState); flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState);
// *** If the SquashAHBAccess signal is high, we need to set NextBusState to IDLE.
// We could either have this case statement set a signal ProposedNextBusState, which gets
// used for NextBusState when we are not squashing. Alternatively, we could add a bunch of
// conditional statments below
always_comb always_comb
case (BusState) case (BusState)
IDLE: if (MMUTranslate) NextBusState = MMUTRANSLATE; IDLE: if (MMUTranslate) NextBusState = MMUTRANSLATE;