diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index 36cda4d91..e88b012aa 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -39,12 +39,12 @@ // MISA RISC-V configuration per specification //16 - quad 3 - double 5 - single -`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) +`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 0 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 `define ZICOUNTERS_SUPPORTED 1 -`define ZFH_SUPPORTED 1 +`define ZFH_SUPPORTED 0 /// Microarchitectural Features `define UARCH_PIPELINED 1 diff --git a/pipelined/src/fpu/fclassify.sv b/pipelined/src/fpu/fclassify.sv index 05a91d212..a1a934ffe 100644 --- a/pipelined/src/fpu/fclassify.sv +++ b/pipelined/src/fpu/fclassify.sv @@ -8,7 +8,7 @@ module fclassify ( input logic XDenormE, // is denormal input logic XZeroE, // is zero input logic XInfE, // is infinity - output logic [63:0] ClassResE // classify result + output logic [`XLEN-1:0] ClassResE // classify result ); logic PInf, PZero, PNorm, PDenorm; @@ -37,6 +37,6 @@ module fclassify ( // bit 7 - +Inf // bit 8 - signaling NaN // bit 9 - quiet NaN - assign ClassResE = {{54{1'b0}}, XNaNE&~XSNaNE, XSNaNE, PInf, PNorm, PDenorm, PZero, NZero, NDenorm, NNorm, NInf}; + assign ClassResE = {{`XLEN-10{1'b0}}, XNaNE&~XSNaNE, XSNaNE, PInf, PNorm, PDenorm, PZero, NZero, NDenorm, NNorm, NInf}; endmodule diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv index 0640a544e..690f9f940 100755 --- a/pipelined/src/fpu/fctrl.sv +++ b/pipelined/src/fpu/fctrl.sv @@ -1,3 +1,4 @@ +`include "wally-config.vh" module fctrl ( input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision @@ -13,7 +14,7 @@ module fctrl ( output logic [2:0] FOpCtrlD, // chooses which opperation to do - specifics shown at bottom of module and in each unit output logic [1:0] FResSelD, // select one of the results done in the memory stage output logic [1:0] FIntResSelD, // select the result that will be written to the integer register - output logic FmtD, // precision - single-0 double-1 + output logic [`FPSIZES/3:0] FmtD, // precision - single-0 double-1 output logic [2:0] FrmD, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude output logic FWriteIntD // is the result written to the integer register ); @@ -119,8 +120,23 @@ module fctrl ( // Precision // 0-single // 1-double - assign FmtD = FResultSelD == 2'b00 ? Funct3D[0] : ((Funct7D[6:3] == 4'b0100)&OpD[4]) | OpD[6:1] == 6'b010000 ? ~Funct7D[0] : Funct7D[0]; + + if (`FPSIZES == 1)begin + logic [1:0] FmtTmp; + assign FmtTmp = (FResultSelD == 2'b00) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0]; + assign FmtD = `FMT == FmtTmp; +end + //assign FmtD = 0; *** change back after full paramerterization + else if (`FPSIZES == 2)begin + logic [1:0] FmtTmp; + assign FmtTmp = (FResultSelD == 2'b00) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0]; + assign FmtD = `FMT == FmtTmp; + end + else if (`FPSIZES == 3|`FPSIZES == 4) + assign FmtD = (FResultSelD == 2'b00) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0]; + + // assign FmtD = FResultSelD == 2'b00 ? Funct3D[0] : ((Funct7D[6:3] == 4'b0100)&OpD[4]) | OpD[6:1] == 6'b010000 ? ~Funct7D[0] : Funct7D[0]; // FResultSel: // 000 - ReadRes - load // 001 - FMARes - FMA and multiply diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 113403c95..0fa125b80 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -115,7 +115,7 @@ module fpu ( logic [63:0] CvtResE; // FP <-> int convert result logic [`XLEN-1:0] CvtIntResE; // FP <-> int convert result logic [4:0] CvtFlgE; // FP <-> int convert flags //*** trim this - logic [63:0] ClassResE; // classify result + logic [`XLEN-1:0] ClassResE; // classify result logic [63:0] CmpResE; // compare result logic CmpNVE; // compare invalid flag (Not Valid) logic [63:0] SgnResE; // sign injection result @@ -231,7 +231,7 @@ module fpu ( mux4 #(5) FFlgMux(5'b0, 5'b0, {CmpNVE, 4'b0}, CvtFlgE, FResSelE, FFlgE); // select the result that may be written to the integer register - to IEU - mux4 #(`XLEN) IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE[`XLEN-1:0], + mux4 #(`XLEN) IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE, CvtIntResE, FIntResSelE, FIntResE); // *** DH 5/25/22: CvtRes will move to mem stage. Premux in execute to save area, then make sure stalls are ok // *** make sure the fpu matches the chapter diagram diff --git a/pipelined/src/fpu/fregfile.sv b/pipelined/src/fpu/fregfile.sv index 2d54038de..00c89ff56 100644 --- a/pipelined/src/fpu/fregfile.sv +++ b/pipelined/src/fpu/fregfile.sv @@ -33,10 +33,10 @@ module fregfile ( input logic clk, reset, input logic we4, input logic [4:0] a1, a2, a3, a4, - input logic [63:0] wd4, - output logic [63:0] rd1, rd2, rd3); + input logic [`FLEN-1:0] wd4, + output logic [`FLEN-1:0] rd1, rd2, rd3); - logic [63:0] rf[31:0]; + logic [`FLEN-1:0] rf[31:0]; integer i; // three ported register file diff --git a/pipelined/src/fpu/fsgninj.sv b/pipelined/src/fpu/fsgninj.sv index 8474fdff6..00c1372c2 100755 --- a/pipelined/src/fpu/fsgninj.sv +++ b/pipelined/src/fpu/fsgninj.sv @@ -26,13 +26,14 @@ // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE // OR OTHER DEALINGS IN THE SOFTWARE. //////////////////////////////////////////////////////////////////////////////////////////////// +`include "wally-config.vh" module fsgninj ( input logic XSgnE, YSgnE, // X and Y sign bits - input logic [63:0] FSrcXE, // X - input logic FmtE, // precision 1 = double 0 = single + input logic [`FLEN-1:0] FSrcXE, // X + input logic [`FPSIZES/3:0] FmtE, // precision 1 = double 0 = single input logic [1:0] SgnOpCodeE, // operation control - output logic [63:0] SgnResE // result + output logic [`FLEN-1:0] SgnResE // result ); logic ResSgn; @@ -50,7 +51,30 @@ module fsgninj ( // format final result based on precision // - uses NaN-blocking format // - if there are any unsused bits the most significant bits are filled with 1s - assign SgnResE = FmtE ? {ResSgn, FSrcXE[62:0]} : {FSrcXE[63:32], ResSgn, FSrcXE[30:0]}; + + if (`FPSIZES == 1) + assign SgnResE = {ResSgn, FSrcXE[`FLEN-2:0]}; + + else if (`FPSIZES == 2) + assign SgnResE = FmtE ? {ResSgn, FSrcXE[`FLEN-2:0]} : {{`FLEN-`LEN1{1'b1}}, ResSgn, FSrcXE[`LEN1-2:0]}; + + else if (`FPSIZES == 3) + always_comb + case (FmtE) + `FMT: SgnResE = {ResSgn, FSrcXE[`FLEN-2:0]}; + `FMT1: SgnResE = {{`FLEN-`LEN1{1'b1}}, ResSgn, FSrcXE[`LEN1-2:0]}; + `FMT2: SgnResE = {{`FLEN-`LEN2{1'b1}}, ResSgn, FSrcXE[`LEN2-2:0]}; + default: SgnResE = 0; + endcase + + else if (`FPSIZES == 4) + always_comb + case (FmtE) + 2'h3: SgnResE = {ResSgn, FSrcXE[`Q_LEN-2:0]}; + 2'h1: SgnResE = {{`Q_LEN-`D_LEN{1'b1}}, ResSgn, FSrcXE[`D_LEN-2:0]}; + 2'h0: SgnResE = {{`Q_LEN-`S_LEN{1'b1}}, ResSgn, FSrcXE[`S_LEN-2:0]}; + 2'h2: SgnResE = {{`Q_LEN-`H_LEN{1'b1}}, ResSgn, FSrcXE[`H_LEN-2:0]}; + endcase endmodule diff --git a/pipelined/src/generic/lzc.sv b/pipelined/src/generic/lzc.sv index 1ce082475..123edcb6e 100644 --- a/pipelined/src/generic/lzc.sv +++ b/pipelined/src/generic/lzc.sv @@ -1,5 +1,5 @@ //leading zero counter i.e. priority encoder -module lzc #(parameter WIDTH=1) ( +module lzc #(parameter WIDTH = 1) ( input logic [WIDTH-1:0] num, output logic [$clog2(WIDTH+1)-1:0] ZeroCnt ); diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index fb796b796..3d7d9825c 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -325,21 +325,15 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets - set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_fpu_timing.rep"] redirect -append $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical paths through fma1 ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/fma1/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical paths through fma2 ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/fma2/*} -nworst 1 } redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fdivsqrt/*} -nworst 1 } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fdivsqrt/*} -nworst 1 } redirect -append $filename { echo "\n\n\n//// Critical paths through faddcvt ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through FMAResM ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FMAResM} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through FDivResM ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FDivResM} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through FResE ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FResE} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through fma/SumE ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/SumE} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through fma/ProdExpE ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/ProdExpE} -nworst 1 } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {faddcvt/*} -nworst 1 } set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_mmu_timing.rep"] redirect -append $filename { echo "\n\n\n//// Critical paths through immu/physicaladdress ////\n\n\n" }