From 8d8d2aabc25a3e1fac9f4509f9a3470f210f85bc Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Tue, 15 Jun 2021 19:24:24 -0400
Subject: [PATCH 1/3] fixed incorrect expectation fof CLINT spec
---
wally-pipelined/testgen/privileged/testgen-CAUSE.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/wally-pipelined/testgen/privileged/testgen-CAUSE.py b/wally-pipelined/testgen/privileged/testgen-CAUSE.py
index 0bca336cf..2df328927 100644
--- a/wally-pipelined/testgen/privileged/testgen-CAUSE.py
+++ b/wally-pipelined/testgen/privileged/testgen-CAUSE.py
@@ -69,7 +69,8 @@ def writeVectors(storecmd, returningInstruction):
csrrc x0, {fromMode}status, x1
la x18, {clintAddr}
- {storecmd} x0, 0(x18)
+ li x1, -1
+ {storecmd} x1, 0(x18)
""")
# Page 6 of unpriviledged spec
From d1bab12e1e7ed21e747915fe83a6c89317154551 Mon Sep 17 00:00:00 2001
From: bracker <bbracker@hmc.edu>
Date: Wed, 16 Jun 2021 10:28:57 -0500
Subject: [PATCH 2/3] chmod +x'd privileged testgen scripts
---
wally-pipelined/testgen/privileged/run.sh | 0
wally-pipelined/testgen/privileged/testgen-CAUSE.py | 0
wally-pipelined/testgen/privileged/testgen-CSR-PERMISSIONS.py | 0
wally-pipelined/testgen/privileged/testgen-DELEG.py | 0
wally-pipelined/testgen/privileged/testgen-EPC.py | 0
wally-pipelined/testgen/privileged/testgen-IE.py | 0
wally-pipelined/testgen/privileged/testgen-IP.py | 0
wally-pipelined/testgen/privileged/testgen-READONLY.py | 0
wally-pipelined/testgen/privileged/testgen-RET.py | 0
wally-pipelined/testgen/privileged/testgen-TVAL.py | 0
wally-pipelined/testgen/privileged/testgen-TVEC.py | 0
11 files changed, 0 insertions(+), 0 deletions(-)
mode change 100644 => 100755 wally-pipelined/testgen/privileged/run.sh
mode change 100644 => 100755 wally-pipelined/testgen/privileged/testgen-CAUSE.py
mode change 100644 => 100755 wally-pipelined/testgen/privileged/testgen-CSR-PERMISSIONS.py
mode change 100644 => 100755 wally-pipelined/testgen/privileged/testgen-DELEG.py
mode change 100644 => 100755 wally-pipelined/testgen/privileged/testgen-EPC.py
mode change 100644 => 100755 wally-pipelined/testgen/privileged/testgen-IE.py
mode change 100644 => 100755 wally-pipelined/testgen/privileged/testgen-IP.py
mode change 100644 => 100755 wally-pipelined/testgen/privileged/testgen-READONLY.py
mode change 100644 => 100755 wally-pipelined/testgen/privileged/testgen-RET.py
mode change 100644 => 100755 wally-pipelined/testgen/privileged/testgen-TVAL.py
mode change 100644 => 100755 wally-pipelined/testgen/privileged/testgen-TVEC.py
diff --git a/wally-pipelined/testgen/privileged/run.sh b/wally-pipelined/testgen/privileged/run.sh
old mode 100644
new mode 100755
diff --git a/wally-pipelined/testgen/privileged/testgen-CAUSE.py b/wally-pipelined/testgen/privileged/testgen-CAUSE.py
old mode 100644
new mode 100755
diff --git a/wally-pipelined/testgen/privileged/testgen-CSR-PERMISSIONS.py b/wally-pipelined/testgen/privileged/testgen-CSR-PERMISSIONS.py
old mode 100644
new mode 100755
diff --git a/wally-pipelined/testgen/privileged/testgen-DELEG.py b/wally-pipelined/testgen/privileged/testgen-DELEG.py
old mode 100644
new mode 100755
diff --git a/wally-pipelined/testgen/privileged/testgen-EPC.py b/wally-pipelined/testgen/privileged/testgen-EPC.py
old mode 100644
new mode 100755
diff --git a/wally-pipelined/testgen/privileged/testgen-IE.py b/wally-pipelined/testgen/privileged/testgen-IE.py
old mode 100644
new mode 100755
diff --git a/wally-pipelined/testgen/privileged/testgen-IP.py b/wally-pipelined/testgen/privileged/testgen-IP.py
old mode 100644
new mode 100755
diff --git a/wally-pipelined/testgen/privileged/testgen-READONLY.py b/wally-pipelined/testgen/privileged/testgen-READONLY.py
old mode 100644
new mode 100755
diff --git a/wally-pipelined/testgen/privileged/testgen-RET.py b/wally-pipelined/testgen/privileged/testgen-RET.py
old mode 100644
new mode 100755
diff --git a/wally-pipelined/testgen/privileged/testgen-TVAL.py b/wally-pipelined/testgen/privileged/testgen-TVAL.py
old mode 100644
new mode 100755
diff --git a/wally-pipelined/testgen/privileged/testgen-TVEC.py b/wally-pipelined/testgen/privileged/testgen-TVEC.py
old mode 100644
new mode 100755
From 7a652139b5d1a68c0a17aa1656828401c3013177 Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Wed, 16 Jun 2021 17:37:08 -0400
Subject: [PATCH 3/3] mcause test fixes and s-mode interrupt bugfix
---
wally-pipelined/src/privileged/csr.sv | 3 +--
wally-pipelined/src/privileged/privileged.sv | 2 +-
wally-pipelined/src/privileged/trap.sv | 4 ++--
wally-pipelined/src/uncore/clint.sv | 20 +++++++++----------
.../testgen/privileged/testgen-CAUSE.py | 4 +++-
5 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv
index fa1f49814..a42e29376 100644
--- a/wally-pipelined/src/privileged/csr.sv
+++ b/wally-pipelined/src/privileged/csr.sv
@@ -55,7 +55,7 @@ module csr #(parameter
output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW,
output logic [`XLEN-1:0] SATP_REGW,
- output logic [11:0] MIP_REGW, MIE_REGW,
+ output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
output logic STATUS_MIE, STATUS_SIE,
output logic STATUS_MXR, STATUS_SUM,
output logic STATUS_MPRV,
@@ -80,7 +80,6 @@ module csr #(parameter
logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM;
logic [11:0] CSRAdrM;
- logic [11:0] SIP_REGW, SIE_REGW;
//logic [11:0] UIP_REGW, UIE_REGW = 0; // N user-mode exceptions not supported
logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, IllegalCSRNAccessM, InsufficientCSRPrivilegeM;
logic IllegalCSRMWriteReadonlyM;
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index 1b85d151a..4f4ecd70f 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -96,7 +96,7 @@ module privileged (
logic [1:0] STATUS_MPP;
logic STATUS_SPP, STATUS_TSR, STATUS_MPRV; // **** status mprv is unused outside of the csr module as of 4 June 2021. should it be deleted alltogether from the module, or should I leav the pin here in case someone needs it?
logic STATUS_MIE, STATUS_SIE;
- logic [11:0] MIP_REGW, MIE_REGW;
+ logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW;
logic md, sd;
diff --git a/wally-pipelined/src/privileged/trap.sv b/wally-pipelined/src/privileged/trap.sv
index 93475b9d3..af4f17305 100644
--- a/wally-pipelined/src/privileged/trap.sv
+++ b/wally-pipelined/src/privileged/trap.sv
@@ -35,7 +35,7 @@ module trap (
input logic mretM, sretM, uretM,
input logic [1:0] PrivilegeModeW, NextPrivilegeModeM,
input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
- input logic [11:0] MIP_REGW, MIE_REGW,
+ input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
input logic STATUS_MIE, STATUS_SIE,
input logic [`XLEN-1:0] PCM,
input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
@@ -58,7 +58,7 @@ module trap (
// Determine pending enabled interrupts
assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || STATUS_SIE; // if S ints enabled or lower priv 3.1.9
- assign PendingIntsM = (MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888) | ({12{SIntGlobalEnM}} & 12'h222);
+ assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
assign InterruptM = (|PendingIntsM) & InstrValidM & ~CommittedM;
// interrupt if any sources are pending
// & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
diff --git a/wally-pipelined/src/uncore/clint.sv b/wally-pipelined/src/uncore/clint.sv
index e3b22a869..df4c1e8fa 100644
--- a/wally-pipelined/src/uncore/clint.sv
+++ b/wally-pipelined/src/uncore/clint.sv
@@ -27,22 +27,22 @@
`include "wally-config.vh"
module clint (
- input logic HCLK, HRESETn,
- input logic HSELCLINT,
- input logic [15:0] HADDR,
- input logic HWRITE,
- input logic [`XLEN-1:0] HWDATA,
- output logic [`XLEN-1:0] HREADCLINT,
- output logic HRESPCLINT, HREADYCLINT,
+ input logic HCLK, HRESETn,
+ input logic HSELCLINT,
+ input logic [15:0] HADDR,
+ input logic HWRITE,
+ input logic [`XLEN-1:0] HWDATA,
input logic HREADY,
- input logic [1:0] HTRANS,
- output logic TimerIntM, SwIntM);
+ input logic [1:0] HTRANS,
+ output logic [`XLEN-1:0] HREADCLINT,
+ output logic HRESPCLINT, HREADYCLINT,
+ output logic TimerIntM, SwIntM);
logic [63:0] MTIMECMP, MTIME;
logic MSIP;
logic [15:0] entry, entryd;
- logic memread, memwrite;
+ logic memread, memwrite;
logic initTrans;
assign initTrans = HREADY & HSELCLINT & (HTRANS != 2'b00);
diff --git a/wally-pipelined/testgen/privileged/testgen-CAUSE.py b/wally-pipelined/testgen/privileged/testgen-CAUSE.py
index 2df328927..0ab0128b4 100755
--- a/wally-pipelined/testgen/privileged/testgen-CAUSE.py
+++ b/wally-pipelined/testgen/privileged/testgen-CAUSE.py
@@ -53,7 +53,7 @@ def writeVectors(storecmd, returningInstruction):
csrrs x0, {fromMode}status, x1
la x18, {clintAddr}
- lw x11, 0(x18)
+ {loadcmd} x11, 0(x18)
li x1, 0x3fffffffffffffff
{storecmd} x1, 0(x18)
@@ -310,9 +310,11 @@ for xlen in xlens:
formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
if (xlen == 32):
storecmd = "sw"
+ loadcmd = "lw"
wordsize = 4
else:
storecmd = "sd"
+ loadcmd = "ld"
wordsize = 8
# testMode can be m, s, and u. User mode traps are deprecated, so this should likely just be ["m", "s"]