mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/openhwgroup/cvw
This commit is contained in:
commit
74574f96cf
1
.gitignore
vendored
1
.gitignore
vendored
@ -82,6 +82,7 @@ synthDC/ppa/plots
|
|||||||
synthDC/wallyplots/
|
synthDC/wallyplots/
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||||||
synthDC/runArchive
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synthDC/runArchive
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||||||
synthDC/hdl
|
synthDC/hdl
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||||||
|
synthDC/wrappers
|
||||||
sim/power.saif
|
sim/power.saif
|
||||||
tests/fp/vectors/*.tv
|
tests/fp/vectors/*.tv
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||||||
synthDC/Summary.csv
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synthDC/Summary.csv
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||||||
|
@ -41,6 +41,16 @@ my @cr; my @cf; my @rt; my @ft;
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|||||||
# cell and corners to analyze
|
# cell and corners to analyze
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||||||
my $libpath; my $libbase; my $cellname; my @corners;
|
my $libpath; my $libbase; my $cellname; my @corners;
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||||||
|
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||||||
|
# Sky130
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||||||
|
$libpath ="/opt/riscv/cad/lib/sky130_osu_sc_t12/12T_ms/lib";
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||||||
|
$libbase = "sky130_osu_sc_12T_ms_";
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||||||
|
$cellname = "sky130_osu_sc_12T_ms__inv_1";
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||||||
|
@corners = ("TT_1P8_25C.ccs", "tt_1P80_25C.ccs", "tt_1P62_25C.ccs", "tt_1P89_25C.ccs", "ss_1P60_-40C.ccs", "ss_1P60_100C.ccs", "ss_1P60_150C.ccs", "ff_1P95_-40C.ccs", "ff_1P95_100C.ccs", "ff_1P95_150C.ccs");
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||||||
|
printf("Library $libbase Cell $cellname\n");
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|
foreach my $corner (@corners) {
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|
&analyzeCell($corner);
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|
}
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||||||
|
|
||||||
# Sky90
|
# Sky90
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||||||
$libpath ="/opt/riscv/cad/lib/sky90/sky90_sc/V1.7.4/lib";
|
$libpath ="/opt/riscv/cad/lib/sky90/sky90_sc/V1.7.4/lib";
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||||||
$libbase = "scc9gena_";
|
$libbase = "scc9gena_";
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||||||
@ -54,7 +64,7 @@ foreach my $corner (@corners) {
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# TSMC
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# TSMC
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||||||
$libpath = "/proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a";
|
$libpath = "/proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a";
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||||||
$libbase = "tcbn28hpcplusbwp30p140";
|
$libbase = "tcbn28hpcplusbwp30p140";
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||||||
$cellname = "INVD1..."; // replace this with the full name of the library cell
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$cellname = "INVD1..."; # replace this with the full name of the library cell
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||||||
@corners = ("tt0p9v25c", "tt0p8v25c", "tt1v25c", "tt0p9v85c", "ssg0p9vm40c", "ssg0p9v125c", "ssg0p81vm40c", "ssg0p81v125c", "ffg0p88vm40c", "ffg0p88v125c", "ffg0p99vm40c", "ffg0p99v125c");
|
@corners = ("tt0p9v25c", "tt0p8v25c", "tt1v25c", "tt0p9v85c", "ssg0p9vm40c", "ssg0p9v125c", "ssg0p81vm40c", "ssg0p81v125c", "ffg0p88vm40c", "ffg0p88v125c", "ffg0p99vm40c", "ffg0p99v125c");
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printf("\nLibrary $libbase Cell $cellname\n");
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printf("\nLibrary $libbase Cell $cellname\n");
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foreach my $corner (@corners) {
|
foreach my $corner (@corners) {
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@ -129,7 +139,7 @@ sub analyzeCell {
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my $delay = &computeDelay($cap);
|
my $delay = &computeDelay($cap);
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my $cornerr = sprintf("%20s", $corner);
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my $cornerr = sprintf("%20s", $corner);
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||||||
my $delayr = sprintf("%2.1f", $delay*1000);
|
my $delayr = sprintf("%2.1f", $delay*1000);
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||||||
my $leakager = sprintf("%3.1f", $leakage);
|
my $leakager = sprintf("%3.3f", $leakage);
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||||||
|
|
||||||
print("$cornerr: Delay $delayr Leakage: $leakager capacitance: $cap\n");
|
print("$cornerr: Delay $delayr Leakage: $leakager capacitance: $cap\n");
|
||||||
#print("$cellname $corner: Area $area Leakage: $leakage capacitance: $cap delay $delay\n");
|
#print("$cellname $corner: Area $area Leakage: $leakage capacitance: $cap delay $delay\n");
|
||||||
|
@ -167,3 +167,7 @@ sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
|
|||||||
sudo pip3 install testresources
|
sudo pip3 install testresources
|
||||||
pip3 install git+https://github.com/riscv/riscof.git
|
pip3 install git+https://github.com/riscv/riscof.git
|
||||||
|
|
||||||
|
# Download OSU Skywater 130 cell library
|
||||||
|
sudo mkdir -p $RISCV/cad/lib
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||||||
|
cd $RISCV/cad/lib
|
||||||
|
sudo git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12
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||||||
|
@ -36,7 +36,7 @@ localparam XLEN = 32'd32;
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|||||||
localparam IEEE754 = 0;
|
localparam IEEE754 = 0;
|
||||||
|
|
||||||
// I
|
// I
|
||||||
localparam MISA = (32'h00000104);
|
localparam MISA = (32'h00000100);
|
||||||
localparam ZICSR_SUPPORTED = 0;
|
localparam ZICSR_SUPPORTED = 0;
|
||||||
localparam ZIFENCEI_SUPPORTED = 0;
|
localparam ZIFENCEI_SUPPORTED = 0;
|
||||||
localparam COUNTERS = 0;
|
localparam COUNTERS = 0;
|
||||||
|
@ -36,7 +36,7 @@ localparam XLEN = 32'd64;
|
|||||||
localparam IEEE754 = 0;
|
localparam IEEE754 = 0;
|
||||||
|
|
||||||
// MISA RISC-V configuration per specification
|
// MISA RISC-V configuration per specification
|
||||||
localparam MISA = (32'h00000104);
|
localparam MISA = (32'h00000100);
|
||||||
localparam ZICSR_SUPPORTED = 0;
|
localparam ZICSR_SUPPORTED = 0;
|
||||||
localparam ZIFENCEI_SUPPORTED = 0;
|
localparam ZIFENCEI_SUPPORTED = 0;
|
||||||
localparam COUNTERS = 0;
|
localparam COUNTERS = 0;
|
||||||
|
@ -16,7 +16,7 @@ done
|
|||||||
echo "All lints run with no errors or warnings"
|
echo "All lints run with no errors or warnings"
|
||||||
|
|
||||||
# --lint-only just runs lint rather than trying to compile and simulate
|
# --lint-only just runs lint rather than trying to compile and simulate
|
||||||
# -I points to the include directory where files such as `include wally-config.vh are found
|
# -I points to the include directory where files such as `include config.vh are found
|
||||||
|
|
||||||
# For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command
|
# For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command
|
||||||
# Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.
|
# Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.
|
||||||
|
6
src/cache/cacheLRU.sv
vendored
6
src/cache/cacheLRU.sv
vendored
@ -70,8 +70,10 @@ module cacheLRU
|
|||||||
// coverage off
|
// coverage off
|
||||||
// Excluded from coverage b/c it is untestable without varying NUMWAYS.
|
// Excluded from coverage b/c it is untestable without varying NUMWAYS.
|
||||||
function integer log2 (integer value);
|
function integer log2 (integer value);
|
||||||
for (log2=0; value>0; log2=log2+1)
|
int val;
|
||||||
value = value>>1;
|
val = value;
|
||||||
|
for (log2 = 0; val > 0; log2 = log2+1)
|
||||||
|
val = val >> 1;
|
||||||
return log2;
|
return log2;
|
||||||
endfunction // log2
|
endfunction // log2
|
||||||
// coverage on
|
// coverage on
|
||||||
|
@ -88,7 +88,6 @@ module ahbapbbridge import cvw::*; #(parameter cvw_t P,
|
|||||||
int i;
|
int i;
|
||||||
always_comb begin
|
always_comb begin
|
||||||
// default: no peripheral selected: read 0, indicate ready during access phase so bus doesn't hang
|
// default: no peripheral selected: read 0, indicate ready during access phase so bus doesn't hang
|
||||||
// *** also could assert ready right away
|
|
||||||
HRDATA = 0;
|
HRDATA = 0;
|
||||||
PREADYOUT = 1'b1;
|
PREADYOUT = 1'b1;
|
||||||
for (i=0; i<PERIPHS; i++) begin
|
for (i=0; i<PERIPHS; i++) begin
|
||||||
|
@ -59,14 +59,9 @@ module gpio_apb import cvw::*; #(parameter cvw_t P) (
|
|||||||
|
|
||||||
// account for subword read/write circuitry
|
// account for subword read/write circuitry
|
||||||
// -- Note GPIO registers are 32 bits no matter what; access them with LW SW.
|
// -- Note GPIO registers are 32 bits no matter what; access them with LW SW.
|
||||||
// (At least that's what I think when FE310 spec says "only naturally aligned 32-bit accesses are supported")
|
assign Din = PWDATA[31:0];
|
||||||
if (P.XLEN == 64) begin
|
if (P.XLEN == 64) assign PRDATA = {Dout, Dout};
|
||||||
assign Din = entry[2] ? PWDATA[63:32] : PWDATA[31:0];
|
else assign PRDATA = Dout;
|
||||||
assign PRDATA = entry[2] ? {Dout,32'b0} : {32'b0,Dout};
|
|
||||||
end else begin // 32-bit
|
|
||||||
assign Din = PWDATA[31:0];
|
|
||||||
assign PRDATA = Dout;
|
|
||||||
end
|
|
||||||
|
|
||||||
// register access
|
// register access
|
||||||
always_ff @(posedge PCLK, negedge PRESETn)
|
always_ff @(posedge PCLK, negedge PRESETn)
|
||||||
|
@ -94,13 +94,9 @@ module plic_apb import cvw::*; #(parameter cvw_t P) (
|
|||||||
|
|
||||||
// account for subword read/write circuitry
|
// account for subword read/write circuitry
|
||||||
// -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
|
// -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
|
||||||
if (P.XLEN == 64) begin
|
assign Din = PWDATA[31:0];
|
||||||
assign Din = entry[2] ? PWDATA[63:32] : PWDATA[31:0];
|
if (P.XLEN == 64) assign PRDATA = {Dout, Dout};
|
||||||
assign PRDATA = entry[2] ? {Dout,32'b0} : {32'b0,Dout};
|
else assign PRDATA = Dout;
|
||||||
end else begin // 32-bit
|
|
||||||
assign PRDATA = Dout;
|
|
||||||
assign Din = PWDATA[31:0];
|
|
||||||
end
|
|
||||||
|
|
||||||
// ==================
|
// ==================
|
||||||
// Register Interface
|
// Register Interface
|
||||||
|
@ -54,31 +54,9 @@ module uart_apb import cvw::*; #(parameter cvw_t P) (
|
|||||||
assign MEMRb = ~memread;
|
assign MEMRb = ~memread;
|
||||||
assign MEMWb = ~memwrite;
|
assign MEMWb = ~memwrite;
|
||||||
|
|
||||||
if (P.XLEN == 64) begin:uart
|
assign Din = PWDATA[7:0];
|
||||||
always_comb begin
|
if (P.XLEN == 64) assign PRDATA = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
|
||||||
PRDATA = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
|
else assign PRDATA = {Dout, Dout, Dout, Dout};
|
||||||
case (entry)
|
|
||||||
3'b000: Din = PWDATA[7:0];
|
|
||||||
3'b001: Din = PWDATA[15:8];
|
|
||||||
3'b010: Din = PWDATA[23:16];
|
|
||||||
3'b011: Din = PWDATA[31:24];
|
|
||||||
3'b100: Din = PWDATA[39:32];
|
|
||||||
3'b101: Din = PWDATA[47:40];
|
|
||||||
3'b110: Din = PWDATA[55:48];
|
|
||||||
3'b111: Din = PWDATA[63:56];
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
end else begin:uart // 32-bit
|
|
||||||
always_comb begin
|
|
||||||
PRDATA = {Dout, Dout, Dout, Dout};
|
|
||||||
case (entry[1:0])
|
|
||||||
2'b00: Din = PWDATA[7:0];
|
|
||||||
2'b01: Din = PWDATA[15:8];
|
|
||||||
2'b10: Din = PWDATA[23:16];
|
|
||||||
2'b11: Din = PWDATA[31:24];
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
logic BAUDOUTb; // loop tx clock BAUDOUTb back to rx clock RCLK
|
logic BAUDOUTb; // loop tx clock BAUDOUTb back to rx clock RCLK
|
||||||
uartPC16550D #(P.UART_PRESCALE) u(
|
uartPC16550D #(P.UART_PRESCALE) u(
|
||||||
|
@ -17,11 +17,9 @@ export TECH ?= sky90
|
|||||||
export MAXCORES ?= 1
|
export MAXCORES ?= 1
|
||||||
# MAXOPT turns on flattening, boundary optimization, and retiming
|
# MAXOPT turns on flattening, boundary optimization, and retiming
|
||||||
# The output netlist is hard to interpret, but significantly better PPA
|
# The output netlist is hard to interpret, but significantly better PPA
|
||||||
# WRAPPER turns on wrapper generation
|
|
||||||
export MAXOPT ?= 0
|
export MAXOPT ?= 0
|
||||||
export DRIVE ?= FLOP
|
export DRIVE ?= FLOP
|
||||||
export USESRAM ?= 0
|
export USESRAM ?= 0
|
||||||
export WRAPPER ?= 0
|
|
||||||
|
|
||||||
|
|
||||||
time := $(shell date +%F-%H-%M)
|
time := $(shell date +%F-%H-%M)
|
||||||
@ -120,11 +118,6 @@ ifeq ($(SAIFPOWER), 1)
|
|||||||
cp -f ../sim/power.saif .
|
cp -f ../sim/power.saif .
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
|
||||||
mkwrapper:
|
|
||||||
ifeq ($(WRAPPER),1)
|
|
||||||
python3 $(WALLY)/synthDC/scripts/wrapperGen.py $(DESIGN)
|
|
||||||
endif
|
|
||||||
mkdirecs:
|
mkdirecs:
|
||||||
@echo "DC Synthesis"
|
@echo "DC Synthesis"
|
||||||
@mkdir -p $(OUTPUTDIR)
|
@mkdir -p $(OUTPUTDIR)
|
||||||
@ -134,7 +127,7 @@ mkdirecs:
|
|||||||
@mkdir -p $(OUTPUTDIR)/mapped
|
@mkdir -p $(OUTPUTDIR)/mapped
|
||||||
@mkdir -p $(OUTPUTDIR)/unmapped
|
@mkdir -p $(OUTPUTDIR)/unmapped
|
||||||
|
|
||||||
synth: mkwrapper mkdirecs configs rundc # clean
|
synth: mkdirecs configs rundc # clean
|
||||||
|
|
||||||
rundc:
|
rundc:
|
||||||
ifeq ($(TECH), tsmc28psyn)
|
ifeq ($(TECH), tsmc28psyn)
|
||||||
|
@ -24,18 +24,20 @@ set hdl_src "../src"
|
|||||||
set saifpower $::env(SAIFPOWER)
|
set saifpower $::env(SAIFPOWER)
|
||||||
set maxopt $::env(MAXOPT)
|
set maxopt $::env(MAXOPT)
|
||||||
set drive $::env(DRIVE)
|
set drive $::env(DRIVE)
|
||||||
set wrapper $::env(WRAPPER)
|
|
||||||
|
|
||||||
eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
|
eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
|
||||||
eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/}
|
eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/}
|
||||||
#eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/}
|
|
||||||
eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
|
eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
|
||||||
eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
|
eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
|
||||||
if {$wrapper ==1 } {
|
|
||||||
|
# Check if a wrapper is needed (when cvw_t parameters are used)
|
||||||
|
set wrapper 0
|
||||||
|
if {[eval exec grep "cvw_t" {$outputDir/hdl/$::env(DESIGN).sv}] ne ""} {
|
||||||
|
set wrapper 1
|
||||||
|
exec python3 $::env(WALLY)/synthDC/scripts/wrapperGen.py $::env(DESIGN)
|
||||||
eval file copy -force [glob ${hdl_src}/../synthDC/wrappers/$::env(DESIGN)wrapper.sv] {$outputDir/hdl/}
|
eval file copy -force [glob ${hdl_src}/../synthDC/wrappers/$::env(DESIGN)wrapper.sv] {$outputDir/hdl/}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
# Only for FMA class project; comment out when done
|
# Only for FMA class project; comment out when done
|
||||||
# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
|
# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
|
||||||
|
|
||||||
@ -53,6 +55,7 @@ if { $wrapper == 1 } {
|
|||||||
} else {
|
} else {
|
||||||
set my_toplevel $::env(DESIGN)
|
set my_toplevel $::env(DESIGN)
|
||||||
}
|
}
|
||||||
|
set my_design $::env(DESIGN)
|
||||||
|
|
||||||
# Set number of significant digits
|
# Set number of significant digits
|
||||||
set report_default_significant_digits 6
|
set report_default_significant_digits 6
|
||||||
@ -145,18 +148,22 @@ set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]]
|
|||||||
|
|
||||||
# Setting constraints on input ports
|
# Setting constraints on input ports
|
||||||
if {$tech == "sky130"} {
|
if {$tech == "sky130"} {
|
||||||
set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk
|
if {$drive == "INV"} {
|
||||||
|
set_driving_cell -lib_cell inv -pin Y $all_in_ex_clk
|
||||||
|
} elseif {$drive == "FLOP"} {
|
||||||
|
set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk
|
||||||
|
}
|
||||||
} elseif {$tech == "sky90"} {
|
} elseif {$tech == "sky90"} {
|
||||||
if {$drive == "INV"} {
|
if {$drive == "INV"} {
|
||||||
set_driving_cell -lib_cell scc9gena_inv_1 -pin Y $all_in_ex_clk
|
set_driving_cell -lib_cell scc9gena_inv_1 -pin Y $all_in_ex_clk
|
||||||
} elseif {$drive == "FLOP"} {
|
} elseif {$drive == "FLOP"} {
|
||||||
set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk
|
set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk
|
||||||
}
|
}
|
||||||
} elseif {$tech == "tsmc28" || $tech=="tsmc28psyn"} {
|
} elseif {$tech == "tsmc28" || $tech=="tsmc28psyn"} {
|
||||||
if {$drive == "INV"} {
|
if {$drive == "INV"} {
|
||||||
set_driving_cell -lib_cell INVD1BWP30P140 -pin ZN $all_in_ex_clk
|
set_driving_cell -lib_cell INVD1BWP30P140 -pin ZN $all_in_ex_clk
|
||||||
} elseif {$drive == "FLOP"} {
|
} elseif {$drive == "FLOP"} {
|
||||||
set_driving_cell -lib_cell DFQD1BWP30P140 -pin Q $all_in_ex_clk
|
set_driving_cell -lib_cell DFQD1BWP30P140 -pin Q $all_in_ex_clk
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -171,16 +178,20 @@ if {$drive == "FLOP"} {
|
|||||||
|
|
||||||
# Setting load constraint on output ports
|
# Setting load constraint on output ports
|
||||||
if {$tech == "sky130"} {
|
if {$tech == "sky130"} {
|
||||||
set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs]
|
|
||||||
} elseif {$tech == "sky90"} {
|
|
||||||
if {$drive == "INV"} {
|
if {$drive == "INV"} {
|
||||||
set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_inv_4/A] * 1] [all_outputs]
|
set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__inv_4/A] * 1] [all_outputs]
|
||||||
|
} elseif {$drive == "FLOP"} {
|
||||||
|
set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs]
|
||||||
|
}
|
||||||
|
} elseif {$tech == "sky90"} {
|
||||||
|
if {$drive == "INV"} {
|
||||||
|
set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_inv_4/A] * 1] [all_outputs]
|
||||||
} elseif {$drive == "FLOP"} {
|
} elseif {$drive == "FLOP"} {
|
||||||
set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs]
|
set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs]
|
||||||
}
|
}
|
||||||
} elseif {$tech == "tsmc28" || $tech == "tsmc28psyn"} {
|
} elseif {$tech == "tsmc28" || $tech == "tsmc28psyn"} {
|
||||||
if {$drive == "INV"} {
|
if {$drive == "INV"} {
|
||||||
set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/INVD4BWP30P140/I] * 1] [all_outputs]
|
set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/INVD4BWP30P140/I] * 1] [all_outputs]
|
||||||
} elseif {$drive == "FLOP"} {
|
} elseif {$drive == "FLOP"} {
|
||||||
set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/DFQD1BWP30P140/D] * 1] [all_outputs]
|
set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/DFQD1BWP30P140/D] * 1] [all_outputs]
|
||||||
}
|
}
|
||||||
@ -238,6 +249,12 @@ set write_rep 1 ;# generates estimated area and timing report
|
|||||||
set write_cst 1 ;# generate report of constraints
|
set write_cst 1 ;# generate report of constraints
|
||||||
set write_hier 1 ;# generate hierarchy report
|
set write_hier 1 ;# generate hierarchy report
|
||||||
|
|
||||||
|
# Report on DESIGN, not wrapper. However, design has a suffix for the parameters.
|
||||||
|
if { $wrapper == 1 } {
|
||||||
|
set designname [format "%s%s" $my_design "__*"]
|
||||||
|
current_design $designname
|
||||||
|
}
|
||||||
|
|
||||||
# Report Constraint Violators
|
# Report Constraint Violators
|
||||||
set filename [format "%s%s" $outputDir "/reports/constraint_all_violators.rpt"]
|
set filename [format "%s%s" $outputDir "/reports/constraint_all_violators.rpt"]
|
||||||
redirect $filename {report_constraint -all_violators}
|
redirect $filename {report_constraint -all_violators}
|
||||||
@ -246,16 +263,16 @@ redirect $filename {report_constraint -all_violators}
|
|||||||
redirect $outputDir/reports/check_design.rpt { check_design }
|
redirect $outputDir/reports/check_design.rpt { check_design }
|
||||||
|
|
||||||
# Report Final Netlist (Hierarchical)
|
# Report Final Netlist (Hierarchical)
|
||||||
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sv"]
|
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sv"]
|
||||||
write_file -f verilog -hierarchy -output $filename
|
write_file -f verilog -hierarchy -output $filename
|
||||||
|
|
||||||
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdc"]
|
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sdc"]
|
||||||
write_sdc $filename
|
write_sdc $filename
|
||||||
|
|
||||||
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".ddc"]
|
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".ddc"]
|
||||||
write_file -format ddc -hierarchy -o $filename
|
write_file -format ddc -hierarchy -o $filename
|
||||||
|
|
||||||
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdf"]
|
set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sdf"]
|
||||||
write_sdf $filename
|
write_sdf $filename
|
||||||
|
|
||||||
# QoR
|
# QoR
|
||||||
|
@ -43,7 +43,7 @@ index=0
|
|||||||
|
|
||||||
# string copy logic
|
# string copy logic
|
||||||
for l in lines:
|
for l in lines:
|
||||||
if l.find("module") == 0:
|
if l.lstrip().find("module") == 0:
|
||||||
lineModuleStart = index
|
lineModuleStart = index
|
||||||
moduleName = l.split()[1]
|
moduleName = l.split()[1]
|
||||||
writeBuf = True
|
writeBuf = True
|
||||||
@ -51,7 +51,7 @@ for l in lines:
|
|||||||
continue
|
continue
|
||||||
if (writeBuf):
|
if (writeBuf):
|
||||||
buf += l
|
buf += l
|
||||||
if l.find (");") == 0:
|
if l.lstrip().find (");") == 0:
|
||||||
lineModuleEnd = index
|
lineModuleEnd = index
|
||||||
break
|
break
|
||||||
index+=1
|
index+=1
|
||||||
@ -63,8 +63,8 @@ buf += f"\t{moduleName} #(P) dut(.*);\nendmodule"
|
|||||||
wrapperPath = f"{os.getenv('WALLY')}/synthDC/wrappers/{moduleName}wrapper.sv"
|
wrapperPath = f"{os.getenv('WALLY')}/synthDC/wrappers/{moduleName}wrapper.sv"
|
||||||
|
|
||||||
# clear wrappers directory
|
# clear wrappers directory
|
||||||
os.system(f"rm {os.getenv('WALLY')}/synthDC/wrappers/*")
|
os.system(f"rm -f {os.getenv('WALLY')}/synthDC/wrappers/*")
|
||||||
os.system(f"mkdir {os.getenv('WALLY')}/synthDC/wrappers")
|
os.system(f"mkdir -p {os.getenv('WALLY')}/synthDC/wrappers")
|
||||||
|
|
||||||
fout = open(wrapperPath, "w")
|
fout = open(wrapperPath, "w")
|
||||||
|
|
||||||
@ -75,4 +75,4 @@ fout.close()
|
|||||||
|
|
||||||
|
|
||||||
|
|
||||||
print(buf)
|
#print(buf)
|
Loading…
Reference in New Issue
Block a user