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Update if-then-else for ram items

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This commit is contained in:
James Stine 2023-02-15 18:12:12 -06:00
parent e0e8af4612
commit 744991bd5a
2 changed files with 8 additions and 8 deletions
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8
src/generic/mem/ram1p1rwbe.sv
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@ -55,7 +55,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
logic [WIDTH-1:0] BitWriteMask;
for (index=0; index < WIDTH; index++)
assign BitWriteMask[index] = bwe[index/8];
TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
.A(addr), .D(din),
.BWEB(~BitWriteMask), .Q(dout));
@ -69,13 +69,13 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
.A(addr), .D(din),
.BWEB(~BitWriteMask), .Q(dout));
end if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin
end else if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin
genvar index;
// 64 x 128-bit SRAM
logic [WIDTH-1:0] BitWriteMask;
for (index=0; index < WIDTH; index++)
assign BitWriteMask[index] = bwe[index/8];
TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
ram1p1rwbe_128x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
.A(addr), .D(din),
.BWEB(~BitWriteMask), .Q(dout));
@ -85,7 +85,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
logic [WIDTH-1:0] BitWriteMask;
for (index=0; index < WIDTH; index++)
assign BitWriteMask[index] = bwe[index/8];
ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
.A(addr), .D(din),
.BWEB(~BitWriteMask), .Q(dout));

2
src/generic/mem/ram2p1r1wbe.sv
View File

@ -64,7 +64,7 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
.QA(rd1),
.QB());
end if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin
end else if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin
ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk),
.CEBA(~ce1), .CEBB(~ce2),