diff --git a/.gitignore b/.gitignore index 630731b23..a675f900d 100644 --- a/.gitignore +++ b/.gitignore @@ -114,4 +114,5 @@ sim/vsim.log tests/coverage/*.elf *.elf.memfile sim/*Cache.log -sim/branch \ No newline at end of file +sim/branch +tests/fp/combined_IF_vectors/IF_vectors/*.tv diff --git a/docs/testplans/testplan.md b/docs/testplans/testplan.md index a25b3a189..37390a632 100644 --- a/docs/testplans/testplan.md +++ b/docs/testplans/testplan.md @@ -1,6 +1,29 @@ -# CORE-V Wally Test Plan +# CORE-V Wally Design Verification Test Plan + +CORE-V Wally is functionally tested in the following ways. Each test is run in lock-step against ImperasDV to ensure all architectural state is correct after each instruction. + +| Functions | Coverage Method | Status | +| ----------- | ----------- |----| +| Instructions | riscv-arch-test | Pass | +| Privileged Unit | wally-riscv-arch-test | Pass | +| Virtual Memory | wally-riscv-arch-test | Pass | +| PMP | wally-riscv-arch-test | Pass +| Peripherals | wally-riscv-arch-test | Pass | +| Floating-Point | TestFloat | Pass | +| General | Code Coverage | 91% | +| General | Boot Linux in Sim | Pass | +| General | Boot Linux on FPGA | Pass | + + +The following performance validation is also run: +| Function | Method | Status | +| --- | --- | --- | +| Overall Performance | embench | Pass| +| Overall Performance | coremark | Pass | +| Branch Predictor | *** | Pass | +| Cache Miss Rate | *** | Pass | + -CORE-V Wally is tested in the following ways: * Run [RISC-V Architecture Compatibility Tests](https://github.com/riscv-non-isa/riscv-arch-test) in lock-step against the ImperasDV reference model. * Run custom tests to cover virtual memory, PMP, privileged unit, and peripherals in lock step against ImperasDV. diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index ff34c0327..1d6f5bcce 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -3,9 +3,9 @@ sdc_src := ~/repos/sdc.tar.gz # Select the desired board and the all build rules # vcu118 -#export XILINX_PART := xcvu9p-flga2104-2L-e -#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 -#export board := vcu118 +export XILINX_PART := xcvu9p-flga2104-2L-e +export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 +export board := vcu118 # vcu108 #export XILINX_PART := xcvu095-ffva2104-2-e @@ -13,15 +13,15 @@ sdc_src := ~/repos/sdc.tar.gz #export board := vcu108 # Arty A7 -export XILINX_PART := xc7a100tcsg324-1 -export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1 -export board := ArtyA7 +#export XILINX_PART := xc7a100tcsg324-1 +#export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1 +#export board := ArtyA7 # for Arty A7 and S7 boards -all: FPGA_Arty +#all: FPGA_Arty # VCU 108 and VCU 118 boards -#all: FPGA_VCU +all: FPGA_VCU FPGA_Arty: PreProcessFiles IP_Arty SDC vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index 4f90333a9..88116aa3d 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -31,11 +31,14 @@ do GetLineNum.do # LZA (i<64) statement confuses coverage tool -# This is ugly to exlcude the whole file - is there a better option? // coverage off isn't working +# DH 4/22/23: Exclude all LZAs coverage exclude -srcfile lzc.sv -# FDIVSQRT has +# DH 4/22/23: FDIVSQRT can't go directly from done to busy again coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state DONE->BUSY +# DH 4/22/23: The busy->idle transition only occurs if a FlushE occurs while the divider is busy. The flush is caused by a trap or return, +# which won't happen while the divider is busy. +coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state BUSY->IDLE ### Exclude D$ states and logic for the I$ instance # This is cleaner than trying to set an I$-specific pragma in cachefsm.sv (which would exclude it for the D$ instance too) @@ -74,7 +77,7 @@ for {set i 0} {$i < $numcacheways} {incr i} { coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetDirtyWay"] -item e 1 coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6 # below: flushD can't go high during an icache write b/c of pipeline stall - coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetValidEN"] -item e 1 -fecexprrow 4 + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4 } ## D$ Exclusions. @@ -85,11 +88,18 @@ coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [Get coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 4 set numcacheways 4 for {set i 0} {$i < $numcacheways} {incr i} { - coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item be 1 -fecexprrow 4 + coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4 + + # FlushStage=1 will never happen when SetValidWay=1 since a pipeline stall is asserted by the cache in the fetch stage, which happens before + # going into the WRITE_LINE state (and asserting SetValidWay). No TrapM can fire and since StallW is high, a stallM caused by WFIStallM would not cause a flushW. + coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4 } # D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY +#################### +# Unused / illegal peripheral accesses +#################### # Excluding peripherals as sources of instructions for the ifu coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/clintdec @@ -97,31 +107,108 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/gpiodec coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uartdec coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/plicdec +# PMA Regions 8, 9, and 10 (dtim, irom, ddr4) are never used in the rv64gc configuration, so exclude coverage +set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-cachable"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 +set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-idempotent"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6 +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6,8 +set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-atomic"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 +set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-tim"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 + # Excluding so far un-used instruction sources for the ifu coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec - #Excluding the bootrom, uncoreran, and clint as sources for the lsu coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec - #Excluding signals in lsu: clintdec and uncoreram accept all sizes so 'SizeValid' will never be 0 set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5 set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5 -# Excluding signals in lsu: the lsu never executes instructions so 'ExecuteAccess' will never be 1 +#################### +# Unused access types due to sharing IFU and LSU logic +#################### + +## The lsu never executes instructions so 'ExecuteAccessF' will never be 1 set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX ="] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 6 set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 4 +set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 +set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2 +set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 1,2,4 +set line [GetLineNum ../src/mmu/mmu.sv "PMAInstrAccessFaultF \\|"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6 +set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6 +set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"] +coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 3 -# Excluding ReadAccess and WriteAccess signal in the ifu that will never be true + +## The IFU has ReadAccess = WriteAccess = 0 and ExecuteAccess = 1 hardwired, so exclude alternatives set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 4 set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-5 set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"] -coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3 \ No newline at end of file +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3 +set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"] +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1 +set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM & PMAAccessFault"] +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2-4 +set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM & PMAAccessFault"] +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2-4 +set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX \\| AtomicAccessM"] +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 3 +set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"] +coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,3,4 +set line [GetLineNum ../src/mmu/mmu.sv "ReadAccessM & ~WriteAccessM"] +coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2-4 +set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & WriteAccessM"] +coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4 +set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"] +coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 3 +set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ReadNoAmoAccessM"] +coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4 +set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & WriteAccessM"] +coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4 +set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & ReadNoAmoAccessM"] +coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4 +set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & WriteAccessM"] +coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6 +set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ReadAccessM"] +coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6 +set line [GetLineNum ../src/mmu/mmu.sv "PMALoadAccessFaultM \\| PMPLoadAccessFaultM"] +coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6 +set line [GetLineNum ../src/mmu/mmu.sv "PMAStoreAmoAccessFaultM \\| PMPStoreAmoAccessFaultM"] +coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6 +set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "ReadAccess \\| WriteAccess"] +coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 1,3,4 +set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "CAMHit & TLBAccess"] +coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3 +set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "~CAMHit & TLBAccess"] +coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3 + +# Excluding reset and clear for impossible case in the wficountreg in privdec +set line [GetLineNum ../src/generic/flop/floprc.sv "reset \\| clear"] +coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2 + +# TLB not recently used never has all RU bits = 1 because it will then clear all to 0 +# This is a blunt instrument; perhaps there is a more graceful exclusion +coverage exclude -srcfile priorityonehot.sv + +# Excluding pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 +coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1 +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1 diff --git a/sim/linux-wave.do b/sim/linux-wave.do index d8bb0f3db..614c6ab07 100644 --- a/sim/linux-wave.do +++ b/sim/linux-wave.do @@ -3,17 +3,18 @@ quietly virtual function -install /testbench/dut/core/lsu -env /testbench/dut/co quietly WaveActivateNextPane {} 0 add wave -noupdate /testbench/clk add wave -noupdate /testbench/reset -add wave -noupdate -expand -group Testbench /testbench/reset_ext -add wave -noupdate -expand -group Testbench -radix unsigned /testbench/InstrCountW -add wave -noupdate -expand -group Testbench -radix unsigned /testbench/AttemptedInstructionCount -add wave -noupdate -expand -group Testbench -radix decimal /testbench/interruptInstrCount -add wave -noupdate -expand -group Testbench /testbench/interruptCauseVal -add wave -noupdate -expand -group Testbench /testbench/interruptEpcVal -add wave -noupdate -expand -group Testbench /testbench/interruptTVal -add wave -noupdate -expand -group Testbench /testbench/interruptDesc -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE +add wave -noupdate /testbench/dut/core/priv/priv/SATP_REGW +add wave -noupdate -group Testbench /testbench/reset_ext +add wave -noupdate -group Testbench -radix unsigned /testbench/InstrCountW +add wave -noupdate -group Testbench -radix unsigned /testbench/AttemptedInstructionCount +add wave -noupdate -group Testbench -radix decimal /testbench/interruptInstrCount +add wave -noupdate -group Testbench /testbench/interruptCauseVal +add wave -noupdate -group Testbench /testbench/interruptEpcVal +add wave -noupdate -group Testbench /testbench/interruptTVal +add wave -noupdate -group Testbench /testbench/interruptDesc add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/priv/priv/InterruptM add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE @@ -30,17 +31,16 @@ add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW add wave -noupdate -group {instruction pipeline} /testbench/InstrFName -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM @@ -73,55 +73,12 @@ add wave -noupdate -group {WriteBack stage} /testbench/ExpectedPCW add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName add wave -noupdate -group {WriteBack stage} /testbench/textW -add wave -noupdate -group Bpred -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR -add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF -add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} -add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]} -add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check} -add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI -add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI -add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI -add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight -add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong -add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 17 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0 -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1 -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1 -add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC -add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredE add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE -add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/BPPredDirWrongE -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget -add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCE -add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1 -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF -add wave -noupdate -group PCS /testbench/dut/core/PCF add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD add wave -noupdate -group PCS /testbench/dut/core/PCE add wave -noupdate -group PCS /testbench/dut/core/PCM @@ -129,10 +86,6 @@ add wave -noupdate -group PCS /testbench/PCW add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext0F -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PrivilegedChangePCM add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2 @@ -147,7 +100,6 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUControl add wave -noupdate -group alu -divider internals add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D @@ -165,10 +117,6 @@ add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/Load add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE -add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF -add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState -add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0 -add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr @@ -176,162 +124,149 @@ add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNe add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF -add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/PAdrM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM[2]} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits[2]} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits[2]} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_D -add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_A -add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_U -add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_X -add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_W -add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_R -add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_V -add wave -noupdate -expand -group lsu -group dtlb -expand -group Status -color Maroon /testbench/dut/core/lsu/dmmu/dmmu/DAPageFault -add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/ImproperPrivilege -add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/UpperBitsUnequalPageFault -add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Misaligned -add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidRead -add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidWrite -add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -group lsu /testbench/dut/core/lsu/PAdrM +add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} +add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr +add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty +add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM[2]} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits[2]} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits[2]} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM +add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit +add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_D +add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_A +add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_U +add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_X +add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_W +add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_R +add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_V +add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/ImproperPrivilege +add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Misaligned +add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidRead +add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidWrite +add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY @@ -344,23 +279,12 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK -add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PCNext2F -add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM -add wave -noupdate -group AHB -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM -add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/funct -add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/result -add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/srca -add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/srcb -add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/width add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite add wave -noupdate -group itlb /testbench/dut/core/ifu/ITLBMissF add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PMAInstrAccessFaultF add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsIn -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsOut -add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsEn add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP @@ -412,9 +336,10 @@ add wave -noupdate /testbench/dut/core/lsu/LSUHWRITE add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate /testbench/dut/core/priv/priv/PrivilegeModeW TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{invalid oad data} {15916799 ns} 1} {{original store} {4919493 ns} 1} {{correct load data} {15300495 ns} 1} {{Cursor 4} {4919381 ns} 1} {{Cursor 5} {4934568 ns} 0} -quietly wave cursor active 5 +WaveRestoreCursors {{invalid oad data} {15916799 ns} 1} {{original store} {4919493 ns} 1} {{correct load data} {165196425 ns} 0} {{Cursor 4} {165662196 ns} 1} {{Cursor 5} {165196436 ns} 1} +quietly wave cursor active 3 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 configure wave -justifyvalue left @@ -429,4 +354,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {4934554 ns} {4934778 ns} +WaveRestoreZoom {165196205 ns} {165196487 ns} diff --git a/sim/run-imperas-linux.sh b/sim/run-imperas-linux.sh index 00e9845cf..fd265cb9e 100755 --- a/sim/run-imperas-linux.sh +++ b/sim/run-imperas-linux.sh @@ -4,6 +4,7 @@ export IMPERAS_TOOLS=$(pwd)/imperas.ic export OTHERFLAGS="+TRACE2LOG_ENABLE=1" -export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000" +#export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000" +export OTHERFLAGS="" vsim -c -do "do wally-linux-imperas.do buildroot buildroot-no-trace $::env(RISCV) 0 0 0" diff --git a/sim/wally-linux-imperas.do b/sim/wally-linux-imperas.do index a95dc51a3..66424602b 100644 --- a/sim/wally-linux-imperas.do +++ b/sim/wally-linux-imperas.do @@ -35,7 +35,7 @@ vlib work if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation - vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt + vopt work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 #-- Run the Simulation diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 0a1a07cab..e84c34dee 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -113,7 +113,7 @@ module cacheLRU // The root node of the LRU tree will always be selected in LRUUpdate. No mux needed. assign NextLRU[NUMWAYS-2] = ~WayExpanded[NUMWAYS-2]; - mux2 #(1) LRUMuxes[NUMWAYS-3:0](CurrLRU[NUMWAYS-3:0], ~WayExpanded[NUMWAYS-3:0], LRUUpdate[NUMWAYS-3:0], NextLRU[NUMWAYS-3:0]); + if (NUMWAYS > 2) mux2 #(1) LRUMuxes[NUMWAYS-3:0](CurrLRU[NUMWAYS-3:0], ~WayExpanded[NUMWAYS-3:0], LRUUpdate[NUMWAYS-3:0], NextLRU[NUMWAYS-3:0]); // Compute next victim way. for(node = NUMWAYS-2; node >= NUMWAYS/2; node--) begin diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 34f1778f5..544e3454e 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -159,7 +159,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( assign SelFlush = (CurrState == STATE_READY & FlushCache) | (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_WRITEBACK); - // coverage off -item e -fecexprrow 1 + // coverage off -item e 1 -fecexprrow 1 // (state is always FLUSH_WRITEBACK when FlushWayFlag & CacheBusAck) assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) | (CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty); diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 368c7b587..f504f40ad 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -82,6 +82,8 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag); // FlushWay is part of a one hot way selection. Must clear it if FlushWay not selected. + // coverage off -item e 1 -fecexprrow 3 + // nonzero ways will never see SelFlush=0 while FlushWay=1 since FlushWay only advances on a subset of SelFlush assertion cases. assign FlushWayEn = FlushWay & SelFlush; assign SelNonHit = FlushWayEn | SetValid | SelWriteback; end @@ -100,7 +102,7 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, assign SetDirtyWay = SetDirty & SelData; // exclusion-tag: icache SetDirtyWay assign ClearDirtyWay = ClearDirty & SelData; assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; // exclusion-tag: icache SelectedWiteWordEn - assign SetValidEN = SetValidWay & ~FlushStage; // exclusion-tag: icache SetValidEN + assign SetValidEN = SetValidWay & ~FlushStage; // exclusion-tag: cache SetValidEN // If writing the whole line set all write enables to 1, else only set the correct word. assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index b9584bc9e..206cefbb4 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -138,10 +138,10 @@ module fctrl ( endcase 7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000) ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0; // fclass - else if (Funct3D == 3'b000 & Rs2D == 5'b00000) - ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0; // fmv.x.w / fmv.x.d to int register - 7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000) - ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0; // fmv.w.x / fmv.d.x to fp reg + else if (Funct3D == 3'b000 & Rs2D == 5'b00000 & SupportedFmt) + ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0; // fmv.x.w/d/h/q fp to int register + 7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000 & SupportedFmt) + ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0; // fmv.w/d/h/q.x int to fp reg 7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00) ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h) 7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01) diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index f4d465012..f7a443639 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -62,7 +62,7 @@ module fdivsqrt( logic [`DIVb+1:0] FirstC; // Step tracker logic Firstun; // Quotient selection logic WZeroE; // Early termination flag - logic [`DURLEN-1:0] cycles; // FSM cycles + logic [`DURLEN-1:0] CyclesE; // FSM cycles logic SpecialCaseM; // Divide by zero, square root of negative, etc. logic DivStartE; // Enable signal for flops during stall @@ -76,7 +76,7 @@ module fdivsqrt( fdivsqrtpreproc fdivsqrtpreproc( // Preprocessor .clk, .IFDivStartE, .Xm(XmE), .Ym(YmE), .Xe(XeE), .Ye(YeE), - .FmtE, .SqrtE, .XZeroE, .Funct3E, .QeM, .X, .D, .cycles, + .FmtE, .SqrtE, .XZeroE, .Funct3E, .QeM, .X, .D, .CyclesE, // Int-specific .ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE, .BZeroM, .nM, .mM, .AM, @@ -85,7 +85,7 @@ module fdivsqrt( fdivsqrtfsm fdivsqrtfsm( // FSM .clk, .reset, .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .XsE, .SqrtE, .WZeroE, .FlushE, .StallM, - .FDivBusyE, .IFDivStartE, .FDivDoneE, .SpecialCaseM, .cycles, + .FDivBusyE, .IFDivStartE, .FDivDoneE, .SpecialCaseM, .CyclesE, // Int-specific .IDivStartE, .ISpecialCaseE, .IntDivE); diff --git a/src/fpu/fdivsqrt/fdivsqrtcycles.sv b/src/fpu/fdivsqrt/fdivsqrtcycles.sv index f1ad32cd8..2e17cc25b 100644 --- a/src/fpu/fdivsqrt/fdivsqrtcycles.sv +++ b/src/fpu/fdivsqrt/fdivsqrtcycles.sv @@ -1,10 +1,10 @@ /////////////////////////////////////////// -// fdivsqrt.sv +// fdivsqrtcycles.sv // // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu, amaiuolo@hmc.edu // Modified: 18 April 2022 // -// Purpose: Combined Divide and Square Root Floating Point and Integer Unit +// Purpose: Determine number of cycles for divsqrt // // Documentation: RISC-V System on Chip Design Chapter 13 // @@ -33,7 +33,7 @@ module fdivsqrtcycles( input logic SqrtE, input logic IntDivE, input logic [`DIVBLEN:0] nE, - output logic [`DURLEN-1:0] cycles + output logic [`DURLEN-1:0] CyclesE ); logic [`DURLEN+1:0] Nf, fbits; // number of fractional bits // DIVN = `NF+3 @@ -68,8 +68,8 @@ module fdivsqrtcycles( always_comb begin if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs - if (`IDIV_ON_FPU) cycles = IntDivE ? ((nE + 1)/`DIVCOPIES) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); - else cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); + if (`IDIV_ON_FPU) CyclesE = IntDivE ? ((nE + 1)/`DIVCOPIES) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); + else CyclesE = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); end /* verilator lint_on WIDTH */ diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 5332087ad..ba0758ee6 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -39,7 +39,7 @@ module fdivsqrtfsm( input logic StallM, FlushE, input logic IntDivE, input logic ISpecialCaseE, - input logic [`DURLEN-1:0] cycles, + input logic [`DURLEN-1:0] CyclesE, output logic IFDivStartE, output logic FDivBusyE, FDivDoneE, output logic SpecialCaseM @@ -66,8 +66,7 @@ module fdivsqrtfsm( if (reset | FlushE) begin state <= #1 IDLE; end else if (IFDivStartE) begin // IFDivStartE implies stat is IDLE -// end else if ((state == IDLE) & IFDivStartE) begin // IFDivStartE implies stat is IDLE - step <= cycles; + step <= CyclesE; if (SpecialCaseE) state <= #1 DONE; else state <= #1 BUSY; end else if (state == BUSY) begin diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 43a5e42b2..3de4b252e 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -43,44 +43,49 @@ module fdivsqrtpreproc ( input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B input logic IntDivE, W64E, output logic ISpecialCaseE, - output logic [`DURLEN-1:0] cycles, + output logic [`DURLEN-1:0] CyclesE, output logic [`DIVBLEN:0] nM, mM, output logic NegQuotM, ALTBM, IntDivM, W64M, output logic AsM, BZeroM, output logic [`XLEN-1:0] AM ); - logic [`DIVb-1:0] XPreproc, DPreproc; + logic [`DIVb-1:0] Xfract, Dfract; logic [`DIVb:0] PreSqrtX; logic [`DIVb+3:0] DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed logic [`NE+1:0] QeE; // Quotient Exponent (FP only) logic [`DIVb-1:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input - logic [`DIVBLEN:0] mE, nE, ell; // Leading zeros of inputs + logic [`DIVBLEN:0] mE, nE, ell; // Leading zeros of inputs logic NumerZeroE; // Numerator is zero (X or A) logic AZeroE, BZeroE; // A or B is Zero for integer division - logic signedDiv; // signed division + logic SignedDivE; // signed division logic NegQuotE; // Integer quotient is negative logic AsE, BsE; // Signs of integer inputs logic [`XLEN-1:0] AE; // input A after W64 adjustment + logic ALTBE; + + ////////////////////////////////////////////////////// + // Integer Preprocessing + ////////////////////////////////////////////////////// if (`IDIV_ON_FPU) begin:intpreproc // Int Supported logic [`XLEN-1:0] BE, PosA, PosB; // Extract inputs, signs, zero, depending on W64 mode if applicable - assign signedDiv = ~Funct3E[0]; + assign SignedDivE = ~Funct3E[0]; // Source handling if (`XLEN==64) begin // 64-bit, supports W64 - mux2 #(64) amux(ForwardedSrcAE, {{32{ForwardedSrcAE[31] & signedDiv}}, ForwardedSrcAE[31:0]}, W64E, AE); - mux2 #(64) bmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31] & signedDiv}}, ForwardedSrcBE[31:0]}, W64E, BE); + mux2 #(64) amux(ForwardedSrcAE, {{32{ForwardedSrcAE[31] & SignedDivE}}, ForwardedSrcAE[31:0]}, W64E, AE); + mux2 #(64) bmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31] & SignedDivE}}, ForwardedSrcBE[31:0]}, W64E, BE); end else begin // 32 bits only assign AE = ForwardedSrcAE; assign BE = ForwardedSrcBE; end assign AZeroE = ~(|AE); assign BZeroE = ~(|BE); - assign AsE = AE[`XLEN-1] & signedDiv; - assign BsE = BE[`XLEN-1] & signedDiv; + assign AsE = AE[`XLEN-1] & SignedDivE; + assign BsE = BE[`XLEN-1] & SignedDivE; assign NegQuotE = AsE ^ BsE; // Integer Quotient is negative // Force integer inputs to be postiive @@ -90,35 +95,35 @@ module fdivsqrtpreproc ( // Select integer or floating point inputs mux2 #(`DIVb) ifxmux({Xm, {(`DIVb-`NF-1){1'b0}}}, {PosA, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFX); mux2 #(`DIVb) ifdmux({Ym, {(`DIVb-`NF-1){1'b0}}}, {PosB, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFD); - - + mux2 #(1) numzmux(XZeroE, AZeroE, IntDivE, NumerZeroE); end else begin // Int not supported assign IFX = {Xm, {(`DIVb-`NF-1){1'b0}}}; assign IFD = {Ym, {(`DIVb-`NF-1){1'b0}}}; + assign NumerZeroE = XZeroE; end + ////////////////////////////////////////////////////// + // Integer & FP leading zero and normalization shift + ////////////////////////////////////////////////////// + // count leading zeros for Subnorm FP and to normalize integer inputs lzc #(`DIVb) lzcX (IFX, ell); lzc #(`DIVb) lzcY (IFD, mE); // Normalization shift: shift off leading one - assign XPreproc = (IFX << ell) << 1; - assign DPreproc = (IFD << mE) << 1; + assign Xfract = (IFX << ell) << 1; + assign Dfract = (IFD << mE) << 1; - // append leading 1 (for nonzero inputs) - // shift square root to be in range [1/4, 1) - // Normalized numbers are shifted right by 1 if the exponent is odd - // Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS. They are shifted right if the number of leading zeros is odd. - mux2 #(`DIVb+1) sqrtxmux({~XZeroE, XPreproc}, {1'b0, ~XZeroE, XPreproc[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX); - assign DivX = {3'b000, ~NumerZeroE, XPreproc}; + // *** CT: move to fdivsqrtintpreshift - // Divisior register - flopen #(`DIVb+4) dreg(clk, IFDivStartE, {4'b0001, DPreproc}, D); + ////////////////////////////////////////////////////// + // Integer Right Shift to digit boundary + // Determine DivXShifted (X shifted to digit boundary) + // and nE (number of fractional digits) + ////////////////////////////////////////////////////// - // ***CT: factor out fdivsqrtcycles if (`IDIV_ON_FPU) begin:intrightshift // Int Supported logic [`DIVBLEN:0] ZeroDiff, p; - logic ALTBE; // calculate number of fractional bits p assign ZeroDiff = mE - ell; // Difference in number of leading zeros @@ -128,31 +133,68 @@ module fdivsqrtpreproc ( // Integer special cases (terminate immediately) assign ISpecialCaseE = BZeroE | ALTBE; - /* verilator lint_off WIDTH */ // calculate number of fractional digits nE and right shift amount RightShiftX to complete in discrete number of steps if (`LOGRK > 0) begin // more than 1 bit per cycle logic [`LOGRK-1:0] IntTrunc, RightShiftX; logic [`DIVBLEN:0] TotalIntBits, IntSteps; - + /* verilator lint_off WIDTH */ assign TotalIntBits = `LOGR + p; // Total number of result bits (r integer bits plus p fractional bits) assign IntTrunc = TotalIntBits % `RK; // Truncation check for ceiling operator assign IntSteps = (TotalIntBits >> `LOGRK) + |IntTrunc; // Number of steps for int div assign nE = (IntSteps * `DIVCOPIES) - 1; // Fractional digits assign RightShiftX = `RK - 1 - ((TotalIntBits - 1) % `RK); // Right shift amount assign DivXShifted = DivX >> RightShiftX; // shift X by up to R*K-1 to complete in nE steps + /* verilator lint_on WIDTH */ end else begin // radix 2 1 copy doesn't require shifting assign nE = p; assign DivXShifted = DivX; end - /* verilator lint_on WIDTH */ + end else begin + assign ISpecialCaseE = 0; + end - // Selet integer or floating-point operands - mux2 #(1) numzmux(XZeroE, AZeroE, IntDivE, NumerZeroE); + // CT *** fdivsqrtfplead1 + + ////////////////////////////////////////////////////// + // Floating-Point Preprocessing + // append leading 1 (for nonzero inputs) + // shift square root to be in range [1/4, 1) + // Normalized numbers are shifted right by 1 if the exponent is odd + // Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS. They are shifted right if the number of leading zeros is odd. + ////////////////////////////////////////////////////// + + assign DivX = {3'b000, ~NumerZeroE, Xfract}; + + // Sqrt is initialized on step one as R(X-1), so depends on Radix + mux2 #(`DIVb+1) sqrtxmux({~XZeroE, Xfract}, {1'b0, ~XZeroE, Xfract[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX); + if (`RADIX == 2) assign SqrtX = {3'b111, PreSqrtX}; + else assign SqrtX = {2'b11, PreSqrtX, 1'b0}; + mux2 #(`DIVb+4) prexmux(DivX, SqrtX, SqrtE, PreShiftX); + + ////////////////////////////////////////////////////// + // Selet integer or floating-point operands + ////////////////////////////////////////////////////// + + if (`IDIV_ON_FPU) begin mux2 #(`DIVb+4) xmux(PreShiftX, DivXShifted, IntDivE, X); + end else begin + assign X = PreShiftX; + end + // Divisior register + flopen #(`DIVb+4) dreg(clk, IFDivStartE, {4'b0001, Dfract}, D); + + // Floating-point exponent + fdivsqrtexpcalc expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .XZero(XZeroE), .ell, .m(mE), .Qe(QeE)); + flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM); + + // Number of FSM cycles (to FSM) + fdivsqrtcycles cyclecalc(.FmtE, .SqrtE, .IntDivE, .nE, .CyclesE); + + if (`IDIV_ON_FPU) begin:intpipelineregs // pipeline registers - flopen #(1) mdureg(clk, IFDivStartE, IntDivE, IntDivM); + flopen #(1) mdureg(clk, IFDivStartE, IntDivE, IntDivM); flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM); flopen #(1) negquotreg(clk, IFDivStartE, NegQuotE, NegQuotM); flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM); @@ -162,21 +204,7 @@ module fdivsqrtpreproc ( flopen #(`XLEN) srcareg(clk, IFDivStartE, AE, AM); if (`XLEN==64) flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M); - end else begin - assign NumerZeroE = XZeroE; - assign X = PreShiftX; end - // Sqrt is initialized on step one as R(X-1), so depends on Radix - if (`RADIX == 2) assign SqrtX = {3'b111, PreSqrtX}; - else assign SqrtX = {2'b11, PreSqrtX, 1'b0}; - mux2 #(`DIVb+4) prexmux(DivX, SqrtX, SqrtE, PreShiftX); - - // Floating-point exponent - fdivsqrtexpcalc expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .XZero(XZeroE), .ell, .m(mE), .Qe(QeE)); - flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM); - - // Number of FSM cycles (to FSM) - fdivsqrtcycles cyclecalc(.FmtE, .SqrtE, .IntDivE, .nE, .cycles); endmodule diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv index 82a2eb8f1..4f7852455 100644 --- a/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -303,8 +303,8 @@ module unpackinput ( assign Man = {ExpNonZero, Frac}; // add the assumed one (or zero if Subnormal or zero) to create the significand assign NaN = ((ExpMax & ~FracZero)|BadNaNBox)&En; // is the input a NaN? assign SNaN = NaN&~Frac[`NF-1]&~BadNaNBox; // is the input a singnaling NaN? - assign Inf = ExpMax & FracZero &En & ~BadNaNBox; // is the input infinity? - assign Zero = ~ExpNonZero & FracZero & ~BadNaNBox; // is the input zero? + assign Inf = ExpMax & FracZero & En; // is the input infinity? + assign Zero = ~ExpNonZero & FracZero; // is the input zero? assign Subnorm = ~ExpNonZero & ~FracZero & ~BadNaNBox; // is the input subnormal endmodule \ No newline at end of file diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byteop.sv similarity index 96% rename from src/ieu/bmu/byte.sv rename to src/ieu/bmu/byteop.sv index 32031059a..e6099533b 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byteop.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// byte.sv +// byteop.sv // // Written: Kevin Kim // Created: 1 February 2023 @@ -29,7 +29,7 @@ `include "wally-config.vh" -module byteUnit #(parameter WIDTH=32) ( +module byteop #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, // Operands input logic ByteSelect, // LSB of Immediate output logic [WIDTH-1:0] ByteResult); // rev8, orcb result diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 1a1b9de24..3d7bcedd9 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -47,7 +47,7 @@ module zbb #(parameter WIDTH=32) ( mux2 #(1) ltmux(LT, LTU, BUnsigned , lt); cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult); - byteUnit #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult); + byteop #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult); ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult); // ZBBSelect[2] differentiates between min(u) vs max(u) instruction diff --git a/src/lsu/amoalu.sv b/src/lsu/amoalu.sv index eda3576be..d2670449a 100644 --- a/src/lsu/amoalu.sv +++ b/src/lsu/amoalu.sv @@ -34,7 +34,7 @@ module amoalu ( input logic [`XLEN-1:0] IHWriteDataM, // LSU's WriteData input logic [6:0] LSUFunct7M, // ALU Operation input logic [2:0] LSUFunct3M, // Memoy access width - output logic [`XLEN-1:0] AMOResult // ALU output + output logic [`XLEN-1:0] AMOResultM // ALU output ); logic [`XLEN-1:0] a, b, y; @@ -60,17 +60,17 @@ module amoalu ( if (`XLEN == 32) begin:sext assign a = ReadDataM; assign b = IHWriteDataM; - assign AMOResult = y; + assign AMOResultM = y; end else begin:sext // `XLEN = 64 always_comb if (LSUFunct3M[1:0] == 2'b10) begin // sign-extend word-length operations a = {{32{ReadDataM[31]}}, ReadDataM[31:0]}; b = {{32{IHWriteDataM[31]}}, IHWriteDataM[31:0]}; - AMOResult = {{32{y[31]}}, y[31:0]}; + AMOResultM = {{32{y[31]}}, y[31:0]}; end else begin a = ReadDataM; b = IHWriteDataM; - AMOResult = y; + AMOResultM = y; end end endmodule diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index fc9ede119..d33e85fe5 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -38,7 +38,7 @@ module atomic ( input logic [`PA_BITS-1:0] PAdrM, // Physical memory address input logic [6:0] LSUFunct7M, // AMO alu operation gated by HPTW input logic [2:0] LSUFunct3M, // IEU or HPTW memory operation size - input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResult as the writedata output, 01: LR/SC operation + input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation input logic [1:0] PreLSURWM, // IEU or HPTW Read/Write signal input logic IgnoreRequest, // On FlushM or TLB miss ignore memory operation output logic [`XLEN-1:0] IMAWriteDataM, // IEU, HPTW, or AMO write data @@ -46,12 +46,12 @@ module atomic ( output logic [1:0] LSURWM // IEU or HPTW Read/Write signal gated by LR/SC ); - logic [`XLEN-1:0] AMOResult; + logic [`XLEN-1:0] AMOResultM; logic MemReadM; - amoalu amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResult); + amoalu amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM); - mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResult, LSUAtomicM[1], IMAWriteDataM); + mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM); assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM); diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index f90e42ce9..2cc76e8f0 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -175,7 +175,7 @@ module hptw ( .SV39Mode(), .UpperBitsUnequal); assign InvalidRead = ReadAccess & ~Readable & (~STATUS_MXR | ~Executable); assign InvalidWrite = WriteAccess & ~Writable; - assign InvalidOp = DTLBWalk ? (InvalidRead | InvalidWrite) : ~Executable; + assign InvalidOp = DTLBWalk ? (InvalidRead | InvalidWrite) : ~Executable; assign OtherPageFault = ImproperPrivilege | InvalidOp | UpperBitsUnequal | Misaligned | ~Valid; // hptw needs to know if there is a Dirty or Access fault occuring on this diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv index 909cc564d..ace481f74 100644 --- a/src/mmu/pmachecker.sv +++ b/src/mmu/pmachecker.sv @@ -57,14 +57,14 @@ module pmachecker ( adrdecs adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWX, Size, SelRegions); // Only non-core RAM/ROM memory regions are cacheable - assign Cacheable = SelRegions[8] | SelRegions[7] | SelRegions[6]; + assign Cacheable = SelRegions[8] | SelRegions[7] | SelRegions[6]; // exclusion-tag: unused-cachable // Nonidemdempotent means access could have side effect and must not be done speculatively or redundantly // I/O is nonidempotent. - assign Idempotent = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[7] | SelRegions[6]; + assign Idempotent = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[7] | SelRegions[6]; // exclusion-tag: unused-idempotent // Atomic operations are only allowed on RAM - assign AtomicAllowed = SelRegions[10] | SelRegions[8] | SelRegions[6]; + assign AtomicAllowed = SelRegions[10] | SelRegions[8] | SelRegions[6]; // exclusion-tag: unused-atomic // Check if tightly integrated memories are selected - assign SelTIM = SelRegions[10] | SelRegions[9]; + assign SelTIM = SelRegions[10] | SelRegions[9]; // exclusion-tag: unused-tim // Detect access faults assign PMAAccessFault = (SelRegions[0]) & AccessRWX | AtomicAccessM & ~AtomicAllowed; diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv index f36fa99fc..a4fb8068b 100644 --- a/src/mmu/pmpadrdec.sv +++ b/src/mmu/pmpadrdec.sv @@ -63,7 +63,7 @@ module pmpadrdec ( assign CurrentAdrFull = {PMPAdr, 2'b00}; assign PAltPMPAdr = {1'b0, PhysicalAddress} < {1'b0, CurrentAdrFull}; // unsigned comparison assign PAgePMPAdrOut = ~PAltPMPAdr; - assign TORMatch = PAgePMPAdrIn & PAltPMPAdr; + assign TORMatch = PAgePMPAdrIn & PAltPMPAdr; // exclusion-tag: PAgePMPAdrIn // Naturally aligned regions logic [`PA_BITS-1:0] NAMask, NABase; diff --git a/src/mmu/tlb/tlblru.sv b/src/mmu/tlb/tlblru.sv index 6cdb475e3..4cabb33ab 100644 --- a/src/mmu/tlb/tlblru.sv +++ b/src/mmu/tlb/tlblru.sv @@ -50,7 +50,5 @@ module tlblru #(parameter TLB_ENTRIES = 8) ( assign RUBitsAccessed = AccessLines | RUBits; assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed; - - // enable must be ORd with TLBFlush to ensure flop fires on a flush. DH 7/8/21 - flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit | TLBWrite), RUBitsNext, RUBits); + flopenr #(TLB_ENTRIES) lrustate(clk, reset, (CAMHit | TLBWrite), RUBitsNext, RUBits); endmodule diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index db142de5f..9f3ae89b9 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -158,7 +158,7 @@ module csr #(parameter assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM, 2'b00}; // 64-byte alignment allows concatenation rather than addition mux2 #(`XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM); end else - assign TrapVectorM = TVecAlignedM; + assign TrapVectorM = TVecAlignedM; // unvectored interrupt handler can be at any word-aligned address. This is called Sstvecd // Trap Returns // A trap sets the PC to TrapVector diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index f0e5f00db..fb519be37 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -171,7 +171,8 @@ module csrm #(parameter IllegalCSRMAccessM = !(`S_SUPPORTED) & (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + `PMP_ENTRIES) // reading a PMP entry CSRMReadValM = {{(`XLEN-(`PA_BITS-2)){1'b0}}, PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0]}; - else if (CSRAdrM >= PMPCFG0 & CSRAdrM < PMPCFG0 + `PMP_ENTRIES/4) begin + else if (CSRAdrM >= PMPCFG0 & CSRAdrM < PMPCFG0 + `PMP_ENTRIES/4 & (`XLEN==32 | CSRAdrM[0] == 0)) begin + // only odd-numbered PMPCFG entries exist in RV64 if (`XLEN==64) begin entry = ({CSRAdrM[11:1], 1'b0} - PMPCFG0)*4; // disregard odd entries in RV64 CSRMReadValM = {PMPCFG_ARRAY_REGW[entry+7],PMPCFG_ARRAY_REGW[entry+6],PMPCFG_ARRAY_REGW[entry+5],PMPCFG_ARRAY_REGW[entry+4], diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 60968a68b..831366bb3 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -122,7 +122,10 @@ module csrsr ( logic [1:0] EndiannessPrivMode; always_comb begin if (SelHPTW) EndiannessPrivMode = `S_MODE; + //coverage off -item c 1 -feccondrow 1 + // status.MPRV always gets reset upon leaving machine mode, so MPRV will never be high when out of machine mode else if (PrivilegeModeW == `M_MODE & STATUS_MPRV) EndiannessPrivMode = STATUS_MPP; + //coverage on else EndiannessPrivMode = PrivilegeModeW; case (EndiannessPrivMode) @@ -174,8 +177,7 @@ module csrsr ( STATUS_MIE <= #1 STATUS_MPIE; // restore global interrupt enable STATUS_MPIE <= #1 1; // STATUS_MPP <= #1 `U_SUPPORTED ? `U_MODE : `M_MODE; // set MPP to lowest supported privilege level - // STATUS_MPRV_INT <= #1 0; // changed to this by Ross to solve Linux bug; might have been s spurious disagreement with QEMU - STATUS_MPRV_INT <= #1 STATUS_MPRV_INT & (STATUS_MPP == `M_MODE); // Seems to be given by page 21 of spec. + STATUS_MPRV_INT <= #1 STATUS_MPRV_INT & (STATUS_MPP == `M_MODE); // page 21 of privileged spec. end else if (sretM) begin STATUS_SIE <= #1 STATUS_SPIE; // restore global interrupt enable STATUS_SPIE <= #1 `S_SUPPORTED; diff --git a/src/privileged/privdec.sv b/src/privileged/privdec.sv index 21239dc95..9aaa9979e 100644 --- a/src/privileged/privdec.sv +++ b/src/privileged/privdec.sv @@ -69,7 +69,10 @@ module privdec ( logic [`WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1; assign WFICountPlus1 = WFICount + 1; floprc #(`WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount); // count while in WFI + // coverage off -item e 1 -fecexprrow 1 + // WFI Timout trap will not occur when STATUS_TW is low while in supervisor mode, so the system gets stuck waiting for an interrupt and triggers a watchdog timeout. assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != `M_MODE) | (`S_SUPPORTED & PrivilegeModeW == `U_MODE)) & WFICount[`WFI_TIMEOUT_BIT]; + // coverage on end else assign WFITimeoutM = 0; /////////////////////////////////////////// diff --git a/testbench/tests.vh b/testbench/tests.vh index a450b057d..ffe718188 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -52,18 +52,20 @@ string tvpaths[] = '{ "fpu", "lsu", "vm64check", - "pmp", + "tlbASID", + "tlbGLB", + "tlbMP", + "tlbGP", + "tlbTP", + "ifuCamlineWrite", "dcache1", "dcache2", + "pmp", "pmpcfg", "pmpcfg1", "pmpcfg2", - "tlbKP", - "tlbMP", - "tlbM3", - "tlbASID", - "tlbGLB", - "ifuCamlineWrite" + "pmppriority", + "pmpadrdecs" }; string coremark[] = '{ diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index 6b6dd6dd9..ec179a0dd 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -63,6 +63,9 @@ trap_handler: bgez t0, exception # if msb is clear, it is an exception interrupt: # must be a timer interrupt + li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again + li t1, 0x02004000 # MTIMECMP in CLINT + sd t0, 0(t1) j trap_return # clean up and return exception: diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index b2a52be06..879980899 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -28,7 +28,7 @@ main: - #bseti t0, zero, 14 # turn on FPU + bseti t0, zero, 14 # turn on FPU csrs mstatus, t0 #Pull denormalized FP number from memory and pass it to fclass.S for coverage @@ -105,6 +105,25 @@ main: # fcvt.w.q a0, ft0 # fcvt.q.d ft3, ft0 + // fdivsqrt: test busy->idle transition caused by a FlushE while divider is busy (when interrupt arrives) + // This code doesn't actually trigger a busy->idle transition because the pending timer interrupt doesn't occur until the division finishes. + li t0, 0x3F812345 # random value slightly bigger than 1 + li t1, 0x3F823456 + fmv.w.x ft0, t0 # move int to fp register + fmv.w.x ft1, t1 + li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again + li t1, 0x02004000 # MTIMECMP in CLINT + sd t0, 0(t1) + csrsi mstatus, 0b1000 # enable interrupts with mstatus.MIE + li t1, 0x0200bff8 # read MTIME in CLINT + ld t0, 0(t1) + addi t0, t0, 11 + li t1, 0x02004000 # MTIMECMP in CLINT + sd t0, 0(t1) # write mtime+10 to cause interrupt soon This is very touchy timing and is sensitive to cache line fetch latency + nop + fdiv.s ft2, ft1, ft0 # should get interrupted, triggering a flush + csrci mstatus, 0b1000 # disable interrupts with mstatus.MIE + # Completing branch coverage in fctrl.sv .word 0x38007553 // Testing the all False case for 119 - funct7 under, op = 101 0011 .word 0x40000053 // Line 145 All False Test case - illegal instruction? @@ -145,4 +164,5 @@ TestData2: .word 0x7f800000 #INF .int 0xbf800000 #FP -1.0 .int 0x7fa00000 #SNaN -.int 0x3fffffff #OverFlow Test \ No newline at end of file +.int 0x3fffffff #OverFlow Test +DivTestData: diff --git a/tests/coverage/pmpadrdecs.S b/tests/coverage/pmpadrdecs.S new file mode 100644 index 000000000..51ca4d148 --- /dev/null +++ b/tests/coverage/pmpadrdecs.S @@ -0,0 +1,22 @@ +// pmpadrdecs +// Liam Chalk, lchalk@hmc.edu, 4/27/2023 +// Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] + +#include "WALLY-init-lib.h" +main: + + # Writing values to pmpcfg0 to change AdrMode to 2 or 3 + # pmpadrdec[0] + li t0, 0x0000000010 + csrw pmpcfg0, t0 + # pmpadrdec[1] + li t0, 0x0000001800 + csrw pmpcfg0, t0 + # pmpadrdec[2] + li t0, 0x0000180000 + csrw pmpcfg0, t0 + # pmpadrdec[4] + li t0, 0x1000000000 + csrw pmpcfg0, t0 + + j done \ No newline at end of file diff --git a/tests/coverage/pmpcfg.S b/tests/coverage/pmpcfg.S index 5b3e37b56..bcc8f3950 100644 --- a/tests/coverage/pmpcfg.S +++ b/tests/coverage/pmpcfg.S @@ -1,6 +1,6 @@ // pmpcfg part 1 // Kevin Wan, kewan@hmc.edu, 4/18/2023 -// Liam Chalk, lchalk@hmc.edu, 4/19/2023 +// Liam Chalk, lchalk@hmc.edu, 4/25/2023 // locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. // See the next part in pmpcfg1.S @@ -19,34 +19,59 @@ main: li t0, 0x90000000 csrw pmpaddr0, t0 - li t0, 0x00000017 + li t0, 0x00001700 + csrw pmpcfg0, t0 + + li t0, 0x90000000 + csrw pmpaddr0, t0 + li t0, 0x00001700 csrw pmpcfg1, t0 li t0, 0x90000000 csrw pmpaddr0, t0 - li t0, 0x00000017 + li t0, 0x00001700 csrw pmpcfg2, t0 li t0, 0x90000000 csrw pmpaddr0, t0 - li t0, 0x00000017 + li t0, 0x00001700 csrw pmpcfg3, t0 li t0, 0x90000000 csrw pmpaddr1, t0 - li t0, 0x00000017 + li t0, 0x00001700 csrw pmpcfg1, t0 li t0, 0x90000000 - csrw pmpaddr1, t0 - li t0, 0x00000017 + csrw pmpaddr2, t0 + li t0, 0x00001700 csrw pmpcfg2, t0 li t0, 0x90000000 - csrw pmpaddr1, t0 - li t0, 0x00000017 + csrw pmpaddr3, t0 + li t0, 0x00001700 csrw pmpcfg3, t0 + li t0, 0x90000000 + csrw pmpaddr0, t0 + li t0, 0x00170000 + csrw pmpcfg0, t0 + + li t0, 0x90000000 + csrw pmpaddr2, t0 + li t0, 0x00170000 + csrw pmpcfg2, t0 + + li t0, 0x90000000 + csrw pmpaddr0, t0 + li t0, 0x17000000 + csrw pmpcfg0, t0 + + li t0, 0x90000000 + csrw pmpaddr2, t0 + li t0, 0x17000000 + csrw pmpcfg2, t0 + li t0, 0x8800000000000000 csrw pmpcfg2, t0 li t0, 0x88000000000000 diff --git a/tests/coverage/pmppriority.S b/tests/coverage/pmppriority.S new file mode 100644 index 000000000..da2f0f40c --- /dev/null +++ b/tests/coverage/pmppriority.S @@ -0,0 +1,161 @@ +// pmppriority test cases +// Kevin Wan kewan@hmc.edu 4/27/2023 +// want memory ranges to match: +// 1. only the most significant address and none of the lower ones, +// 2. the most significant address and ANY of the lower ones. + + + +#include "WALLY-init-lib.h" +main: + + li t1, 0x21FFFFFF // start at 0x8000000 with a range of 1000000. Address format is set to NAPOT in pmpcfg. + csrw pmpaddr0, t1 + csrw pmpaddr1, t1 + csrw pmpaddr2, t1 + csrw pmpaddr3, t1 + csrw pmpaddr4, t1 + csrw pmpaddr5, t1 + csrw pmpaddr6, t1 + csrw pmpaddr7, t1 + + csrw pmpaddr8, t1 + csrw pmpaddr9, t1 + csrw pmpaddr10, t1 + csrw pmpaddr11, t1 + csrw pmpaddr12, t1 + csrw pmpaddr13, t1 + csrw pmpaddr14, t1 + csrw pmpaddr15, t1 + + + li t0, 0x1F + csrw pmpcfg0, t0 //set to XWR and NAPOT + sw zero, 0(sp) + + li t0, 0x1F00 + csrw pmpcfg0, t0 + sw zero, 0(sp) + + li t0, 0x1F1F + csrw pmpcfg0, t0 + sw zero, 0(sp) + + li t0, 0x1F0000 + csrw pmpcfg0, t0 + sw zero, 0(sp) + + li t0, 0x1F1F1F + csrw pmpcfg0, t0 + sw zero, 0(sp) + + li t0, 0x1F000000 + csrw pmpcfg0, t0 + sw zero, 0(sp) + + li t0, 0x1F1F1F1F + csrw pmpcfg0, t0 + sw zero, 0(sp) + + li t0, 0x1F00000000 + csrw pmpcfg0, t0 + sw zero, 0(sp) + + li t0, 0x1F1F1F1F1F + csrw pmpcfg0, t0 + sw zero, 0(sp) + + li t0, 0x1F0000000000 + csrw pmpcfg0, t0 + sw zero, 0(sp) + + li t0, 0x1F1F1F1F1F1F + csrw pmpcfg0, t0 + sw zero, 0(sp) + + li t0, 0x1F000000000000 + csrw pmpcfg0, t0 + sw zero, 0(sp) + + li t0, 0x1F1F1F1F1F1F1F + csrw pmpcfg0, t0 + sw zero, 0(sp) + + li t0, 0x1F00000000000000 + csrw pmpcfg0, t0 + sw zero, 0(sp) + + li t0, 0x1F1F1F1F1F1F1F1F + csrw pmpcfg0, t0 + sw zero, 0(sp) + + li t0, 0x0 + csrw pmpcfg0, t0 + li t0, 0x1F + csrw pmpcfg2, t0 + sw zero, 0(sp) + + li t0, 0x1F00 + csrw pmpcfg2, t0 + sw zero, 0(sp) + + li t0, 0x1F0000 + csrw pmpcfg2, t0 + sw zero, 0(sp) + + li t0, 0x1F00000000 + csrw pmpcfg2, t0 + sw zero, 0(sp) + + li t0, 0x1F0000000000 + csrw pmpcfg2, t0 + sw zero, 0(sp) + + li t0, 0x1F000000000000 + csrw pmpcfg2, t0 + sw zero, 0(sp) + + li t0, 0x1F00000000000000 + csrw pmpcfg2, t0 + sw zero, 0(sp) + + li t0, 0x1F1F1F1F1F1F1F1F + csrw pmpcfg0, t0 + li t0, 0x1F + csrw pmpcfg2, t0 + sw zero, 0(sp) + + li t0, 0x1F1F + csrw pmpcfg2, t0 + sw zero, 0(sp) + + li t0, 0x1F1F1F + csrw pmpcfg2, t0 + sw zero, 0(sp) + + li t0, 0x1F1F1F1F + csrw pmpcfg2, t0 + sw zero, 0(sp) + + li t0, 0x1F1F1F1F1F + csrw pmpcfg2, t0 + sw zero, 0(sp) + + li t0, 0x1F1F1F1F1F1F + csrw pmpcfg2, t0 + sw zero, 0(sp) + + li t0, 0x1F1F1F1F1F1F1F + csrw pmpcfg2, t0 + sw zero, 0(sp) + + li t0, 0x1F1F1F1F1F1F1F1F + csrw pmpcfg2, t0 + sw zero, 0(sp) + + + + j done + + + \ No newline at end of file diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 5e187866b..d311f2a06 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -169,6 +169,24 @@ main: csrw mcounteren, t0 csrw scounteren, t0 + #getting the remainder of PMD instructions + + #go to user mode + li a0, 0 + ecall + #set status TVM to 0 by writing to bit 20 of mstatus as 0 + #bseti t0, zero, 20 + sfence.vma zero, zero + + # Go to supervisor mode + li a0, 1 + ecall + + sfence.vma zero, zero + + li a0, 3 + ecall + # Write to satp when status.TVM is 1 from machine mode bseti t0, zero, 20 csrs mstatus, t0 @@ -203,6 +221,30 @@ main: csrr t0, hpmcounter22 + #getting the mpp and mstatus Mpriv condition met + #go to machine mode + li a0, 3 + ecall + # set bit 17 of mstatus to enable STATUS_MPRV + bseti t1, zero, 17 + csrs mstatus, t1 + + li a0, 3 + ecall + + # set bit 21 of mstatus to 0 to disable STATUS_TW + csrr t1, mstatus + bseti t2, zero, 21 + not t2, t2 + and t1, t1, t2 + csrs mstatus, t1 + + # go to user mode + li a0, 0 + ecall + + wfi + j done diff --git a/tests/coverage/tlbASID.S b/tests/coverage/tlbASID.S index bf71c0491..278568147 100644 --- a/tests/coverage/tlbASID.S +++ b/tests/coverage/tlbASID.S @@ -46,26 +46,21 @@ main: li t5, 0 # j = 0 // now use as a counter for new asid loop li t3, 32 # Max amount of Loops = 32 -loop: bge t2, t3, nASID # exit loop if i >= loops - lw t1, 0(t0) +loop: bge t2, t3, finished # exit loop if i >= loops + li t1, 0x00008067 #load in jalr + sw t1, 0(t0) + fence.I + jalr t0 + li t5, 0x9001000000080080 // try making asid = 1 + csrw satp, t5 + jalr t0 + li t5, 0x9000000000080080 // try making asid = 0 + csrw satp, t5 li t4, 0x1000 add t0, t0, t4 addi t2, t2, 1 j loop - -nASID: bne t5, zero, finished - li a0, 3 // go - ecall - li t5, 0x9000100000080080 // try making asid = 1 - csrw satp, t5 - li a0, 1 - ecall - li t2, 0 - li t0, 0xC0000000 - li t5, 1 // make this not zero. - j loop - - + finished: j done @@ -130,4 +125,4 @@ pagetable: .8byte 0x200088CF .8byte 0x20008CCF - \ No newline at end of file + diff --git a/tests/coverage/tlbGLB.S b/tests/coverage/tlbGLB.S index 77e3a31c1..03bc6a629 100644 --- a/tests/coverage/tlbGLB.S +++ b/tests/coverage/tlbGLB.S @@ -48,7 +48,10 @@ main: li t3, 32 # Max amount of Loops = 32 loop: bge t2, t3, nASID # exit loop if i >= loops - lw t1, 0(t0) + li t1, 0x00008067 #load in jalr + sw t1, 0(t0) + fence.I + jalr t0 li t4, 0x1000 add t0, t0, t4 addi t2, t2, 1 @@ -79,17 +82,17 @@ pagetable: .align 12 // level 2 page table, contains direction to a gigapageg .8byte 0x0 .8byte 0x0 - .8byte 0x200000CF // gigapage that starts at 8000 0000 goes to C000 0000 - .8byte 0x200208C1 // pointer to next page table entry at 8008 2000 + .8byte 0x200000EF // gigapage that starts at 8000 0000 goes to C000 0000 + .8byte 0x200208E1 // pointer to next page table entry at 8008 2000 .align 12 // level 1 page table, points to level 0 page table .8byte 0x20020CE1 .align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2 - .8byte 0x200000CF // access xC000 0000 - .8byte 0x200004CF // access xC000 1000 - .8byte 0x200008CF // access xC000 2000 - .8byte 0x20000CCF // access xC000 3000 + .8byte 0x200000EF // access xC000 0000 + .8byte 0x200004EF // access xC000 1000 + .8byte 0x200008EF // access xC000 2000 + .8byte 0x20000CEF // access xC000 3000 .8byte 0x200010EF // access xC000 4000 .8byte 0x200014EF @@ -131,4 +134,46 @@ pagetable: .8byte 0x200088EF .8byte 0x20008CEF + .8byte 0x200010EF // access xC000 4000 + .8byte 0x200014EF + .8byte 0x200018EF + .8byte 0x20001CEF + + .8byte 0x200020EF // access xC000 8000 + .8byte 0x200024EF + .8byte 0x200028EF + .8byte 0x20002CEF + + .8byte 0x200030EF // access xC000 C000 + .8byte 0x200034EF + .8byte 0x200038EF + .8byte 0x20003CEF + + .8byte 0x200040EF // access xC001 0000 + .8byte 0x200044EF + .8byte 0x200048EF + .8byte 0x20004CEF + + .8byte 0x200050EF // access xC001 4000 + .8byte 0x200054EF + .8byte 0x200058EF + .8byte 0x20005CEF + + .8byte 0x200060EF // access xC001 8000 + .8byte 0x200064EF + .8byte 0x200068EF + .8byte 0x20006CEF + + .8byte 0x200070EF // access xC001 C000 + .8byte 0x200074eF + .8byte 0x200078EF + .8byte 0x20007CEF + + .8byte 0x200080EF // access xC002 0000 + .8byte 0x200084EF + .8byte 0x200088EF + .8byte 0x20008CEF + + + \ No newline at end of file diff --git a/tests/coverage/tlbGP.S b/tests/coverage/tlbGP.S new file mode 100644 index 000000000..ede79f13e --- /dev/null +++ b/tests/coverage/tlbGP.S @@ -0,0 +1,158 @@ +/////////////////////////////////////////// +// tlbGP.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// +// Purpose: Create Page tables and access gigapages +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate + +#include "WALLY-init-lib.h" + +# run-elf.bash find this in project description +main: + # Page table root address at 0x80010000 + li t5, 0x9000000000080010 + csrw satp, t5 + + # sfence.vma x0, x0 + + # switch to supervisor mode + li a0, 1 + ecall + li t5, 0 + li t0, 0xC0200000 // go to first gigapage + li t4, 0x40000000 // put this outside the loop. + li t2, 0 # i = 0 + li t3, 64 # Max amount of Loops = 16 + +loop: bge t2, t3, finished # exit loop if i >= loops + lw t1, 0(t0) + li t1, 0x00008067 #load in jalr + sw t1, 0(t0) + fence.I + jalr t0 + add t0, t0, t4 + addi t2, t2, 1 + j loop + +finished: + j done + +.data + +.align 16 +# Page table situated at 0x80010000 +pagetable: + .8byte 0x200044C1 + +.align 12 + .8byte 0x000000CF //8000 0000 + .8byte 0x100000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + .8byte 0x200000CF + + + + + diff --git a/tests/coverage/tlbMP.S b/tests/coverage/tlbMP.S index 6981d1f36..043e5dc4a 100644 --- a/tests/coverage/tlbMP.S +++ b/tests/coverage/tlbMP.S @@ -39,25 +39,22 @@ main: # switch to supervisor mode li a0, 1 ecall + li t5, 0 li t0, 0x84000000 // go to first megapage - li t4, 0x1000 // put this outside the loop. + li t4, 0x200000 // put this outside the loop. li t2, 0 # i = 0 li t3, 32 # Max amount of Loops = 16 -loop: bge t2, t3, lKP # exit loop if i >= loops - lw t1, 0(t0) +loop: bge t2, t3, finished # exit loop if i >= loops + li t1, 0x00008067 #load in jalr + sw t1, 0(t0) + fence.I + jalr t0 add t0, t0, t4 addi t2, t2, 1 j loop -lKP: bne t5, zero, finished - li t0, 0x80000000 - slli t4, t4, 9 - addi t5, t5, 1 - li t2, 0 - j loop - finished: j done @@ -116,6 +113,46 @@ pagetable: .8byte 0x20F000CF .8byte 0x20F800CF + .8byte 0x200000CF // access 8000,0000 I AM REPEATING PTE TO SAVE TIME. + .8byte 0x200800CF // access 8020,0000 + .8byte 0x201000CF // acesss 8040,0000 + .8byte 0x201800CF // acesss 8060,0000 + + .8byte 0x202000CF // access 8080,0000 + .8byte 0x202800CF // access 80A0,0000 + .8byte 0x203000CF // access 80C0,0000 + .8byte 0x203800CF // access 80E0,0000 + + .8byte 0x204000CF // access 8100,0000 + .8byte 0x204800CF + .8byte 0x205000CF + .8byte 0x205800CF + + .8byte 0x206000CF // access 8180,0000 + .8byte 0x206800CF + .8byte 0x207000CF + .8byte 0x207800CF + + .8byte 0x208000CF // access 8200,0000 + .8byte 0x208800CF + .8byte 0x209000CF + .8byte 0x209800CF + + .8byte 0x20A000CF // access 8280,0000 + .8byte 0x20A800CF + .8byte 0x20B000CF + .8byte 0x20B800CF + + .8byte 0x20C000CF // access 8300,0000 + .8byte 0x20C800CF + .8byte 0x20D000CF + .8byte 0x20D800CF + + .8byte 0x20E000CF // access 8380,0000 + .8byte 0x20E800CF + .8byte 0x20F000CF + .8byte 0x20F800CF + .8byte 0x20004CC1 // Kilopage entry, for addresses from 8400, 0000 to 841F, FFFF // point to ... diff --git a/tests/coverage/tlbTP.S b/tests/coverage/tlbTP.S new file mode 100644 index 000000000..54857afbd --- /dev/null +++ b/tests/coverage/tlbTP.S @@ -0,0 +1,144 @@ +/////////////////////////////////////////// +// tlbTP.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// +// Purpose: Test coverage for LSU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate + +#include "WALLY-init-lib.h" + +# run-elf.bash find this in project description +main: + # Page table root address at 0x80010000 + li t5, 0x9000000000080010 + csrw satp, t5 + + # sfence.vma x0, x0 + + # switch to supervisor mode + li a0, 1 + ecall + li t5, 0 + li t0, 0x80000000 // go to first gigapage + li t4, 0x8000000000 // put this outside the loop. + li t2, 0 # i = 0 + li t3, 64 # run through 64 PTEs + +loop: bge t2, t3, finished # exit loop if i >= loops + li t1, 0x00008067 + sw t1, 0(t0) + fence.I + jalr t0 + add t0, t0, t4 + addi t2, t2, 1 + j loop + + +finished: + j done + +.data + +.align 16 +# Page table situated at 0x80010000 +pagetable: + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF + .8byte 0x0CF \ No newline at end of file