Reworked bus to handle burst interfacing

pipelined/src/ebu/ahblite.sv

@@ -46,6 +46,7 @@ module ahblite (
   output logic [`XLEN-1:0] 	 IFUBusHRDATA,
   output logic 				 IFUBusAck,
   input logic [2:0]    IFUBurstType,
+  input logic [1:0]    IFUTransType,
   input logic          IFUBurstDone,
   // Signals from Data Cache
   input logic [`PA_BITS-1:0] LSUBusAdr,
@@ -55,6 +56,7 @@ module ahblite (
   output logic [`XLEN-1:0] 	 LSUBusHRDATA,
   input logic [2:0] 		 LSUBusSize,
   input logic [2:0]      LSUBurstType,
+  input logic [1:0]    LSUTransType,
   input logic          LSUBurstDone,
   output logic 				 LSUBusAck,
   // AHB-Lite external signals
@@ -116,17 +118,20 @@ module ahblite (
                else               NextBusState = MEMREAD;
       MEMREADNEXT: if (LSUBurstDone & ~IFUBusRead) NextBusState = IDLE;
                    else if (LSUBurstDone & IFUBusRead) NextBusState = INSTRREAD;
+                   else if (HREADY)                    NextBusState = MEMREADNEXT;
                    else                                NextBusState = MEMREAD;
       MEMWRITE: if (HREADY)       NextBusState = MEMWRITENEXT;
                 else              NextBusState = MEMWRITE;
       MEMWRITENEXT: if (LSUBurstDone & ~IFUBusRead) NextBusState = IDLE;
                     else if (LSUBurstDone & IFUBusRead) NextBusState = INSTRREAD;
+                    else if (HREADY)                    NextBusState = MEMWRITENEXT;
                     else                                NextBusState = MEMWRITE;
       INSTRREAD: if (HREADY)      NextBusState = INSTRREADNEXT;
                  else             NextBusState = INSTRREAD;
       INSTRREADNEXT: if (IFUBurstDone & ~LSUBusRead & ~LSUBusWrite) NextBusState = IDLE;
                      else if (IFUBurstDone & LSUBusRead)            NextBusState = MEMREAD;
                      else if (IFUBurstDone & LSUBusWrite)           NextBusState = MEMWRITE;
+                     else if (HREADY)                               NextBusState = INSTRREADNEXT;
                      else                                           NextBusState = INSTRREAD;
       default:                     NextBusState = IDLE;
     endcase
@@ -160,7 +165,7 @@ module ahblite (
   assign HMASTLOCK = 0; // no locking supported
   assign HWRITE = (NextBusState == MEMWRITE) | (NextBusState == MEMWRITENEXT);
   // delay write data by one cycle for
-  flop #(`XLEN) wdreg(HCLK, LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
+  flopen #(`XLEN) wdreg(HCLK, (IFUBusAck | LSUBusAck), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
   // delay signals for subword writes
   flop #(3)   adrreg(HCLK, HADDR[2:0], HADDRD);
   flop #(4)   sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED);

pipelined/src/ebu/todolist

@@ -0,0 +1,26 @@
+1. Decide whether to use ahblite or busdp implements burst.
+    a. If ahb, move capture register for the line into ahblite. Busdp will need to indicate length of read/write (probably using HBURST signal) *** Ross likes this one.
+    b. BusDP generates ALL intermediate addresses. Is still responsible for controlling HBURST. *** David likes this one, Ross from an efficiency standpoint too
+
+2. (Don't) ignore entire CPU and cache and busdp. Focus on making AHBlite that can implement burst and non-burst mode.
+    a. modify ifu to use burst. immediately detects if its working.
+        i. make sure we collect the right stuff from memory. (gets captured into ahblite's capture register)
+    b. modify busdp to use new ahblite interface.
+        i. remove capture register.
+        ii. modify fsm to expect one ack, not however many it expects right now
+        iii. increase width of data coming from ahb to cache line length.
+    c. modify cache to work with new ahb interface.
+        i. output full cacheline to ahb
+        ii. word select multiplexer (subcachelineread + lines before it) will be controlled by word count in ahb.
+            v. ONLY NEED MUX.
+
+// Don't do A
+        
+  assign CntEn = PreCntEn & LSUBusAck | (DCacheFetchLine | DCacheWriteLine);
+  assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine);
+
+    Have BusDP output HBURST (Done) and HTRANS (*** TODO) [SEQ/NONSEQ/IDLE]
+
+    Add delayed word count flop for internal capture of HRDATA and pushing HWDATA
+        WordCount is used to select which word to write. send current to cache.
+    BusDP handles HWDATA and just pushes it to ahblite.sv

pipelined/src/ifu/ifu.sv

@@ -42,6 +42,7 @@ module ifu (
 (* mark_debug = "true" *)	output logic 				IFUBusRead,
 (* mark_debug = "true" *)	output logic 				IFUStallF,
 (* mark_debug = "true" *) output logic [2:0]  IFUBurstType,
+(* mark_debug = "true" *) output logic [1:0]  IFUTransType,
 (* mark_debug = "true" *) output logic        IFUBurstDone,
 	(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, 
 	// Execute
@@ -192,7 +193,7 @@ module ifu (
     busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) 
     busdp(.clk, .reset,
           .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(), .LSUBusWriteCrit(),
-          .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUBurstDone(IFUBurstDone),
+          .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUBurstDone(IFUBurstDone),
           .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr),
           .WordCount(), 
           .DCacheFetchLine(ICacheFetchLine),

pipelined/src/lsu/busdp.sv

@@ -44,6 +44,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
   output logic                LSUBusRead,
   output logic [2:0]          LSUBusSize,
   output logic [2:0]          LSUBurstType,
+  output logic [1:0]          LSUTransType, // For AHBLite
   output logic                LSUBurstDone,
   input logic [2:0]           LSUFunct3M,
   output logic [`PA_BITS-1:0] LSUBusAdr, // ** change name to HADDR to make ahb lite.
@@ -68,6 +69,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
   
   localparam integer   WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0;
   logic [`PA_BITS-1:0]        LocalLSUBusAdr;
+  logic [LOGWPL-1:0]   WordCountDelayed;
 
 
   // *** implement flops as an array if feasbile; DCacheBusWriteData might be a problem
@@ -87,5 +89,5 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
   busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm(
     .clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine,
 		.LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead,
-		.LSUBurstType, .LSUBurstDone, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount);
+		.LSUBurstType, .LSUTransType, .LSUBurstDone, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed);
 endmodule

pipelined/src/lsu/busfsm.sv

@@ -50,10 +50,11 @@ module busfsm #(parameter integer   WordCountThreshold,
    output logic              LSUBusRead,
    output logic [2:0]        LSUBurstType,
    output logic              LSUBurstDone,
+   output logic [1:0]        LSUTransType,
    output logic              DCacheBusAck,
    output logic              BusCommittedM,
    output logic              SelUncachedAdr,
-   output logic [LOGWPL-1:0] WordCount);
+   output logic [LOGWPL-1:0] WordCount, WordCountDelayed);
   
 
   
@@ -86,10 +87,17 @@ module busfsm #(parameter integer   WordCountThreshold,
 		.d(NextWordCount),
 		.q(WordCount));  
   
+  flopenr #(LOGWPL) 
+  WordCountDelayedReg(.clk(clk),
+		.reset(reset | CntReset),
+		.en(CntEn),
+		.d(WordCount),
+		.q(WordCountDelayed));
+
   assign NextWordCount = WordCount + 1'b1;
 
-  assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0]);
+  assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]);
-  assign CntEn = PreCntEn & LSUBusAck;
+  assign CntEn = PreCntEn & LSUBusAck | (DCacheFetchLine | DCacheWriteLine);
 
   assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM;
 
@@ -129,13 +137,14 @@ module busfsm #(parameter integer   WordCountThreshold,
       8:        LocalBurstType = 3'b100; // WRAP8
       16:       LocalBurstType = 3'b110; // WRAP16
       default:  LocalBurstType = 3'b000; // No Burst
-    endcase // This block might be better in the FSM. WordCountThreshold is WordsPerLine
+    endcase // *** This isn't working, ask someone for help.
   end
 
   assign LSUBurstType = (UnCachedAccess) ? 3'b0 : LocalBurstType ; // Don't want to use burst when doing an Uncached Access
   assign LSUBurstDone = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck;
+  assign LSUTransType = (|WordCount) ? 2'b11 : (LSUBusRead | LSUBusWrite) ? 2'b10 : 2'b00; 
 
-  assign CntReset = BusCurrState == STATE_BUS_READY;
+  assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine);
   assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) |
 					(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
 					(BusCurrState == STATE_BUS_UNCACHED_READ) |

pipelined/src/lsu/lsu.sv

@@ -70,6 +70,7 @@ module lsu (
    (* mark_debug = "true" *)   output logic [`XLEN-1:0] LSUBusHWDATA,
    (* mark_debug = "true" *)   output logic [2:0] LSUBusSize, 
    (* mark_debug = "true" *)   output logic [2:0] LSUBurstType,
+   (* mark_debug = "true" *)   output logic [1:0] LSUTransType,
    (* mark_debug = "true" *)   output logic LSUBurstDone,
             // page table walker
    input logic [`XLEN-1:0]  SATP_REGW, // from csr
@@ -213,7 +214,7 @@ module lsu (
             
     busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp(
       .clk, .reset,
-      .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUBurstDone,
+      .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUBurstDone,
       .WordCount, .LSUBusWriteCrit,
       .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine,
       .DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM,

pipelined/src/wally/wallypipelinedcore.sv

@@ -137,6 +137,7 @@ module wallypipelinedcore (
   logic             IFUBusRead;
   logic             IFUBusAck;
   logic [2:0]       IFUBurstType;
+  logic [1:0]       IFUTransType;
   logic             IFUBurstDone;
   
   // AHB LSU interface
@@ -156,6 +157,7 @@ module wallypipelinedcore (
   logic             InstrAccessFaultF;
   logic [2:0]             LSUBusSize;
   logic [2:0]             LSUBurstType;
+  logic [1:0]             LSUTransType;
   logic             LSUBurstDone;
   
   logic             DCacheMiss;
@@ -172,7 +174,7 @@ module wallypipelinedcore (
     .FlushF, .FlushD, .FlushE, .FlushM, 
     // Fetch
     .IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr,
-    .IFUBusRead, .IFUStallF, .IFUBurstType, .IFUBurstDone,
+    .IFUBusRead, .IFUStallF, .IFUBurstType, .IFUTransType, .IFUBurstDone,
     .ICacheAccess, .ICacheMiss,
 
     // Execute
@@ -253,7 +255,7 @@ module wallypipelinedcore (
   .ReadDataM, .FlushDCacheM,
   // connected to ahb (all stay the same)
   .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck,
-  .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUBurstDone,
+  .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUBurstDone,
 
     // connect to csr or privilege and stay the same.
     .PrivilegeModeW, .BigEndianM,          // connects to csr
@@ -285,12 +287,13 @@ module wallypipelinedcore (
      .clk, .reset,
      .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00),
      .IFUBusAdr,
-     .IFUBusRead, .IFUBusHRDATA, .IFUBusAck, .IFUBurstType, .IFUBurstDone,
+     .IFUBusRead, .IFUBusHRDATA, .IFUBusAck, .IFUBurstType, .IFUTransType, .IFUBurstDone,
      // Signals from Data Cache
      .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA,
      .LSUBusHRDATA,
      .LSUBusSize,
      .LSUBurstType,
+     .LSUTransType,
      .LSUBurstDone,
      .LSUBusAck,