Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fixed sublte bug in the spi_fifo which allows for spurious write to fifo. Fixed fpga zsbl so that is uses read fifo interrupt pending (IP) rather than transmit fifo IP. Resolves issue with stalled load reading the wrong fifo status.

Browse Source
This commit is contained in:
Rose Thompson 2024-11-25 15:50:29 -06:00
parent d311ee238c
commit 7358c1fe67
3 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
fpga/zsbl/spi.c
View File

@ -31,7 +31,7 @@
uint8_t spi_txrx(uint8_t byte) { uint8_t spi_txrx(uint8_t byte) {
spi_sendbyte(byte); spi_sendbyte(byte);
waittx(); waitrx();
return spi_readbyte(); return spi_readbyte();
} }

2
fpga/zsbl/spi.h
View File

@ -106,7 +106,7 @@ static inline void waittx() {
} }
static inline void waitrx() { static inline void waitrx() {
while(read_reg(SPI_IP) & 2) {} while(!(read_reg(SPI_IP) & 2)) {}
} }
static inline uint8_t spi_readbyte() { static inline uint8_t spi_readbyte() {

2
src/uncore/spi_fifo.sv
View File

@ -26,7 +26,7 @@ module spi_fifo #(parameter M=3, N=8)( // 2^M entries of N bits
assign rdata = mem[raddr]; assign rdata = mem[raddr];
always_ff @(posedge PCLK) always_ff @(posedge PCLK)
if (winc & ~wfull) mem[waddr] <= wdata; if (winc & wen & ~wfull) mem[waddr] <= wdata;
// write and read are enabled // write and read are enabled
always_ff @(posedge PCLK) always_ff @(posedge PCLK)