From f37bae1062bb559bfeb8c25328bc4218d79ec438 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 29 Jan 2023 11:33:54 -0800 Subject: [PATCH 01/12] Converted rv32ic to rv32imc --- pipelined/config/rv32gc/wally-config.vh | 2 +- pipelined/config/{rv32ic => rv32imc}/wally-config.vh | 2 +- pipelined/regression/lint-wally | 2 +- pipelined/regression/regression-wally | 10 +++++----- pipelined/regression/wally-pipelined-batch.do | 4 ++-- synthDC/wallySynth.py | 6 +++--- 6 files changed, 13 insertions(+), 13 deletions(-) rename pipelined/config/{rv32ic => rv32imc}/wally-config.vh (98%) diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index ef98b0028..1be6b25b4 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -68,7 +68,7 @@ // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 `define IDIV_BITSPERCYCLE 4 -`define IDIV_ON_FPU 0 +`define IDIV_ON_FPU 1 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 16 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32imc/wally-config.vh similarity index 98% rename from pipelined/config/rv32ic/wally-config.vh rename to pipelined/config/rv32imc/wally-config.vh index a80c00e38..5b03d2d58 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32imc/wally-config.vh @@ -37,7 +37,7 @@ // IEEE 754 compliance `define IEEE754 0 -`define MISA (32'h00000104 | 1 << 20 | 1 << 18 ) +`define MISA (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 diff --git a/pipelined/regression/lint-wally b/pipelined/regression/lint-wally index 000b63402..4ff93af60 100755 --- a/pipelined/regression/lint-wally +++ b/pipelined/regression/lint-wally @@ -5,7 +5,7 @@ export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do +for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do #for config in rv64gc; do echo "$config linting..." if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index 7398d7cec..f99906284 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -94,13 +94,13 @@ for test in tests32gc: grepstr="All tests ran without failures") configs.append(tc) -tests32icimperas = ["imperas32i", "imperas32c"] # unused -tests32ic = ["arch32i", "arch32c", "wally32periph"] -for test in tests32ic: +tests32imcimperas = ["imperas32i", "imperas32c"] # unused +tests32imc = ["arch32i", "arch32c", "arch32m", "wally32periph"] +for test in tests32imc: tc = TestCase( name=test, - variant="rv32ic", - cmd="vsim > {} -c < {} -c < -# Example: do wally-pipelined-batch.do rv32ic imperas-32i +# Example: do wally-pipelined-batch.do rv32imc imperas-32i # Use this wally-pipelined-batch.do file to run this example. # Either bring up ModelSim and type the following at the "ModelSim>" prompt: @@ -37,7 +37,7 @@ if {$2 eq "ahb"} { # because vsim will run vopt # default to config/rv64ic, but allow this to be overridden at the command line. For example: -# do wally-pipelined-batch.do ../config/rv32ic rv32ic +# do wally-pipelined-batch.do ../config/rv32imc rv32imc if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 6b10f2e8b..9ac3a995d 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -17,7 +17,7 @@ def mask(command): if __name__ == '__main__': techs = ['sky90', 'tsmc28'] - allConfigs = ['rv32gc', 'rv32ic', 'rv64gc', 'rv64ic', 'rv32e', 'rv32i', 'rv64i'] + allConfigs = ['rv32gc', 'rv32imc', 'rv64gc', 'rv64imc', 'rv32e', 'rv32i', 'rv64i'] freqVaryPct = [-20, -12, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20] pool = Pool() @@ -25,7 +25,7 @@ if __name__ == '__main__': parser = argparse.ArgumentParser() parser.add_argument("-s", "--freqsweep", type=int, help = "Synthesize wally with target frequencies at given MHz and +/- 2, 4, 6, 8 %%") - parser.add_argument("-c", "--configsweep", action='store_true', help = "Synthesize wally with configurations 32e, 32ic, 64ic, 32gc, and 64gc") + parser.add_argument("-c", "--configsweep", action='store_true', help = "Synthesize wally with configurations 32e, 32imc, 64ic, 32gc, and 64gc") parser.add_argument("-f", "--featuresweep", action='store_true', help = "Synthesize wally with features turned off progressively to visualize critical path") parser.add_argument("-v", "--version", choices=allConfigs, help = "Configuration of wally") @@ -47,7 +47,7 @@ if __name__ == '__main__': for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep runSynth(config, mod, tech, freq, maxopt) if args.configsweep: - for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32ic', 'rv32e']: #configs + for config in ['rv32i', 'rv64gc', 'rv64i', 'rv32gc', 'rv32imc', 'rv32e']: #configs runSynth(config, mod, tech, freq, maxopt) if args.featuresweep: config = args.version if args.version else 'rv64gc' From d6b0a8f9a1444c5d4b6065196e1eb1a606305be7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 29 Jan 2023 11:34:35 -0800 Subject: [PATCH 02/12] Removed unused wally-harvard.do script --- pipelined/regression/wally-harvard.do | 56 --------------------------- 1 file changed, 56 deletions(-) delete mode 100644 pipelined/regression/wally-harvard.do diff --git a/pipelined/regression/wally-harvard.do b/pipelined/regression/wally-harvard.do deleted file mode 100644 index e6050d2c7..000000000 --- a/pipelined/regression/wally-harvard.do +++ /dev/null @@ -1,56 +0,0 @@ -# wally-pipelined.do -# -# Modification by Oklahoma State University & Harvey Mudd College -# Use with Testbench -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" - -# Use this wally-pipelined.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt - -# default to config/rv64ic, but allow this to be overridden at the command line. For example: -# do wally-pipelined.do ../config/rv32ic -#switch $argc { -# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583} -# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583} -#} -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-harvard.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -vopt +acc work.testbench -G TEST=$2 -o workopt -vsim workopt - -view wave --- display input and output signals as hexidecimal values -#do ./wave-dos/peripheral-waves.do -add log -recursive /* -do wave.do - --- Run the Simulation -#run 3600 -run -all -#quit -#noview ../testbench/testbench-imperas.sv -noview ../testbench/testbench.sv -view wave From a099cbb45bfd1a170514dbd420b06c6e4a008518 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 29 Jan 2023 11:35:17 -0800 Subject: [PATCH 03/12] Fixed configuration of ram to use macro when depth is corret --- pipelined/src/generic/mem/ram1p1rwbe.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv index 47b3f1fe7..6ab6590fd 100644 --- a/pipelined/src/generic/mem/ram1p1rwbe.sv +++ b/pipelined/src/generic/mem/ram1p1rwbe.sv @@ -49,7 +49,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( // *************************************************************************** // TRUE SRAM macro // *************************************************************************** - if (`USE_SRAM == 1 && WIDTH == 128 && `XLEN == 64) begin + if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 64) begin genvar index; // 64 x 128-bit SRAM logic [WIDTH-1:0] BitWriteMask; @@ -59,7 +59,7 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); - end else if (`USE_SRAM == 1 && WIDTH == 44 && `XLEN == 64) begin + end else if (`USE_SRAM == 1 && WIDTH == 44 && DEPTH == 64) begin genvar index; // 64 x 44-bit SRAM logic [WIDTH-1:0] BitWriteMask; From 2a20d71a1279610608c29a266bfc39cbfc54ca43 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 29 Jan 2023 11:40:08 -0800 Subject: [PATCH 04/12] Missing files related to rv32imc config --- .gitignore | 31 ------------------------------- synthDC/Makefile | 2 +- 2 files changed, 1 insertion(+), 32 deletions(-) diff --git a/.gitignore b/.gitignore index 609ef1487..3a8e8be91 100644 --- a/.gitignore +++ b/.gitignore @@ -81,37 +81,6 @@ synthDC/runArchive synthDC/hdl /pipelined/regression/power.saif tests/fp/vectors/*.tv -# Temporary configs produced for synthesis -pipelined/config/rv32e_FPUoff -pipelined/config/rv32e_PMP0 -pipelined/config/rv32e_PMP16 -pipelined/config/rv32e_noMulDiv -pipelined/config/rv32e_noPriv -pipelined/config/rv32e_orig -pipelined/config/rv32gc_FPUoff -pipelined/config/rv32gc_PMP0 -pipelined/config/rv32gc_PMP16 -pipelined/config/rv32gc_noMulDiv -pipelined/config/rv32gc_noPriv -pipelined/config/rv32gc_orig -pipelined/config/rv32ic_FPUoff -pipelined/config/rv32ic_PMP0 -pipelined/config/rv32ic_PMP16 -pipelined/config/rv32ic_noMulDiv -pipelined/config/rv32ic_noPriv -pipelined/config/rv32ic_orig -pipelined/config/rv64gc_FPUoff -pipelined/config/rv64gc_PMP0 -pipelined/config/rv64gc_PMP16 -pipelined/config/rv64gc_noMulDiv -pipelined/config/rv64gc_noPriv -pipelined/config/rv64gc_orig -pipelined/config/rv64ic_FPUoff -pipelined/config/rv64ic_PMP0 -pipelined/config/rv64ic_PMP16 -pipelined/config/rv64ic_noMulDiv -pipelined/config/rv64ic_noPriv -pipelined/config/rv64ic_orig synthDC/Summary.csv pipelined/srt/exptestgen pipelined/srt/testgen diff --git a/synthDC/Makefile b/synthDC/Makefile index 81d982251..8ad8b4389 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -45,7 +45,7 @@ default: @echo "Use wallySynth.py to run a concurrent sweep " -DIRS32 = rv32e rv32gc rv32ic rv32i +DIRS32 = rv32e rv32gc rv32imc rv32i DIRS64 = rv64i rv64gc DIRS = $(DIRS32) $(DIRS64) From db07c6618b18dbcc8ecaaded303175bdd3c9e534 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 29 Jan 2023 14:19:24 -0800 Subject: [PATCH 05/12] Removed unused TESTSBP parameter --- pipelined/config/buildroot/wally-config.vh | 1 - pipelined/config/fpga/wally-config.vh | 1 - pipelined/config/rv32e/wally-config.vh | 1 - pipelined/config/rv32gc/wally-config.vh | 1 - pipelined/config/rv32i/wally-config.vh | 1 - pipelined/config/rv32imc/wally-config.vh | 1 - pipelined/config/rv64fpquad/wally-config.vh | 1 - pipelined/config/rv64gc/wally-config.vh | 1 - pipelined/config/rv64i/wally-config.vh | 1 - pipelined/src/wally/cvw.sv | 1 - 10 files changed, 10 deletions(-) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index f34874dc3..34056ea74 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -130,7 +130,6 @@ `define BPRED_SUPPORTED 1 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index d23ef9684..007f233f5 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -139,7 +139,6 @@ `define BPRED_SUPPORTED 1 `define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 -`define TESTSBP 1 `define BPRED_SIZE 10 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 84082fdc8..8f779cb83 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -134,7 +134,6 @@ `define BPRED_SUPPORTED 0 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 1be6b25b4..9814a79ee 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -133,7 +133,6 @@ `define BPRED_SUPPORTED 1 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 1cc0c5b32..448f05aef 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -134,7 +134,6 @@ `define BPRED_SUPPORTED 0 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32imc/wally-config.vh b/pipelined/config/rv32imc/wally-config.vh index 5b03d2d58..db0e974ad 100644 --- a/pipelined/config/rv32imc/wally-config.vh +++ b/pipelined/config/rv32imc/wally-config.vh @@ -133,7 +133,6 @@ `define BPRED_SUPPORTED 0 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index 649956fbe..528b8586d 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -136,7 +136,6 @@ `define BPRED_SUPPORTED 1 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 01b245b3d..d0877c075 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -138,7 +138,6 @@ //`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 `define BPRED_TYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 //`define BPRED_TYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 -`define TESTSBP 0 `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index b4621d31d..0c78e774c 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -136,7 +136,6 @@ `define BPRED_SUPPORTED 0 `define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE -`define TESTSBP 0 `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/src/wally/cvw.sv b/pipelined/src/wally/cvw.sv index 0a804c9a3..c4541b698 100644 --- a/pipelined/src/wally/cvw.sv +++ b/pipelined/src/wally/cvw.sv @@ -100,7 +100,6 @@ package cvw; parameter PLIC_UART_ID = `PLIC_UART_ID; parameter BPRED_SUPPORTED = `BPRED_SUPPORTED; parameter BPRED_TYPE = `BPRED_TYPE; - parameter TESTSBP = `TESTSBP; parameter BPRED_SIZE = `BPRED_SIZE; parameter HPTW_WRITES_SUPPORTED = `HPTW_WRITES_SUPPORTED; // parameter = `; From 327303e2e27f6b532a31aa4d8479cf7788ce1ca4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 29 Jan 2023 15:55:37 -0800 Subject: [PATCH 06/12] Moved shared constants into per-processor config and removed wally-constants --- pipelined/config/buildroot/wally-config.vh | 13 ++ pipelined/config/fpga/wally-config.vh | 13 ++ pipelined/config/rv32e/wally-config.vh | 13 ++ pipelined/config/rv32gc/wally-config.vh | 13 ++ pipelined/config/rv32i/wally-config.vh | 13 ++ pipelined/config/rv32imc/wally-config.vh | 13 ++ pipelined/config/rv64fpquad/wally-config.vh | 13 ++ pipelined/config/rv64gc/wally-config.vh | 13 ++ pipelined/config/rv64i/wally-config.vh | 13 ++ pipelined/config/shared/wally-constants.vh | 148 -------------------- pipelined/config/shared/wally-shared.vh | 125 +++++++++++++++-- pipelined/testbench/testbench.sv | 2 +- 12 files changed, 231 insertions(+), 161 deletions(-) delete mode 100644 pipelined/config/shared/wally-constants.vh diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 34056ea74..783b9d91b 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -134,3 +134,16 @@ `define HPTW_WRITES_SUPPORTED 1 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 007f233f5..c4d9cf629 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -143,3 +143,16 @@ `define HPTW_WRITES_SUPPORTED 1 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 8f779cb83..24242b384 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -137,3 +137,16 @@ `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 69ea4b5b2..089a9ada4 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -136,3 +136,16 @@ `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 448f05aef..0a081b415 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -137,3 +137,16 @@ `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/rv32imc/wally-config.vh b/pipelined/config/rv32imc/wally-config.vh index 727a50d57..b4293dcc6 100644 --- a/pipelined/config/rv32imc/wally-config.vh +++ b/pipelined/config/rv32imc/wally-config.vh @@ -136,3 +136,16 @@ `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index 528b8586d..3757175a3 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -139,3 +139,16 @@ `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 818030f12..c3dd87295 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -139,3 +139,16 @@ `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index 0c78e774c..90d7b4045 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -139,3 +139,16 @@ `define BPRED_SIZE 10 `define HPTW_WRITES_SUPPORTED 0 + +// FPU division architecture +`define RADIX 32'h4 +`define DIVCOPIES 32'h4 + +// bit manipulation +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 + +// Memory synthesis configuration +`define USE_SRAM 0 diff --git a/pipelined/config/shared/wally-constants.vh b/pipelined/config/shared/wally-constants.vh deleted file mode 100644 index 0999fc207..000000000 --- a/pipelined/config/shared/wally-constants.vh +++ /dev/null @@ -1,148 +0,0 @@ -////////////////////////////////////////// -// wally-constants.vh -// -// Written: tfleming@hmc.edu 4 March 2021 -// Modified: Kmacsaigoren@hmc.edu 31 May 2021 -// Added constants for checking sv mode and changed existing constants to accomodate -// both sv48 and sv39 -// -// Purpose: Specify constants nexessary for different memory virtualization modes. -// These are specific to sv49, defined in section 4.5 of the privileged spec. -// However, despite different constants for different modes, the hardware helps distinguish between -// each mode. -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// constants defining different privilege modes -// defined in Table 1.1 of the privileged spec -`define M_MODE (2'b11) -`define S_MODE (2'b01) -`define U_MODE (2'b00) - -// Virtual Memory Constants -`define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9) -`define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS)) -`define PPN_BITS (`XLEN==32 ? 22 : 44) -`define PA_BITS (`XLEN==32 ? 34 : 56) -`define SVMODE_BITS (`XLEN==32 ? 1 : 4) -`define ASID_BASE (`XLEN==32 ? 22 : 44) -`define ASID_BITS (`XLEN==32 ? 9 : 16) - -// constants to check SATP_MODE against -// defined in Table 4.3 of the privileged spec -`define NO_TRANSLATE 0 -`define SV32 1 -`define SV39 8 -`define SV48 9 - -// macros to define supported modes -`define A_SUPPORTED ((`MISA >> 0) % 2 == 1) -`define B_SUPPORTED ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)) // not based on MISA -`define C_SUPPORTED ((`MISA >> 2) % 2 == 1) -`define D_SUPPORTED ((`MISA >> 3) % 2 == 1) -`define E_SUPPORTED ((`MISA >> 4) % 2 == 1) -`define F_SUPPORTED ((`MISA >> 5) % 2 == 1) -`define I_SUPPORTED ((`MISA >> 8) % 2 == 1) -`define M_SUPPORTED ((`MISA >> 12) % 2 == 1) -`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1) -`define S_SUPPORTED ((`MISA >> 18) % 2 == 1) -`define U_SUPPORTED ((`MISA >> 20) % 2 == 1) -// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 - -// logarithm of XLEN, used for number of index bits to select -`define LOG_XLEN (`XLEN == 32 ? 5 : 6) - -// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries) -`define PMPCFG_ENTRIES (`PMP_ENTRIES/8) - -// Floating point constants for Quad, Double, Single, and Half precisions -`define Q_LEN 32'd128 -`define Q_NE 32'd15 -`define Q_NF 32'd112 -`define Q_BIAS 32'd16383 -`define Q_FMT 2'd3 -`define D_LEN 32'd64 -`define D_NE 32'd11 -`define D_NF 32'd52 -`define D_BIAS 32'd1023 -`define D_FMT 2'd1 -`define S_LEN 32'd32 -`define S_NE 32'd8 -`define S_NF 32'd23 -`define S_BIAS 32'd127 -`define S_FMT 2'd0 -`define H_LEN 32'd16 -`define H_NE 32'd5 -`define H_NF 32'd10 -`define H_BIAS 32'd15 -`define H_FMT 2'd2 - -// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits -`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `S_LEN) -`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `S_NE) -`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `S_NF) -`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : 2'd0) -`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS) -/* Delete once tested dh 10/10/22 - -`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN) -`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) -`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) -`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2) -`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)*/ - -// Floating point constants needed for FPU paramerterization -`define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED)) -`define FMTBITS ((32)'(`FPSIZES>=3)+1) -`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN) -`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE) -`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF) -`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2) -`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS) -`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN) -`define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE) -`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF) -`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2) -`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS) - -// largest length in IEU/FPU -`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF)) -`define LLEN ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN)) -`define LOGCVTLEN $unsigned($clog2(`CVTLEN+1)) -`define NORMSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6))) -`define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ)) -`define CORRSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4))) - -// division constants - -`define DIVN (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input -`define LOGR ($clog2(`RADIX)) // r = log(R) -`define RK (`LOGR*`DIVCOPIES) // r*k used for intdiv preproc -`define LOGRK ($clog2(`RK)) // log2(r*k) -`define FPDUR ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4)) -`define DURLEN ($clog2(`FPDUR+1)) -`define DIVb (`FPDUR*`LOGR*`DIVCOPIES-1) // canonical fdiv size (b) -`define DIVBLEN ($clog2(`DIVb+1)-1) -`define DIVa (`DIVb+1-`XLEN) // used for idiv on fpu - -// Disable spurious Verilator warnings - -/* verilator lint_off STMTDLY */ -/* verilator lint_off ASSIGNDLY */ -/* verilator lint_off PINCONNECTEMPTY */ diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index 4e43c7217..507388f7f 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -23,19 +23,120 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// +// constants defining different privilege modes +// defined in Table 1.1 of the privileged spec +`define M_MODE (2'b11) +`define S_MODE (2'b01) +`define U_MODE (2'b00) + +// Virtual Memory Constants +`define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9) +`define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS)) +`define PPN_BITS (`XLEN==32 ? 22 : 44) +`define PA_BITS (`XLEN==32 ? 34 : 56) +`define SVMODE_BITS (`XLEN==32 ? 1 : 4) +`define ASID_BASE (`XLEN==32 ? 22 : 44) +`define ASID_BITS (`XLEN==32 ? 9 : 16) + +// constants to check SATP_MODE against +// defined in Table 4.3 of the privileged spec +`define NO_TRANSLATE 0 +`define SV32 1 +`define SV39 8 +`define SV48 9 + +// macros to define supported modes +`define A_SUPPORTED ((`MISA >> 0) % 2 == 1) +`define B_SUPPORTED ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)) // not based on MISA +`define C_SUPPORTED ((`MISA >> 2) % 2 == 1) +`define D_SUPPORTED ((`MISA >> 3) % 2 == 1) +`define E_SUPPORTED ((`MISA >> 4) % 2 == 1) +`define F_SUPPORTED ((`MISA >> 5) % 2 == 1) +`define I_SUPPORTED ((`MISA >> 8) % 2 == 1) +`define M_SUPPORTED ((`MISA >> 12) % 2 == 1) +`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1) +`define S_SUPPORTED ((`MISA >> 18) % 2 == 1) +`define U_SUPPORTED ((`MISA >> 20) % 2 == 1) +// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 + +// logarithm of XLEN, used for number of index bits to select +`define LOG_XLEN (`XLEN == 32 ? 5 : 6) + +// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries) +`define PMPCFG_ENTRIES (`PMP_ENTRIES/8) + +// Floating point constants for Quad, Double, Single, and Half precisions +`define Q_LEN 32'd128 +`define Q_NE 32'd15 +`define Q_NF 32'd112 +`define Q_BIAS 32'd16383 +`define Q_FMT 2'd3 +`define D_LEN 32'd64 +`define D_NE 32'd11 +`define D_NF 32'd52 +`define D_BIAS 32'd1023 +`define D_FMT 2'd1 +`define S_LEN 32'd32 +`define S_NE 32'd8 +`define S_NF 32'd23 +`define S_BIAS 32'd127 +`define S_FMT 2'd0 +`define H_LEN 32'd16 +`define H_NE 32'd5 +`define H_NF 32'd10 +`define H_BIAS 32'd15 +`define H_FMT 2'd2 + +// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits +`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `S_LEN) +`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `S_NE) +`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `S_NF) +`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : 2'd0) +`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS) +/* Delete once tested dh 10/10/22 + +`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN) +`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) +`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) +`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2) +`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)*/ + +// Floating point constants needed for FPU paramerterization +`define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED)) +`define FMTBITS ((32)'(`FPSIZES>=3)+1) +`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN) +`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE) +`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF) +`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2) +`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS) +`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN) +`define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE) +`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF) +`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2) +`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS) + +// largest length in IEU/FPU +`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF)) +`define LLEN ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN)) +`define LOGCVTLEN $unsigned($clog2(`CVTLEN+1)) +`define NORMSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6))) +`define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ)) +`define CORRSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4))) + // division constants -`define RADIX 32'h4 -`define DIVCOPIES 32'h4 -// eventually move to each config -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 +`define DIVN (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input +`define LOGR ($clog2(`RADIX)) // r = log(R) +`define RK (`LOGR*`DIVCOPIES) // r*k used for intdiv preproc +`define LOGRK ($clog2(`RK)) // log2(r*k) +`define FPDUR ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4)) +`define DURLEN ($clog2(`FPDUR+1)) +`define DIVb (`FPDUR*`LOGR*`DIVCOPIES-1) // canonical fdiv size (b) +`define DIVBLEN ($clog2(`DIVb+1)-1) +`define DIVa (`DIVb+1-`XLEN) // used for idiv on fpu -// Memory synthesis configuration -`define USE_SRAM 0 - -// shared constants -`include "wally-constants.vh" +// Disable spurious Verilator warnings +/* verilator lint_off STMTDLY */ +/* verilator lint_off ASSIGNDLY */ +/* verilator lint_off PINCONNECTEMPTY */ diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 0696367da..325f9c00a 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -543,7 +543,7 @@ module riscvassertions; assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF"); assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); - assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported"); + assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZICSR not supported"); assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses"); assert (`DCACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); From 4c75a90e39c90a932a7811f13da09c3a2b4c2743 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 29 Jan 2023 17:19:53 -0800 Subject: [PATCH 07/12] Moved WALLY-status-fp-enabled tests from a to priv suites --- pipelined/testbench/tests.vh | 70 +++--------------------------------- 1 file changed, 4 insertions(+), 66 deletions(-) diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index bbc82d9ad..1d094254e 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -94,47 +94,6 @@ string tvpaths[] = '{ "bd_sizeopt_speed/src/ud/ud", "bd_sizeopt_speed/src/wikisort/wikisort" }; - - // *** restore CSR tests from Imperas old - string extra64i[] = '{ - `MYIMPERASTEST, - "rv64i_m/I/WALLY-ADD", - "rv64i_m/I/WALLY-SUB", - "rv64i_m/I/WALLY-ADDI", - "rv64i_m/I/WALLY-ANDI", - "rv64i_m/I/WALLY-ORI", - "rv64i_m/I/WALLY-XORI", - "rv64i_m/I/WALLY-SLTI", - "rv64i_m/I/WALLY-SLTIU", - "rv64i_m/I/WALLY-SLLI", - "rv64i_m/I/WALLY-SRLI", - "rv64i_m/I/WALLY-SRAI", - "rv64i_m/I/WALLY-JAL", - "rv64i_m/I/WALLY-JALR", - "rv64i_m/I/WALLY-STORE", - "rv64i_m/I/WALLY-ADDIW", - "rv64i_m/I/WALLY-SLLIW", - "rv64i_m/I/WALLY-SRLIW", - "rv64i_m/I/WALLY-SRAIW", - "rv64i_m/I/WALLY-ADDW", - "rv64i_m/I/WALLY-SUBW", - "rv64i_m/I/WALLY-SLLW", - "rv64i_m/I/WALLY-SRLW", - "rv64i_m/I/WALLY-SRAW", - "rv64i_m/I/WALLY-BEQ", - "rv64i_m/I/WALLY-BNE", - "rv64i_m/I/WALLY-BLTU", - "rv64i_m/I/WALLY-BLT", - "rv64i_m/I/WALLY-BGE", - "rv64i_m/I/WALLY-BGEU", - "rv64i_m/I/WALLY-CSRRW", - "rv64i_m/I/WALLY-CSRRS", - "rv64i_m/I/WALLY-CSRRC", - "rv64i_m/I/WALLY-CSRRWI", - "rv64i_m/I/WALLY-CSRRSI", - "rv64i_m/I/WALLY-CSRRCI" - }; - string imperas32f[] = '{ `IMPERASTEST, @@ -875,40 +834,17 @@ string imperas32f[] = '{ "rv32i_m/I/XORI-01" }; - string imperas32p[] = '{ - `MYIMPERASTEST, - "rv32p/WALLY-MSTATUS", - "rv32p/WALLY-MCAUSE", - "rv32p/WALLY-SCAUSE", - "rv32p/WALLY-MEPC", - "rv32p/WALLY-SEPC", - "rv32p/WALLY-MTVAL", - "rv32p/WALLY-STVAL", - "rv32p/WALLY-MARCHID", - "rv32p/WALLY-MIMPID", - "rv32p/WALLY-MHARTID", - "rv32p/WALLY-MVENDORID", - "rv32p/WALLY-MTVEC", - "rv32p/WALLY-STVEC", - "rv32p/WALLY-MIE", - "rv32p/WALLY-MEDELEG", - "rv32p/WALLY-IP", - "rv32p/WALLY-CSR-PERMISSIONS-M", - "rv32p/WALLY-CSR-PERMISSIONS-S" - }; string wally64a[] = '{ `WALLYTEST, "rv64i_m/privilege/src/WALLY-amo-01.S", - "rv64i_m/privilege/src/WALLY-lrsc-01.S", - "rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S" + "rv64i_m/privilege/src/WALLY-lrsc-01.S" }; string wally32a[] = '{ `WALLYTEST, "rv32i_m/privilege/src/WALLY-amo-01.S", - "rv32i_m/privilege/src/WALLY-lrsc-01.S", - "rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S" + "rv32i_m/privilege/src/WALLY-lrsc-01.S" }; string arch64priv[] = '{ @@ -1825,6 +1761,7 @@ string imperas32f[] = '{ "rv64i_m/privilege/src/WALLY-status-sie-01.S", "rv64i_m/privilege/src/WALLY-status-tw-01.S", "rv64i_m/privilege/src/WALLY-status-tvm-01.S", + "rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S", "rv64i_m/privilege/src/WALLY-stvec-01.S", "rv64i_m/privilege/src/WALLY-trap-01.S", "rv64i_m/privilege/src/WALLY-trap-s-01.S", @@ -1912,6 +1849,7 @@ string imperas32f[] = '{ "rv32i_m/privilege/src/WALLY-status-sie-01.S", "rv32i_m/privilege/src/WALLY-status-tw-01.S", "rv32i_m/privilege/src/WALLY-status-tvm-01.S", + "rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S", "rv32i_m/privilege/src/WALLY-stvec-01.S", "rv32i_m/privilege/src/WALLY-trap-01.S", "rv32i_m/privilege/src/WALLY-trap-s-01.S", From 0c20ac010c8ec31094cc26ac0041ea4ff37c8918 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 30 Jan 2023 11:00:41 -0800 Subject: [PATCH 08/12] Updated Questa to 2022.4_2. --- setup.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/setup.sh b/setup.sh index 27ed893db..d54ae7bd4 100755 --- a/setup.sh +++ b/setup.sh @@ -13,9 +13,9 @@ echo \$WALLY set to ${WALLY} # License servers and commercial CAD tool paths # Must edit these based on your local environment. Ask your sysadmin. -export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server +export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server -export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin # Change this for your path to Questa +export QUESTAPATH=/cad/mentor/questa_sim-2022.4_2/questasim/bin # Change this for your path to Questa export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler # Path to RISC-V Tools From 49e45f45b7d97438902e5f1808a6128c57f16625 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 30 Jan 2023 12:48:52 -0800 Subject: [PATCH 09/12] Moved out version of wally using package because synthesis isn't working yet --- .../src/wally/wallypipelinedcore.sv => wallypipelinedcore.sv | 0 pipelined/src/wally/wallypipelinedsoc.sv => wallypipelinedsoc.sv | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename pipelined/src/wally/wallypipelinedcore.sv => wallypipelinedcore.sv (100%) rename pipelined/src/wally/wallypipelinedsoc.sv => wallypipelinedsoc.sv (100%) diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/wallypipelinedcore.sv similarity index 100% rename from pipelined/src/wally/wallypipelinedcore.sv rename to wallypipelinedcore.sv diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/wallypipelinedsoc.sv similarity index 100% rename from pipelined/src/wally/wallypipelinedsoc.sv rename to wallypipelinedsoc.sv From 6777fd9b55994d0f4fa4c893d047a597a804ed19 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 30 Jan 2023 12:54:40 -0800 Subject: [PATCH 10/12] Restored top-level modules without import statements --- pipelined/src/wally/wallypipelinedcore.sv | 361 ++++++++++++++++++++++ pipelined/src/wally/wallypipelinedsoc.sv | 93 ++++++ 2 files changed, 454 insertions(+) create mode 100644 pipelined/src/wally/wallypipelinedcore.sv create mode 100644 pipelined/src/wally/wallypipelinedsoc.sv diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv new file mode 100644 index 000000000..2df96d1fb --- /dev/null +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -0,0 +1,361 @@ +/////////////////////////////////////////// +// wallypipelinedcore.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: Pipelined RISC-V Processor +// +// Documentation: RISC-V System on Chip Design (Figure 4.1) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +//import cvw::*; // global CORE-V-Wally parameters +`include "wally-config.vh" + +module wallypipelinedcore ( + input logic clk, reset, + // Privileged + input logic MTimerInt, MExtInt, SExtInt, MSwInt, + input logic [63:0] MTIME_CLINT, + // Bus Interface + input logic [`AHBW-1:0] HRDATA, + input logic HREADY, HRESP, + output logic HCLK, HRESETn, + output logic [`PA_BITS-1:0] HADDR, + output logic [`AHBW-1:0] HWDATA, + output logic [`XLEN/8-1:0] HWSTRB, + output logic HWRITE, + output logic [2:0] HSIZE, + output logic [2:0] HBURST, + output logic [3:0] HPROT, + output logic [1:0] HTRANS, + output logic HMASTLOCK +); + + logic StallF, StallD, StallE, StallM, StallW; + logic FlushD, FlushE, FlushM, FlushW; + logic RetM; + logic TrapM; + + // signals that must connect through DP + logic IntDivE, W64E; + logic CSRReadM, CSRWriteM, PrivilegedM; + logic [1:0] AtomicM; + logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; + logic [`XLEN-1:0] SrcAM; + logic [2:0] Funct3E; + logic [31:0] InstrD; + logic [31:0] InstrM; + logic [`XLEN-1:0] PCFSpill, PCE, PCLinkE; + logic [`XLEN-1:0] PCM; + logic [`XLEN-1:0] CSRReadValW, MDUResultW; + logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F; + logic [1:0] MemRWM; + logic InstrValidM; + logic InstrMisalignedFaultM; + logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD; + logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM; + logic LoadMisalignedFaultM, LoadAccessFaultM; + logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM; + logic InvalidateICacheM, FlushDCacheM; + logic PCSrcE; + logic CSRWriteFenceM; + logic DivBusyE; + logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; + logic SquashSCW; + + // floating point unit signals + logic [2:0] FRM_REGW; + logic [4:0] RdE, RdM, RdW; + logic FPUStallD; + logic FWriteIntE; + logic [`FLEN-1:0] FWriteDataM; + logic [`XLEN-1:0] FIntResM; + logic [`XLEN-1:0] FCvtIntResW; + logic FCvtIntW; + logic FDivBusyE; + logic IllegalFPUInstrM; + logic FRegWriteM; + logic FCvtIntStallD; + logic FpLoadStoreM; + logic [4:0] SetFflagsM; + logic [`XLEN-1:0] FIntDivResultW; + + // memory management unit signals + logic ITLBWriteF; + logic ITLBMissF; + logic [`XLEN-1:0] SATP_REGW; + logic STATUS_MXR, STATUS_SUM, STATUS_MPRV; + logic [1:0] STATUS_MPP, STATUS_FS; + logic [1:0] PrivilegeModeW; + logic [`XLEN-1:0] PTE; + logic [1:0] PageType; + logic sfencevmaM, WFIStallM; + logic SelHPTW; + + // PMA checker signals + var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]; + var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0]; + + // IMem stalls + logic IFUStallF; + logic LSUStallM; + + // cpu lsu interface + logic [2:0] Funct3M; + logic [`XLEN-1:0] IEUAdrE; + logic [`XLEN-1:0] WriteDataM; + logic [`XLEN-1:0] IEUAdrM; + logic [`LLEN-1:0] ReadDataW; + logic CommittedM; + + // AHB ifu interface + logic [`PA_BITS-1:0] IFUHADDR; + logic [2:0] IFUHBURST; + logic [1:0] IFUHTRANS; + logic [2:0] IFUHSIZE; + logic IFUHWRITE; + logic IFUHREADY; + + // AHB LSU interface + logic [`PA_BITS-1:0] LSUHADDR; + logic [`XLEN-1:0] LSUHWDATA; + logic [`XLEN/8-1:0] LSUHWSTRB; + logic LSUHWRITE; + logic LSUHREADY; + + logic BPPredWrongE, BPPredWrongM; + logic DirPredictionWrongM; + logic BTBPredPCWrongM; + logic RASPredPCWrongM; + logic PredictionInstrClassWrongM; + logic [3:0] InstrClassM; + logic InstrAccessFaultF, HPTWInstrAccessFaultM; + logic [2:0] LSUHSIZE; + logic [2:0] LSUHBURST; + logic [1:0] LSUHTRANS; + + logic DCacheMiss; + logic DCacheAccess; + logic ICacheMiss; + logic ICacheAccess; + logic BreakpointFaultM, EcallFaultM; + logic InstrDAPageFaultF; + logic BigEndianM; + logic FCvtIntE; + logic CommittedF; + logic JumpOrTakenBranchM; + + // instruction fetch unit: PC, branch prediction, instruction cache + ifu ifu(.clk, .reset, + .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + // Fetch + .HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F, + .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE, + .ICacheAccess, .ICacheMiss, + // Execute + .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, .BPPredWrongM, + // Mem + .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM, + .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM, + .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, + // Faults out + .IllegalBaseInstrFaultD, .InstrPageFaultF, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM, + // mmu management + .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, + .STATUS_MPP, .ITLBWriteF, .sfencevmaM, .ITLBMissF, + // pmp/pma (inside mmu) signals. + .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF, .InstrDAPageFaultF); + + // integer execution unit: integer register file, datapath and controller + ieu ieu(.clk, .reset, + // Decode Stage interface + .InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, + // Execute Stage interface + .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E, + .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, + // Memory stage interface + .SquashSCW, // from LSU + .MemRWM, // read/write control goes to LSU + .AtomicM, // atomic control goes to LSU + .WriteDataM, // Write data to LSU + .Funct3M, // size and signedness to LSU + .SrcAM, // to privilege and fpu + .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, + // Writeback stage + .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]), + .InstrValidM, .FCvtIntResW, .FCvtIntW, + // hazards + .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE, + .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .StoreStallD); + + lsu lsu( + .clk, .reset, .StallM, .FlushM, .StallW, .FlushW, + // CPU interface + .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM, + .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW, + .FpLoadStoreM, .FWriteDataM, .IEUAdrE, .IEUAdrM, .WriteDataM, + .ReadDataW, .FlushDCacheM, + // connected to ahb (all stay the same) + .LSUHADDR, .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, + .LSUHBURST, .LSUHTRANS, .LSUHWRITE, .LSUHREADY, + // connect to csr or privilege and stay the same. + .PrivilegeModeW, .BigEndianM, // connects to csr + .PMPCFG_ARRAY_REGW, // connects to csr + .PMPADDR_ARRAY_REGW, // connects to csr + // hptw keep i/o + .SATP_REGW, // from csr + .STATUS_MXR, // from csr + .STATUS_SUM, // from csr + .STATUS_MPRV, // from csr + .STATUS_MPP, // from csr + .sfencevmaM, // connects to privilege + .LoadPageFaultM, // connects to privilege + .StoreAmoPageFaultM, // connects to privilege + .LoadMisalignedFaultM, // connects to privilege + .LoadAccessFaultM, // connects to privilege + .HPTWInstrAccessFaultM, // connects to privilege + .StoreAmoMisalignedFaultM, // connects to privilege + .StoreAmoAccessFaultM, // connects to privilege + .InstrDAPageFaultF, + .PCFSpill, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, + .LSUStallM); + + if(`BUS_SUPPORTED) begin : ebu + ebu ebu(// IFU connections + .clk, .reset, + // IFU interface + .IFUHADDR, + .IFUHBURST, + .IFUHTRANS, + .IFUHREADY, + .IFUHSIZE, + // LSU interface + .LSUHADDR, + .LSUHWDATA, + .LSUHWSTRB, + .LSUHSIZE, + .LSUHBURST, + .LSUHTRANS, + .LSUHWRITE, + .LSUHREADY, + // BUS interface + .HREADY, .HRESP, .HCLK, .HRESETn, + .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, + .HPROT, .HTRANS, .HMASTLOCK); + end + + // global stall and flush control + hazard hzu( + .BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM, + .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD, + .LSUStallM, .IFUStallF, + .FCvtIntStallD, .FPUStallD, + .DivBusyE, .FDivBusyE, + .EcallFaultM, .BreakpointFaultM, + .WFIStallM, + // Stall & flush outputs + .StallF, .StallD, .StallE, .StallM, .StallW, + .FlushD, .FlushE, .FlushM, .FlushW); + + // privileged unit + if (`ZICSR_SUPPORTED) begin:priv + privileged priv( + .clk, .reset, + .FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW, + .CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PCNext2F, + .InstrM, .CSRReadValW, .UnalignedPCNextF, + .RetM, .TrapM, .sfencevmaM, + .InstrValidM, .CommittedM, .CommittedF, + .FRegWriteM, .LoadStallD, + .DirPredictionWrongM, .BTBPredPCWrongM, .BPPredWrongM, + .RASPredPCWrongM, .PredictionInstrClassWrongM, + .InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM, + .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, + .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, + .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, + .MTimerInt, .MExtInt, .SExtInt, .MSwInt, + .MTIME_CLINT, .IEUAdrM, .SetFflagsM, + .InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW, + .IllegalFPUInstrM, .PrivilegeModeW, .SATP_REGW, + .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, + .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, + .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM); + end else begin + assign CSRReadValW = 0; + assign UnalignedPCNextF = PCNext2F; + assign RetM = 0; + assign TrapM = 0; + assign WFIStallM = 0; + assign sfencevmaM = 0; + assign BigEndianM = 0; + end + + // multiply/divide unit + if (`M_SUPPORTED) begin:mdu + mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW, + .ForwardedSrcAE, .ForwardedSrcBE, + .Funct3E, .Funct3M, .IntDivE, .W64E, + .MDUResultW, .DivBusyE); + end else begin // no M instructions supported + assign MDUResultW = 0; + assign DivBusyE = 0; + end + + // floating point unit + if (`F_SUPPORTED) begin:fpu + fpu fpu( + .clk, .reset, + .FRM_REGW, // Rounding mode from CSR + .InstrD, // instruction from IFU + .ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory + .ForwardedSrcAE, // Integer input being processed (from IEU) + .StallE, .StallM, .StallW, // stall signals from HZU + .FlushE, .FlushM, .FlushW, // flush signals from HZU + .RdE, .RdM, .RdW, // which FP register to write to (from IEU) + .STATUS_FS, // is floating-point enabled? + .FRegWriteM, // FP register write enable + .FpLoadStoreM, + .ForwardedSrcBE, // Integer input for intdiv + .Funct3E, .Funct3M, .IntDivE, .W64E, // Integer flags and functions + .FPUStallD, // Stall the decode stage + .FWriteIntE, .FCvtIntE, // integer register write enable, conversion operation + .FWriteDataM, // Data to be written to memory + .FIntResM, // data to be written to integer register + .FCvtIntResW, // fp -> int conversion result to be stored in int register + .FCvtIntW, // fpu result selection + .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) + .IllegalFPUInstrM, // Is the instruction an illegal fpu instruction + .SetFflagsM, // FPU flags (to privileged unit) + .FIntDivResultW); + end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low + assign FPUStallD = 0; + assign FWriteIntE = 0; + assign FCvtIntE = 0; + assign FIntResM = 0; + assign FCvtIntW = 0; + assign FDivBusyE = 0; + assign IllegalFPUInstrM = 1; + assign SetFflagsM = 0; + assign FpLoadStoreM = 0; + end + +endmodule diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv new file mode 100644 index 000000000..e4c461571 --- /dev/null +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -0,0 +1,93 @@ +/////////////////////////////////////////// +// wally-pipelinedsoc.sv +// +// Written: David_Harris@hmc.edu 6 November 2020 +// Modified: +// +// Purpose: System on chip including pipelined processor and uncore memories/peripherals +// +// Documentation: RISC-V System on Chip Design (Figure 6.20) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +//import cvw::*; // global CORE-V-Wally parameters +`include "wally-config.vh" + +module wallypipelinedsoc ( + input logic clk, + input logic reset_ext, // external asynchronous reset pin + output logic reset, // reset synchronized to clk to prevent races on release + // AHB Interface + input logic [`AHBW-1:0] HRDATAEXT, + input logic HREADYEXT, HRESPEXT, + output logic HSELEXT, + // outputs to external memory, shared with uncore memory + output logic HCLK, HRESETn, + output logic [`PA_BITS-1:0] HADDR, + output logic [`AHBW-1:0] HWDATA, + output logic [`XLEN/8-1:0] HWSTRB, + output logic HWRITE, + output logic [2:0] HSIZE, + output logic [2:0] HBURST, + output logic [3:0] HPROT, + output logic [1:0] HTRANS, + output logic HMASTLOCK, + output logic HREADY, + // I/O Interface + input logic TIMECLK, // optional for CLINT MTIME counter + input logic [31:0] GPIOPinsIn, // inputs from GPIO + output logic [31:0] GPIOPinsOut, // output values for GPIO + output logic [31:0] GPIOPinsEn, // output enables for GPIO + input logic UARTSin, // UART serial data input + output logic UARTSout, // UART serial data output + input logic SDCCmdIn, // SDC Command input + output logic SDCCmdOut, // SDC Command output + output logic SDCCmdOE, // SDC Command output enable + input logic [3:0] SDCDatIn, // SDC data input + output logic SDCCLK // SDC clock +); + + // Uncore signals + logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore + logic HRESP; // response from AHB + logic MTimerInt, MSwInt; // timer and software interrupts from CLINT + logic [63:0] MTIME_CLINT; // from CLINT to CSRs + logic MExtInt,SExtInt; // from PLIC + + // synchronize reset to SOC clock domain + synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); + + // instantiate processor and internal memories + wallypipelinedcore core(.clk, .reset, + .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, + .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, + .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK + ); + + // instantiate uncore if a bus interface exists + if (`BUS_SUPPORTED) begin : uncore + uncore uncore(.HCLK, .HRESETn, .TIMECLK, + .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, + .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, + .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, + .UARTSout, .MTIME_CLINT, + .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK); + end + +endmodule From a8f268e2a48214f4303dd3a9ccc6508390f6aa65 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 31 Jan 2023 04:37:23 -0800 Subject: [PATCH 11/12] Removed output delay in synthesis --- synthDC/scripts/synth.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 1d7281fcb..9fd86eccc 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -134,8 +134,8 @@ if {$tech == "sky130"} { # Set input/output delay if {$drive == "FLOP"} { - set_input_delay 0.1 -max -clock $my_clk $all_in_ex_clk - set_output_delay 0.1 -max -clock $my_clk [all_outputs] + set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk + set_output_delay 0.0 -max -clock $my_clk [all_outputs] } else { set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk set_output_delay 0.0 -max -clock $my_clk [all_outputs] From 625ca64474f0d5b618cfe511fdfc0c7c4bb031fa Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 31 Jan 2023 14:40:12 -0800 Subject: [PATCH 12/12] Removed student solution to fir --- examples/C/fir/fir.S | 35 ----------------------------------- 1 file changed, 35 deletions(-) delete mode 100644 examples/C/fir/fir.S diff --git a/examples/C/fir/fir.S b/examples/C/fir/fir.S deleted file mode 100644 index a96339ba7..000000000 --- a/examples/C/fir/fir.S +++ /dev/null @@ -1,35 +0,0 @@ -// fir.s -// mmasserfrye@hmc.edu 30 January 2022 -// FIR filter - -// a0 = N, a1 = M, a2 = &X, a3 = &c, a4 = &Y - -.global fir - -fir: - li t0, 0 # n = 0 = t0 - slli t6, a0, 3 # N*8 - slli t5, a1, 3 # M*8 - addi t4, t5, -8 # (M-1)*8 -for1: - bge t0, t6, end # exit outer for if n >= N - fmv.d.x f3, zero # sum = 0 = f3 - li t2, 0 # i = 0 = t2 - add t1, t4, t0 # [(M-1) + n]*8 -for2: - bge t2, t5, for1end # exit inner for if i >= M - sub t3, t1, t2 # [(M-1) + n - i]*8 - add t3, t3, a2 # t3 = offset + &X - fld f0, 0(t3) # X[n-i+(M-1)] - add t3, t2, a3 # t3 = offset + &c - fld f1, 0(t3) # c[i] - fmadd.d f3, f0, f1, f3 # sum += c[i]*X[n-i+(M-1)] - addi t2, t2, 8 # i++ - j for2 -for1end: - add t3, t0, a4 # t3 = offset + &Y - fsd f3, 0(t3) # Y[n] = sum - addi t0, t0, 8 # n++ - j for1 -end: - ret \ No newline at end of file