From 73261e7f89ca3c2109c75dadc39d8647cc01ccd1 Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Fri, 24 May 2024 16:34:33 -0500
Subject: [PATCH] More cleanup. Close to the simpliest it can be.

---
 src/rvvi/packetizer.sv | 3 +--
 testbench/testbench.sv | 4 +---
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/src/rvvi/packetizer.sv b/src/rvvi/packetizer.sv
index 49828ab38..b5a2cb695 100644
--- a/src/rvvi/packetizer.sv
+++ b/src/rvvi/packetizer.sv
@@ -34,7 +34,6 @@ module packetizer import cvw::*; #(parameter cvw_t P,
   input  logic m_axi_aclk, m_axi_aresetn,
   output logic RVVIStall,
   // axi 4 write address channel
-  input  logic  		   m_axi_awready,
   // axi 4 write data channel
   output logic [31:0]      m_axi_wdata,
   output logic [3:0] 	   m_axi_wstrb,
@@ -81,7 +80,7 @@ module packetizer import cvw::*; #(parameter cvw_t P,
   end
 
   assign RVVIStall = CurrState != STATE_RDY;
-  assign TransReady = m_axi_awready & m_axi_wready;
+  assign TransReady = m_axi_wready;
   assign WordCountEnable = (CurrState == STATE_RDY & valid) | (CurrState == STATE_TRANS & TransReady);
   assign WordCountReset = CurrState == STATE_RDY;
 
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 5bc47b1ba..3895a157a 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -597,7 +597,6 @@ module testbench;
 
     rvvisynth #(P, MAX_CSRS) rvvisynth(.clk, .reset, .valid, .rvvi);
 
-    logic                                             m_axi_awready;
     // axi 4 write data channel
     logic [31:0]                                      m_axi_wdata;
     logic [3:0]                                       m_axi_wstrb;
@@ -612,7 +611,7 @@ module testbench;
     logic                                             rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame;
 
     packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall,
-      .m_axi_awready, .m_axi_wdata, .m_axi_wstrb, .m_axi_wlast, .m_axi_wvalid, .m_axi_wready);
+      .m_axi_wdata, .m_axi_wstrb, .m_axi_wlast, .m_axi_wvalid, .m_axi_wready);
 
     eth_mac_mii_fifo #("GENERIC", "BUFG", 32) ethernet(.rst(reset), .logic_clk(clk), .logic_rst(reset),
       .tx_axis_tdata(m_axi_wdata), .tx_axis_tkeep(m_axi_wstrb), .tx_axis_tvalid(m_axi_wvalid), .tx_axis_tready(m_axi_wready),
@@ -635,7 +634,6 @@ module testbench;
       .cfg_ifg(8'd12), .cfg_tx_enable(1'b1), .cfg_rx_enable(1'b1)
       );
   
-  assign m_axi_awready = '1;
   end else begin
     assign RVVIStall = '0;
   end