From 730efefc4190c21cefe5d71d6fe4bf0a23654110 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 29 Dec 2023 16:18:30 -0600 Subject: [PATCH] Cleanup. --- src/cache/cache.sv | 11 +++++------ src/cache/cachefsm.sv | 7 ------- src/cache/cacheway.sv | 8 ++++---- src/lsu/dtim.sv | 2 +- 4 files changed, 10 insertions(+), 18 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index f0e396c45..c8f707904 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -93,7 +93,6 @@ module cache import cvw::*; #(parameter cvw_t P, logic FlushWayCntEn; logic SelWriteback; logic LRUWriteEn; - logic SelFlush; logic ResetOrFlushCntRst; logic [LINELEN-1:0] ReadDataLine, ReadDataLineCache; logic SelFetchBuffer; @@ -111,10 +110,10 @@ module cache import cvw::*; #(parameter cvw_t P, // and FlushAdr when handling D$ flushes // The icache must update to the newest PCNextF on flush as it is probably a trap. Trap // sets PCNextF to XTVEC and the icache must start reading the instruction. - assign AdrSelMuxSelData = {SelFlush, ((SelAdrData | SelHPTW) & ~((READ_ONLY_CACHE == 1) & FlushStage))}; + assign AdrSelMuxSelData = {FlushCache, ((SelAdrData | SelHPTW) & ~((READ_ONLY_CACHE == 1) & FlushStage))}; mux3 #(SETLEN) AdrSelMuxData(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr, AdrSelMuxSelData, CacheSetData); - assign AdrSelMuxSelTag = {SelFlush, ((SelAdrTag | SelHPTW) & ~((READ_ONLY_CACHE == 1) & FlushStage))}; + assign AdrSelMuxSelTag = {FlushCache, ((SelAdrTag | SelHPTW) & ~((READ_ONLY_CACHE == 1) & FlushStage))}; mux3 #(SETLEN) AdrSelMuxTag(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr, AdrSelMuxSelTag, CacheSetTag); @@ -122,7 +121,7 @@ module cache import cvw::*; #(parameter cvw_t P, cacheway #(P, PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( .clk, .reset, .CacheEn, .CacheSetData, .CacheSetTag, .PAdr, .LineWriteData, .LineByteMask, .SelWay, .SetValid, .ClearValid, .SetDirty, .ClearDirty, .VictimWay, - .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .HitDirtyWay, .TagWay, .FlushStage, .InvalidateCache); + .FlushWay, .FlushCache, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .HitDirtyWay, .TagWay, .FlushStage, .InvalidateCache); // Select victim way for associative caches if(NUMWAYS > 1) begin:vict @@ -161,7 +160,7 @@ module cache import cvw::*; #(parameter cvw_t P, mux3 #(PA_BITS) CacheBusAdrMux(.d0({PAdr[PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), .d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), .d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}), - .s({SelFlush, SelWriteback}), .y(CacheBusAdr)); + .s({FlushCache, SelWriteback}), .y(CacheBusAdr)); ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path @@ -227,7 +226,7 @@ module cache import cvw::*; #(parameter cvw_t P, .FlushStage, .CacheRW, .Stall, .CacheHit, .LineDirty, .HitLineDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdrData, .SelAdrTag, .SelWay, - .ClearDirty, .SetDirty, .SetValid, .ClearValid, .SelWriteback, .SelFlush, + .ClearDirty, .SetDirty, .SetValid, .ClearValid, .SelWriteback, .FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer, .InvalidateCache, .CMOpM, .CacheEn, .LRUWriteEn); diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 719cfab32..07494c2a9 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -62,7 +62,6 @@ module cachefsm import cvw::*; #(parameter cvw_t P, output logic ClearDirty, // Clear the dirty bit in the selected way and set output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback output logic LRUWriteEn, // Update the LRU state - output logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr output logic SelWay, // Controls which way to select a way data and tag, 00 = hitway, 10 = victimway, 11 = flushway output logic FlushAdrCntEn, // Enable the counter for Flush Adr output logic FlushWayCntEn, // Enable the way counter during a flush @@ -175,12 +174,6 @@ module cachefsm import cvw::*; #(parameter cvw_t P, (CurrState == STATE_WRITE_LINE); assign SelWriteback = (CurrState == STATE_WRITEBACK & (CMOpM[1] | CMOpM[2] | ~CacheBusAck)) | (CurrState == STATE_READY & AnyMiss & LineDirty); -/* -----\/----- EXCLUDED -----\/----- - assign SelFlush = (CurrState == STATE_READY & FlushCache) | - (CurrState == STATE_FLUSH) | - (CurrState == STATE_FLUSH_WRITEBACK); - -----/\----- EXCLUDED -----/\----- */ - assign SelFlush = FlushCache; // coverage off -item e 1 -fecexprrow 1 // (state is always FLUSH_WRITEBACK when FlushWayFlag & CacheBusAck) assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) | diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 52ccc6c15..96762dbde 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -43,7 +43,7 @@ module cacheway import cvw::*; #(parameter cvw_t P, input logic SetDirty, // Set the dirty bit in the selected way and set input logic SelWay, // Controls which way to select a way data and tag, 00 = hitway, 10 = victimway, 11 = flushway input logic ClearDirty, // Clear the dirty bit in the selected way and set - input logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr + input logic FlushCache, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr input logic VictimWay, // LRU selected this way as victim to evict input logic FlushWay, // This way is selected for flush and possible writeback if dirty input logic InvalidateCache,// Clear all valid bits @@ -80,12 +80,12 @@ module cacheway import cvw::*; #(parameter cvw_t P, if (!READ_ONLY_CACHE) begin:flushlogic logic FlushWayEn; - mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelDirty); + mux2 #(1) seltagmux(VictimWay, FlushWay, FlushCache, SelDirty); // FlushWay is part of a one hot way selection. Must clear it if FlushWay not selected. // coverage off -item e 1 -fecexprrow 3 - // nonzero ways will never see SelFlush=0 while FlushWay=1 since FlushWay only advances on a subset of SelFlush assertion cases. - assign FlushWayEn = FlushWay & SelFlush; + // nonzero ways will never see FlushCache=0 while FlushWay=1 since FlushWay only advances on a subset of FlushCache assertion cases. + assign FlushWayEn = FlushWay & FlushCache; assign SelNonHit = FlushWayEn | SelWay; end else begin:flushlogic // no flush operation for read-only caches. assign SelDirty = VictimWay; diff --git a/src/lsu/dtim.sv b/src/lsu/dtim.sv index 2817eafac..a44086a15 100644 --- a/src/lsu/dtim.sv +++ b/src/lsu/dtim.sv @@ -36,7 +36,7 @@ module dtim import cvw::*; #(parameter cvw_t P) ( input logic [P.PA_BITS-1:0] DTIMAdr, // No stall: Execution stage memory address. Stall: Memory stage memory address input logic [P.LLEN-1:0] WriteDataM, // Write data from IEU input logic [P.LLEN/8-1:0] ByteMaskM, // Selects which bytes within a word to write - output logic [P.LLEN-1:0] ReadDataWordM // Read data before subword selection + output logic [P.LLEN-1:0] ReadDataWordM // Read data before subword selection ); logic we;