Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Bit width error.

Browse Source
This commit is contained in:
Ross Thompson 2022-10-24 13:48:47 -05:00
parent 048ed01554
commit 7244ca1e7b
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
pipelined/src/uncore/uartPC16550D.sv
View File

@ -99,7 +99,7 @@ module uartPC16550D(
// receive data // receive data
(* mark_debug = "true" *) logic [10:0] RXBR; (* mark_debug = "true" *) logic [10:0] RXBR;
(* mark_debug = "true" *) logic [6:0] rxtimeoutcnt; (* mark_debug = "true" *) logic [9:0] rxtimeoutcnt;
logic rxcentered; logic rxcentered;
logic rxparity, rxparitybit, rxstopbit; logic rxparity, rxparitybit, rxstopbit;
(* mark_debug = "true" *) logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr; (* mark_debug = "true" *) logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;