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Added prefetch signals

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This commit is contained in:
David Harris 2023-07-02 10:06:58 -07:00
parent 482e4e6e92
commit 723b8266cb
3 changed files with 32 additions and 17 deletions
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33
src/ieu/controller.sv
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@ -63,6 +63,7 @@ module controller import cvw::*; #(parameter cvw_t P) (
output logic BMUActiveE, // Bit manipulation instruction being executed
output logic MDUActiveE, // Mul/Div instruction being executed
output logic [3:0] CMOpE, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
output logic [2:0] PrefetchE, // which prefetch instruction 1: prefetch.i, 2: prefetch.r, 4: prefetch.w
// Memory stage control signals
input logic StallM, FlushM, // Stall, flush Memory stage
@ -142,6 +143,7 @@ module controller import cvw::*; #(parameter cvw_t P) (
logic [2:0] ALUSelectD; // ALU Output selection mux control
logic IWValidFunct3D; // Detects if Funct3 is valid for IW instructions
logic [3:0] CMOpD; // which CMO instruction 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
logic [2:0] PrefetchD; // which prefetch instruction 1: prefetch.i, 2: prefetch.r, 4: prefetch.w
// Extract fields
assign OpD = InstrD[6:0];
@ -353,26 +355,37 @@ module controller import cvw::*; #(parameter cvw_t P) (
end
// Cache Management instructions
if (P.ZICBOM_SUPPORTED | P.ZICBOZ_SUPPORTED) begin:cmo
always_comb
if (CMOD) begin
always_comb begin
CMOpD = 4'b0000; // default: not a cbo instruction
if ((P.ZICBOM_SUPPORTED | P.ZICBOZ_SUPPORTED) & CMOD) begin
CMOpD[3] = (InstrD[31:20] == 12'd4); // cbo.zero
CMOpD[2] = (InstrD[31:20] == 12'd2); // cbo.clean
CMOpD[1] = (InstrD[31:20] == 12'd1) | ((InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b01)); // cbo.flush
CMOpD[0] = (InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b11); // cbo.inval
end else
CMOpD = 4'b0000; // not a cbo instruction
end else begin:cmo
assign CMOpD = 4'b0000; // cbo instructions not supported
end
end
// Prefetch Hints
always_comb begin
PrefetchD = 3'b000; // default: not a prefetch hint
if (P.ZICBOP_SUPPORTED & (InstrD[14:0] == 15'b110_00000_0010011)) begin // ori with destiation x0 is hint for Prefetch
case (Rs2D) // which type of prefectch?
5'b00000: PrefetchD = 3'b001; // prefetch.i
5'b00001: PrefetchD = 3'b010; // prefetch.r
5'b00011: PrefetchD = 3'b100; // prefetch.w
// default: not a prefetch hint
endcase
end
end
//assign AnyPrefetchD = |PrefetchD;
// Decode stage pipeline control register
flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
// Execute stage pipeline control register and logic
flopenrc #(33) controlregE(clk, reset, FlushE, ~StallE,
{ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, InstrValidD},
{ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, InstrValidE});
flopenrc #(36) controlregE(clk, reset, FlushE, ~StallE,
{ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, PrefetchD, InstrValidD},
{ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, PrefetchE, InstrValidE});
// Branch Logic
// The comparator handles both signed and unsigned branches using BranchSignedE

3
src/ieu/ieu.sv
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@ -46,6 +46,7 @@ module ieu import cvw::*; #(parameter cvw_t P) (
output logic [4:0] RdE, // Destination register
output logic MDUActiveE, // Mul/Div instruction being executed
output logic [3:0] CMOpE, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
output logic [2:0] PrefetchE, // which prefetch instruction 1: prefetch.i, 2: prefetch.r, 4: prefetch.w
// Memory stage signals
input logic SquashSCW, // Squash store conditional, from LSU
output logic [1:0] MemRWM, // Read/write control goes to LSU
@ -104,7 +105,7 @@ module ieu import cvw::*; #(parameter cvw_t P) (
.IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
.PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE,
.Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE,
.BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE, .CMOpE,
.BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE, .CMOpE, .PrefetchE,
.StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
.RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
.StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM, .StoreStallD);

3
src/wally/wallypipelinedcore.sv
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@ -79,6 +79,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
logic SquashSCW;
logic MDUActiveE; // Mul/Div instruction being executed
logic [3:0] CMOpE; // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
logic [2:0] PrefetchE; // 1: prefetch.i, 2: prefetch.r, 4: prefetch.w
logic [3:0] ENVCFG_CBE; // Cache block operation enables
// floating point unit signals
@ -193,7 +194,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
.InstrD, .STATUS_FS, .ENVCFG_CBE, .IllegalIEUFPUInstrD, .IllegalBaseInstrD,
// Execute Stage interface
.PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E,
.Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE, .CMOpE,
.Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE, .CMOpE, .PrefetchE,
// Memory stage interface
.SquashSCW, // from LSU
.MemRWM, // read/write control goes to LSU