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Fixed lint errors in the SDC.

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This commit is contained in:
Ross Thompson 2021-09-24 12:38:48 -05:00
parent 0f87f68b9d
commit 71e20c7f61
2 changed files with 10 additions and 6 deletions
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10
wally-pipelined/src/sdc/sd_cmd_fsm.sv
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@ -101,7 +101,7 @@ module sd_cmd_fsm
logic w_ACMD41_busy_timer_START, w_ACMD41_times_out_FLAG, w_ACMD41_busy_timer_RST; //give up after 1000 ms of ACMD41 logic w_ACMD41_busy_timer_START, w_ACMD41_times_out_FLAG, w_ACMD41_busy_timer_RST; //give up after 1000 ms of ACMD41
logic [2:0] w_ERROR_CODE_D, r_ERROR_CODE_Q ; // Error Codes for fatal error on SD CMD FSM logic [2:0] w_ERROR_CODE_D, r_ERROR_CODE_Q ; // Error Codes for fatal error on SD CMD FSM
logic w_error_code_rst, w_error_code_en; logic w_ERROR_CODE_RST, w_ERROR_CODE_EN;
logic [18:0] Timer_In; logic [18:0] Timer_In;
@ -204,9 +204,9 @@ module sd_cmd_fsm
localparam logic [7:0] c_NCC_min = 8'd7; // counter_in localparam logic [7:0] c_NCC_min = 8'd7; // counter_in
localparam logic [7:0] c_NRC_min = 8'd8; // counter_in localparam logic [7:0] c_NRC_min = 8'd8; // counter_in
//localparam logic [18:0] c_1000ms = 18'd400000; // ACMD41 timeout //localparam logic [18:0] c_1000ms = 19'd400000; // ACMD41 timeout
//*** BUG this value is too bit to fit into 19 bits. //*** BUG this value is too bit to fit into 19 bits.
localparam logic [18:0] c_1000ms = 18'd40000; // ACMD41 timeout localparam logic [18:0] c_1000ms = 19'd40000; // ACMD41 timeout
// command instruction type (opcode(6)) // command instruction type (opcode(6))
localparam c_CMD = 1'b0; localparam c_CMD = 1'b0;
@ -297,11 +297,15 @@ module sd_cmd_fsm
(i_COUNTER_OUT == 0)) ? s_error_no_response : (i_COUNTER_OUT == 0)) ? s_error_no_response :
(((r_curr_state == s_idle_for_start_bit) & (i_SD_CMD_RX == c_start_bit) & (((r_curr_state == s_idle_for_start_bit) & (i_SD_CMD_RX == c_start_bit) &
/* verilator lint_off UNSIGNED */
(i_COUNTER_OUT >= 0) & (i_R_TYPE == c_response_type_R2_CID_CSD)) | (i_COUNTER_OUT >= 0) & (i_R_TYPE == c_response_type_R2_CID_CSD)) |
/* verilator lint_on UNSIGNED */
((r_curr_state == s_rx_136) & (i_COUNTER_OUT > 0))) ? s_rx_136 : ((r_curr_state == s_rx_136) & (i_COUNTER_OUT > 0))) ? s_rx_136 :
(((r_curr_state == s_idle_for_start_bit) & (i_SD_CMD_RX == c_start_bit) & (((r_curr_state == s_idle_for_start_bit) & (i_SD_CMD_RX == c_start_bit) &
/* verilator lint_off UNSIGNED */
(i_COUNTER_OUT >= 0) & (i_R_TYPE != c_response_type_R2_CID_CSD)) | (i_COUNTER_OUT >= 0) & (i_R_TYPE != c_response_type_R2_CID_CSD)) |
/* verilator lint_on UNSIGNED */
((r_curr_state == s_rx_48) & (i_COUNTER_OUT > 0))) ? s_rx_48 : ((r_curr_state == s_rx_48) & (i_COUNTER_OUT > 0))) ? s_rx_48 :
(((r_curr_state == s_rx_136) & (i_COUNTER_OUT == 0)) | (((r_curr_state == s_rx_136) & (i_COUNTER_OUT == 0)) |

2
wally-pipelined/src/sdc/simple_timer.sv
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@ -34,7 +34,7 @@ module simple_timer #(parameter BUS_WIDTH = 4)
input logic CLK); input logic CLK);
logic [0:2**BUS_WIDTH-1] count; logic [BUS_WIDTH-1:0] count;
logic timer_en; logic timer_en;
assign timer_en = count != 0; assign timer_en = count != 0;