diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 213b5ceea..946e2d283 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -7,37 +7,37 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM -add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/DCacheStall +add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -85,11 +85,11 @@ add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/if add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM -add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrW +add wave -noupdate -group {instruction pipeline} /testbench/InstrFName +add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD +add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE +add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM +add wave -noupdate -group {instruction pipeline} /testbench/InstrW add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F @@ -105,7 +105,7 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D -add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf +add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rf add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3 @@ -118,18 +118,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags -add wave -noupdate -expand -group alu -divider internals -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt -add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags +add wave -noupdate -group alu -divider internals +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E @@ -243,7 +243,6 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DisableTranslation add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemRWM -add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DataStall add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemPAdrM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataW @@ -253,6 +252,7 @@ add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DSquashBusAccessM add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/HRDATAW add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAckW add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/StallW +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR @@ -280,56 +280,45 @@ add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM -add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUTranslate -add wave -noupdate -expand -group ptwalker -color Gold /testbench/dut/hart/pagetablewalker/WalkerState -add wave -noupdate -expand -group ptwalker -color Salmon /testbench/dut/hart/pagetablewalker/HPTWStall -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/HPTWRead -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUPAdr -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUStall -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/EndWalk -add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/pagetablewalker/MMUReadPTE -add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/pagetablewalker/PRegEn -add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/pagetablewalker/CurrentPTE +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM +add wave -noupdate -expand -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM +add wave -noupdate -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/pagetablewalker/genblk1/WalkerState +add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/MMUTranslate +add wave -noupdate -expand -group ptwalker -color Salmon /testbench/dut/hart/lsu/pagetablewalker/HPTWStall +add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/HPTWRead +add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/MMUPAdr +add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/ITLBMissF +add wave -noupdate -expand -group ptwalker -expand -group miss/write /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/MMUReadPTE +add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/lsu/pagetablewalker/genblk1/CurrentPTE add wave -noupdate -expand -group ptwalker -divider data -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/TranslationPAdr -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/ValidPTE -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/LeafPTE -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUStall -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/TranslationPAdr -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/PageTableEntry -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/PageType -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/ITLBWriteF -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/DTLBWriteM -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerInstrPageFaultF -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerLoadPageFaultM -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerStorePageFaultM -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/MMUStall -add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/EndWalk -add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUPAdr -add wave -noupdate -expand -group {LSU ARB} -color Gold /testbench/dut/hart/arbiter/CurrState -add wave -noupdate -expand -group {LSU ARB} -color {Medium Orchid} /testbench/dut/hart/arbiter/SelPTW -add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/pagetablewalker/MMUStall -add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWTranslate -add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWRead -add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWPAdr -add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWReadPTE -add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWReady -add wave -noupdate -expand -group {LSU ARB} -group toLSU /testbench/dut/hart/arbiter/MemAdrMtoLSU -add wave -noupdate /testbench/dut/hart/lsu/DataStall +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/ITLBWriteF +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/DTLBWriteM +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerInstrPageFaultF +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerLoadPageFaultM +add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/lsu/pagetablewalker/WalkerStorePageFaultM +add wave -noupdate -expand -group ptwalker /testbench/dut/hart/lsu/pagetablewalker/MMUPAdr +add wave -noupdate -expand -group {LSU ARB} -color Gold /testbench/dut/hart/lsu/arbiter/CurrState +add wave -noupdate -expand -group {LSU ARB} -color {Medium Orchid} /testbench/dut/hart/lsu/arbiter/SelPTW +add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/lsu/arbiter/HPTWTranslate +add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/lsu/arbiter/HPTWRead +add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/lsu/arbiter/HPTWPAdr +add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/lsu/arbiter/HPTWReadPTE +add wave -noupdate -expand -group {LSU ARB} -expand -group toLSU /testbench/dut/hart/lsu/arbiter/MemAdrMtoLSU add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn @@ -354,21 +343,15 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss -add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/tlb/TLBWrite add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF -add wave -noupdate /testbench/dut/hart/pagetablewalker/StartWalk -add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/DisableTranslation -add wave -noupdate -group tlbread /testbench/dut/hart/lsu/dmmu/tlb/VirtualAddress -add wave -noupdate -group tlbread /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/CAMHit -add wave -noupdate -group tlbread /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/VPNIndex -add wave -noupdate -group tlbread /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/HitPageType -add wave -noupdate -group tlbread /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/VirtualPageNumber -add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/TLBWrite -add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/PTEWriteVal -add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/WriteLines +add wave -noupdate /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM +add wave -noupdate /testbench/dut/hart/lsu/pagetablewalker/MemAdrM +add wave -noupdate /testbench/dut/hart/lsu/MemAdrM +add wave -noupdate /testbench/dut/hart/lsu/pagetablewalker/PCF TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 8} {4545 ns} 0} {{Cursor 3} {3377 ns} 0} {{Cursor 4} {3215 ns} 0} -quietly wave cursor active 1 +WaveRestoreCursors {{Cursor 4} {16658 ns} 1} {{Cursor 4} {16655 ns} 0} +quietly wave cursor active 2 configure wave -namecolwidth 250 configure wave -valuecolwidth 189 configure wave -justifyvalue left @@ -383,4 +366,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {4209 ns} {4657 ns} +WaveRestoreZoom {16565 ns} {16719 ns} diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index ffd96be9c..db6aa37ac 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -28,122 +28,123 @@ `include "wally-config.vh" // *** Ross Thompson amo misalignment check? -module lsu ( - input logic clk, reset, - input logic StallM, FlushM, StallW, FlushW, - output logic DCacheStall, - // Memory Stage +module lsu + ( + input logic clk, reset, + input logic StallM, FlushM, StallW, FlushW, + output logic DCacheStall, + // Memory Stage - // connected to cpu (controls) - input logic [1:0] MemRWM, - input logic [2:0] Funct3M, - input logic [1:0] AtomicM, - output logic CommittedM, - output logic SquashSCW, - output logic DataMisalignedM, + // connected to cpu (controls) + input logic [1:0] MemRWM, + input logic [2:0] Funct3M, + input logic [1:0] AtomicM, + output logic CommittedM, + output logic SquashSCW, + output logic DataMisalignedM, - // address and write data - input logic [`XLEN-1:0] MemAdrM, - input logic [`XLEN-1:0] WriteDataM, - output logic [`XLEN-1:0] ReadDataW, + // address and write data + input logic [`XLEN-1:0] MemAdrM, + input logic [`XLEN-1:0] WriteDataM, + output logic [`XLEN-1:0] ReadDataW, - // cpu privilege - input logic [1:0] PrivilegeModeW, - input logic DTLBFlushM, - // faults - input logic NonBusTrapM, - output logic DTLBLoadPageFaultM, DTLBStorePageFaultM, - output logic LoadMisalignedFaultM, LoadAccessFaultM, - // cpu hazard unit (trap) - output logic StoreMisalignedFaultM, StoreAccessFaultM, + // cpu privilege + input logic [1:0] PrivilegeModeW, + input logic DTLBFlushM, + // faults + input logic NonBusTrapM, + output logic DTLBLoadPageFaultM, DTLBStorePageFaultM, + output logic LoadMisalignedFaultM, LoadAccessFaultM, + // cpu hazard unit (trap) + output logic StoreMisalignedFaultM, StoreAccessFaultM, - // connect to ahb - input logic CommitM, // should this be generated in the abh interface? - output logic [`PA_BITS-1:0] MemPAdrM, // to ahb - output logic MemReadM, MemWriteM, - output logic [1:0] AtomicMaskedM, - input logic MemAckW, // from ahb - input logic [`XLEN-1:0] HRDATAW, // from ahb - output logic [2:0] SizeFromLSU, - output logic StallWfromLSU, + // connect to ahb + input logic CommitM, // should this be generated in the abh interface? + output logic [`PA_BITS-1:0] MemPAdrM, // to ahb + output logic MemReadM, MemWriteM, + output logic [1:0] AtomicMaskedM, + input logic MemAckW, // from ahb + input logic [`XLEN-1:0] HRDATAW, // from ahb + output logic [2:0] SizeFromLSU, + output logic StallWfromLSU, - // mmu management + // mmu management - // page table walker - input logic [`XLEN-1:0] SATP_REGW, // from csr - input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, - input logic [1:0] STATUS_MPP, + // page table walker + input logic [`XLEN-1:0] SATP_REGW, // from csr + input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, + input logic [1:0] STATUS_MPP, - input logic [`XLEN-1:0] PCF, - input logic ITLBMissF, - output logic [`XLEN-1:0] PageTableEntryF, - output logic [1:0] PageTypeF, - output logic ITLBWriteF, - output logic WalkerInstrPageFaultF, - output logic WalkerLoadPageFaultM, - output logic WalkerStorePageFaultM, + input logic [`XLEN-1:0] PCF, + input logic ITLBMissF, + output logic [`XLEN-1:0] PageTableEntryF, + output logic [1:0] PageTypeF, + output logic ITLBWriteF, + output logic WalkerInstrPageFaultF, + output logic WalkerLoadPageFaultM, + output logic WalkerStorePageFaultM, - output logic DTLBHitM, // not connected - - // PMA/PMP (inside mmu) signals - input logic [31:0] HADDR, // *** replace all of these H inputs with physical adress once pma checkers have been edited to use paddr as well. - input logic [2:0] HSIZE, HBURST, - input logic HWRITE, - input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], // *** this one especially has a large note attached to it in pmpchecker. + output logic DTLBHitM, // not connected - output logic PMALoadAccessFaultM, PMAStoreAccessFaultM, - output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa. - - output logic DSquashBusAccessM -// output logic [5:0] DHSELRegionsM - -); + // PMA/PMP (inside mmu) signals + input logic [31:0] HADDR, // *** replace all of these H inputs with physical adress once pma checkers have been edited to use paddr as well. + input logic [2:0] HSIZE, HBURST, + input logic HWRITE, + input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], + input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], // *** this one especially has a large note attached to it in pmpchecker. - logic SquashSCM; - logic DTLBPageFaultM; - logic MemAccessM; + output logic PMALoadAccessFaultM, PMAStoreAccessFaultM, + output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa. - logic preCommittedM; + output logic DSquashBusAccessM + // output logic [5:0] DHSELRegionsM - typedef enum {STATE_READY, - STATE_FETCH, - STATE_FETCH_AMO_1, - STATE_FETCH_AMO_2, - STATE_STALLED, - STATE_PTW_READY, - STATE_PTW_FETCH, - STATE_PTW_DONE} statetype; + ); + + logic SquashSCM; + logic DTLBPageFaultM; + logic MemAccessM; + + logic preCommittedM; + + typedef enum {STATE_READY, + STATE_FETCH, + STATE_FETCH_AMO_1, + STATE_FETCH_AMO_2, + STATE_STALLED, + STATE_PTW_READY, + STATE_PTW_FETCH, + STATE_PTW_DONE} statetype; statetype CurrState, NextState; - + - logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; // *** these are just so that the mmu has somewhere to put these outputs since they aren't used in dmem + logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; // *** these are just so that the mmu has somewhere to put these outputs since they aren't used in dmem // *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete. - logic DTLBMissM; - logic [`XLEN-1:0] PageTableEntryM; - logic [1:0] PageTypeM; - logic DTLBWriteM; - logic [`XLEN-1:0] MMUReadPTE; - logic MMUReady; - logic HPTWStall; - logic [`XLEN-1:0] MMUPAdr; - logic MMUTranslate; - logic HPTWRead; - logic [1:0] MemRWMtoLSU; - logic [2:0] SizeToLSU; - logic [1:0] AtomicMtoLSU; - logic [`XLEN-1:0] MemAdrMtoLSU; - logic [`XLEN-1:0] WriteDataMtoLSU; - logic [`XLEN-1:0] ReadDataWFromLSU; - logic StallWtoLSU; - logic CommittedMfromLSU; - logic SquashSCWfromLSU; - logic DataMisalignedMfromLSU; - logic HPTWReady; - logic LSUStall; - logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB. + logic DTLBMissM; + logic [`XLEN-1:0] PageTableEntryM; + logic [1:0] PageTypeM; + logic DTLBWriteM; + logic [`XLEN-1:0] MMUReadPTE; + logic MMUReady; + logic HPTWStall; + logic [`XLEN-1:0] MMUPAdr; + logic MMUTranslate; + logic HPTWRead; + logic [1:0] MemRWMtoLSU; + logic [2:0] SizeToLSU; + logic [1:0] AtomicMtoLSU; + logic [`XLEN-1:0] MemAdrMtoLSU; + logic [`XLEN-1:0] WriteDataMtoLSU; + logic [`XLEN-1:0] ReadDataWFromLSU; + logic StallWtoLSU; + logic CommittedMfromLSU; + logic SquashSCWfromLSU; + logic DataMisalignedMfromLSU; + logic HPTWReady; + logic LSUStall; + logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB. @@ -216,7 +217,7 @@ module lsu ( .DataStall(LSUStall)); - + mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) dmmu(.VirtualAddress(MemAdrMtoLSU), .Size(SizeToLSU[1:0]), @@ -234,7 +235,7 @@ module lsu ( .ReadAccessM(MemRWMtoLSU[1]), .SquashBusAccess(DSquashBusAccessM), .DisableTranslation(DisableTranslation), -// .SelRegions(DHSELRegionsM), + // .SelRegions(DHSELRegionsM), .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist? // Specify which type of page fault is occurring @@ -275,8 +276,8 @@ module lsu ( generate if (`A_SUPPORTED) begin // atomic instructions supported logic [`PA_BITS-1:2] ReservationPAdrW; - logic ReservationValidM, ReservationValidW; - logic lrM, scM, WriteAdrMatchM; + logic ReservationValidM, ReservationValidW; + logic lrM, scM, WriteAdrMatchM; assign lrM = MemReadM && AtomicMtoLSU[0]; assign scM = MemRWMtoLSU[0] && AtomicMtoLSU[0]; @@ -351,7 +352,7 @@ module lsu ( end end STATE_FETCH: begin - LSUStall = 1'b1; + LSUStall = 1'b1; if (MemAckW & ~StallWtoLSU) begin NextState = STATE_READY; end else if (MemAckW & StallWtoLSU) begin @@ -372,6 +373,7 @@ module lsu ( LSUStall = 1'b0; if (DTLBWriteM) begin NextState = STATE_READY; + LSUStall = 1'b1; end else if (MemReadM & ~DataMisalignedMfromLSU) begin NextState = STATE_PTW_FETCH; end else begin