From 043f1e10c5dc9a630fc22f68851d632f6ec24cee Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Sat, 3 Jul 2021 15:51:25 -0500
Subject: [PATCH 1/3] Added explicit names to lsu, lsuarb and pagetable walker
to make the code refactoring process eaiser.
---
wally-pipelined/src/lsu/lsu.sv | 16 +--
.../src/wally/wallypipelinedhart.sv | 125 ++++++++++++++----
2 files changed, 109 insertions(+), 32 deletions(-)
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 36d4715fe..36d859071 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -66,7 +66,7 @@ module lsu (
input logic MemAckW, // from ahb
input logic [`XLEN-1:0] HRDATAW, // from ahb
output logic [2:0] Funct3MfromLSU,
- output logic StallWfromLSU,
+ output logic StallWfromLSU,
// mmu management
@@ -85,14 +85,14 @@ module lsu (
output logic DTLBHitM, // not connected
// PMA/PMP (inside mmu) signals
- input logic [31:0] HADDR, // *** replace all of these H inputs with physical adress once pma checkers have been edited to use paddr as well.
- input logic [2:0] HSIZE, HBURST,
- input logic HWRITE,
- input var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0],
- input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // *** this one especially has a large note attached to it in pmpchecker.
+ input logic [31:0] HADDR, // *** replace all of these H inputs with physical adress once pma checkers have been edited to use paddr as well.
+ input logic [2:0] HSIZE, HBURST,
+ input logic HWRITE,
+ input var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0],
+ input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // *** this one especially has a large note attached to it in pmpchecker.
- output logic PMALoadAccessFaultM, PMAStoreAccessFaultM,
- output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa.
+ output logic PMALoadAccessFaultM, PMAStoreAccessFaultM,
+ output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa.
output logic DSquashBusAccessM
// output logic [5:0] DHSELRegionsM
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 978f747fa..47035ec6b 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -122,8 +122,8 @@ module wallypipelinedhart
logic PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM;
logic PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM;
logic DSquashBusAccessM, ISquashBusAccessF;
- var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
- var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0];
+ var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
+ var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0];
// IMem stalls
logic ICacheStallF;
@@ -187,10 +187,38 @@ module wallypipelinedhart
// mux2 #(`XLEN) OutputInput2mux(WriteDataM, FWriteDataM, FMemRWM[0], WriteDatatmpM);
- pagetablewalker pagetablewalker(.HPTWRead(HPTWRead),
- .*); // can send addresses to ahblite, send out pagetablestall
+ pagetablewalker pagetablewalker(
+ .clk(clk),
+ .reset(reset),
+ .SATP_REGW(SATP_REGW), // already on lsu port
+ .PCF(PCF), // add to lsu port
+ .MemAdrM(MemAdrM), // alreayd on lsu port
+ .ITLBMissF(ITLBMissF), // add to lsu port
+ .DTLBMissM(DTLBMissM), // already on lsu port convert to internal
+ .MemRWM(MemRWM), // already on lsu port
+ .PageTableEntryF(PageTableEntryF), // add to lsu port
+ .PageTableEntryM(PageTableEntryM), // already on lsu port convert to internal
+ .PageTypeF(PageTypeF), // add to lsu port connects to ifu
+ .PageTypeM(PageTypeM),
+ .ITLBWriteF(ITLBWriteF),
+ .DTLBWriteM(DTLBWriteM),
+ .MMUReadPTE(MMUReadPTE),
+ .MMUReady(MMUReady),
+ .HPTWStall(HPTWStall),
+ .MMUPAdr(MMUPAdr),
+ .MMUTranslate(MMUTranslate),
+ .HPTWRead(HPTWRead),
+ .MMUStall(MMUStall),
+ .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
+ .WalkerLoadPageFaultM(WalkerLoadPageFaultM),
+ .WalkerStorePageFaultM(WalkerStorePageFaultM));
+
+
+
// arbiter between IEU and pagetablewalker
- lsuArb arbiter(// HPTW connection
+ lsuArb arbiter(.clk(clk),
+ .reset(reset),
+ // HPTW connection
.HPTWTranslate(MMUTranslate),
.HPTWRead(HPTWRead),
.HPTWPAdr(MMUPAdr),
@@ -202,8 +230,8 @@ module wallypipelinedhart
.Funct3M(Funct3M),
.AtomicM(AtomicM),
.MemAdrM(MemAdrM),
- .StallW(StallW),
.WriteDataM(WriteDataM),
+ .StallW(StallW),
.ReadDataW(ReadDataW),
.CommittedM(CommittedM),
.SquashSCW(SquashSCW),
@@ -222,29 +250,78 @@ module wallypipelinedhart
.DataMisalignedMfromLSU(DataMisalignedMfromLSU),
.ReadDataWFromLSU(ReadDataWFromLSU),
.HPTWReadyfromLSU(HPTWReadyfromLSU),
- .DataStall(DataStall),
- .*);
+ .DataStall(DataStall));
- lsu lsu(.MemRWM(MemRWMtoLSU),
- .Funct3M(Funct3MtoLSU),
- .AtomicM(AtomicMtoLSU),
- .MemAdrM(MemAdrMtoLSU),
- .WriteDataM(WriteDataMtoLSU),
- .ReadDataW(ReadDataWFromLSU),
+ lsu lsu(.clk(clk),
+ .reset(reset),
+ .StallM(StallM),
+ .FlushM(FlushM),
.StallW(StallWtoLSU),
+ .FlushW(FlushW),
+ // connected to arbiter (reconnect to CPU)
+ .MemRWM(MemRWMtoLSU), // change to MemRWM
+ .Funct3M(Funct3MtoLSU), // change to Funct3M
+ .AtomicM(AtomicMtoLSU), // change to AtomicMtoLSU
+ .CommittedM(CommittedMfromLSU), // change to CommitttedM
+ .SquashSCW(SquashSCWfromLSU), // change to SquashSCW
+ .DataMisalignedM(DataMisalignedMfromLSU), // change to DataMisalignedM
+ .MemAdrM(MemAdrMtoLSU), // change to MemAdrM
+ .WriteDataM(WriteDataMtoLSU), // change to WriteDataM
+ .ReadDataW(ReadDataWFromLSU), // change to ReadDataW
- .CommittedM(CommittedMfromLSU),
- .SquashSCW(SquashSCWfromLSU),
- .DataMisalignedM(DataMisalignedMfromLSU),
- .DisableTranslation(DisableTranslation),
+ // connected to ahb (all stay the same)
+ .CommitM(CommitM),
+ .MemPAdrM(MemPAdrM),
+ .MemReadM(MemReadM),
+ .MemWriteM(MemWriteM),
+ .AtomicMaskedM(AtomicMaskedM),
+ .MemAckW(MemAckW),
+ .HRDATAW(HRDATAW),
+ .Funct3MfromLSU(Funct3MfromLSU), // stays the same
+ .StallWfromLSU(StallWfromLSU), // stays the same
+ .DSquashBusAccessM(DSquashBusAccessM), // probalby removed after dcache implemenation?
+ // currently not connected (but will need to be used for lsu talking to ahb.
+ .HADDR(HADDR),
+ .HSIZE(HSIZE),
+ .HBURST(HBURST),
+ .HWRITE(HWRITE),
+
+ // connect to csr or privilege and stay the same.
+ .PrivilegeModeW(PrivilegeModeW), // connects to csr
+ .PMPCFG_ARRAY_REGW(PMPCFG_ARRAY_REGW), // connects to csr
+ .PMPADDR_ARRAY_REGW(PMPADDR_ARRAY_REGW), // connects to csr
+ // hptw keep i/o
+ .SATP_REGW(SATP_REGW), // from csr
+ .STATUS_MXR(STATUS_MXR), // from csr
+ .STATUS_SUM(STATUS_SUM), // from csr
+
+ .DTLBFlushM(DTLBFlushM), // connects to privilege
+ .NonBusTrapM(NonBusTrapM), // connects to privilege
+ .DTLBLoadPageFaultM(DTLBLoadPageFaultM), // connects to privilege
+ .DTLBStorePageFaultM(DTLBStorePageFaultM), // connects to privilege
+ .LoadMisalignedFaultM(LoadMisalignedFaultM), // connects to privilege
+ .LoadAccessFaultM(LoadAccessFaultM), // connects to privilege
+ .StoreMisalignedFaultM(StoreMisalignedFaultM), // connects to privilege
+ .StoreAccessFaultM(StoreAccessFaultM), // connects to privilege
+ .PMALoadAccessFaultM(PMALoadAccessFaultM),
+ .PMAStoreAccessFaultM(PMAStoreAccessFaultM),
+ .PMPLoadAccessFaultM(PMPLoadAccessFaultM),
+ .PMPStoreAccessFaultM(PMPStoreAccessFaultM),
+
+ // connected to hptw. Move to internal.
+ .PageTableEntryM(PageTableEntryM),
+ .PageTypeM(PageTypeM),
+ .DTLBWriteM(DTLBWriteM), // from hptw.
+ .DTLBMissM(DTLBMissM), // to hptw from dmmu
+ .DisableTranslation(DisableTranslation), // from hptw to dmmu
+ .HPTWReady(HPTWReadyfromLSU), // from hptw, remove
+
+ .DTLBHitM(DTLBHitM), // not connected remove
+
+ .DataStall(DataStall)) // change to DCacheStall
+ ;
- .DataStall(DataStall),
- .HPTWReady(HPTWReadyfromLSU),
- .Funct3MfromLSU(Funct3MfromLSU),
- .StallWfromLSU(StallWfromLSU),
-// .DataStall(LSUStall),
- .* ); // data cache unit
ahblite ebu(
//.InstrReadF(1'b0),
From 9f16d08d0d802b7ae96fdfbd7032a16333a4adc7 Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Sat, 3 Jul 2021 16:06:09 -0500
Subject: [PATCH 2/3] removed mmustall and finished port annotations on ptw and
lsuArb.
---
wally-pipelined/src/ebu/ahblite.sv | 9 -------
wally-pipelined/src/mmu/pagetablewalker.sv | 15 -----------
.../src/wally/wallypipelinedhart.sv | 26 +++++++++----------
3 files changed, 12 insertions(+), 38 deletions(-)
diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv
index 70f32bf70..09e5799c5 100644
--- a/wally-pipelined/src/ebu/ahblite.sv
+++ b/wally-pipelined/src/ebu/ahblite.sv
@@ -53,13 +53,6 @@ module ahblite (
input logic [1:0] MemSizeM,
//output logic DataStall,
// Signals from MMU
-/* -----\/----- EXCLUDED -----\/-----
- input logic MMUStall,
- input logic [`XLEN-1:0] MMUPAdr,
- input logic MMUTranslate,
- output logic [`XLEN-1:0] MMUReadPTE,
- output logic MMUReady,
- -----/\----- EXCLUDED -----/\----- */
// Signals from PMA checker
input logic DSquashBusAccessM, ISquashBusAccessF,
// Signals to PMA checker (metadata of proposed access)
@@ -158,8 +151,6 @@ module ahblite (
-----/\----- EXCLUDED -----/\----- */
- //assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) ||
- // MMUStall);
// bus outputs
assign #1 GrantData = (ProposedNextBusState == MEMREAD) || (ProposedNextBusState == MEMWRITE) ||
diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv
index d0d2152f6..45479d4ab 100644
--- a/wally-pipelined/src/mmu/pagetablewalker.sv
+++ b/wally-pipelined/src/mmu/pagetablewalker.sv
@@ -64,11 +64,6 @@ module pagetablewalker
output logic HPTWRead,
-
-
- // Stall signal
- output logic MMUStall,
-
// Faults
output logic WalkerInstrPageFaultF,
output logic WalkerLoadPageFaultM,
@@ -190,7 +185,6 @@ module pagetablewalker
PRegEn = 1'b0;
TranslationPAdr = '0;
HPTWRead = 1'b0;
- MMUStall = 1'b1;
PageTableEntry = '0;
PageType = '0;
DTLBWriteM = '0;
@@ -209,7 +203,6 @@ module pagetablewalker
end else begin
NextWalkerState = IDLE;
TranslationPAdr = '0;
- MMUStall = 1'b0;
end
end
@@ -271,14 +264,12 @@ module pagetablewalker
LEAF: begin
NextWalkerState = IDLE;
- MMUStall = 1'b0;
end
FAULT: begin
NextWalkerState = IDLE;
WalkerInstrPageFaultF = ~DTLBMissMQ;
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
WalkerStorePageFaultM = DTLBMissMQ && MemStore;
- MMUStall = 1'b0;
end
// Default case should never happen, but is included for linter.
@@ -293,8 +284,6 @@ module pagetablewalker
assign VPN1 = TranslationVAdrQ[31:22];
assign VPN0 = TranslationVAdrQ[21:12];
- //assign HPTWRead = (WalkerState == IDLE && MMUTranslate) ||
- // WalkerState == LEVEL2 || WalkerState == LEVEL1;
// Capture page table entry from data cache
@@ -335,7 +324,6 @@ module pagetablewalker
PRegEn = 1'b0;
TranslationPAdr = '0;
HPTWRead = 1'b0;
- MMUStall = 1'b1;
PageTableEntry = '0;
PageType = '0;
DTLBWriteM = '0;
@@ -358,7 +346,6 @@ module pagetablewalker
end else begin
NextWalkerState = IDLE;
TranslationPAdr = '0;
- MMUStall = 1'b0;
end
end
@@ -499,7 +486,6 @@ module pagetablewalker
LEAF: begin
NextWalkerState = IDLE;
- MMUStall = 1'b0;
end
FAULT: begin
@@ -507,7 +493,6 @@ module pagetablewalker
WalkerInstrPageFaultF = ~DTLBMissMQ;
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
WalkerStorePageFaultM = DTLBMissMQ && MemStore;
- MMUStall = 1'b0;
end
// Default case should never happen
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 47035ec6b..9a678189b 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -129,7 +129,6 @@ module wallypipelinedhart
logic ICacheStallF;
logic DCacheStall;
logic [`XLEN-1:0] MMUPAdr, MMUReadPTE;
- logic MMUStall;
logic MMUTranslate, MMUReady;
logic HPTWRead;
logic HPTWReadyfromLSU;
@@ -199,19 +198,18 @@ module wallypipelinedhart
.PageTableEntryF(PageTableEntryF), // add to lsu port
.PageTableEntryM(PageTableEntryM), // already on lsu port convert to internal
.PageTypeF(PageTypeF), // add to lsu port connects to ifu
- .PageTypeM(PageTypeM),
- .ITLBWriteF(ITLBWriteF),
- .DTLBWriteM(DTLBWriteM),
- .MMUReadPTE(MMUReadPTE),
- .MMUReady(MMUReady),
- .HPTWStall(HPTWStall),
- .MMUPAdr(MMUPAdr),
- .MMUTranslate(MMUTranslate),
- .HPTWRead(HPTWRead),
- .MMUStall(MMUStall),
- .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
- .WalkerLoadPageFaultM(WalkerLoadPageFaultM),
- .WalkerStorePageFaultM(WalkerStorePageFaultM));
+ .PageTypeM(PageTypeM), // already on lsu port convert to internal
+ .ITLBWriteF(ITLBWriteF), // add to lsu port connects to ifu
+ .DTLBWriteM(DTLBWriteM), // already on lsu port convert to internal
+ .MMUReadPTE(MMUReadPTE), // from lsu arb convert to internal
+ .MMUReady(MMUReady), // to lsu arb, convert to internal
+ .HPTWStall(HPTWStall), // from lsu arb convert to internal
+ .MMUPAdr(MMUPAdr), // to lsu arb, convert to internal
+ .MMUTranslate(MMUTranslate), // to lsu arb, convert to internal
+ .HPTWRead(HPTWRead), // to lsu arb, convert to internal
+ .WalkerInstrPageFaultF(WalkerInstrPageFaultF), // add to lsu port
+ .WalkerLoadPageFaultM(WalkerLoadPageFaultM), // add to lsu port (to privilege)
+ .WalkerStorePageFaultM(WalkerStorePageFaultM)); // add to lsu port (to privilege)
From 5b70eb86b0c83d8b14ba7faf30c9ddab07d3e632 Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Sun, 4 Jul 2021 13:49:38 -0500
Subject: [PATCH 3/3] relocated lsuarb and pagetable walker inside the lsu.
Does not pass busybear or buildroot, but passes rv32ic and rv64ic.
---
wally-pipelined/regression/wave.do | 93 +++-----
wally-pipelined/src/lsu/lsu.sv | 212 +++++++++++++-----
wally-pipelined/src/lsu/lsuArb.sv | 3 -
.../src/wally/wallypipelinedhart.sv | 108 ++-------
4 files changed, 201 insertions(+), 215 deletions(-)
diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index 213b5ceea..42da60938 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -7,19 +7,19 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
@@ -118,18 +118,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags
-add wave -noupdate -expand -group alu -divider internals
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
-add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
+add wave -noupdate -group alu -divider internals
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
@@ -243,7 +243,6 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DisableTranslation
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemRWM
-add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/DataStall
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemAdrM
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/MemPAdrM
add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataW
@@ -294,42 +293,7 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
-add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUTranslate
-add wave -noupdate -expand -group ptwalker -color Gold /testbench/dut/hart/pagetablewalker/WalkerState
-add wave -noupdate -expand -group ptwalker -color Salmon /testbench/dut/hart/pagetablewalker/HPTWStall
-add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/HPTWRead
-add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUPAdr
-add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUStall
-add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/EndWalk
-add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/pagetablewalker/MMUReadPTE
-add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/pagetablewalker/PRegEn
-add wave -noupdate -expand -group ptwalker -expand -group pte /testbench/dut/hart/pagetablewalker/CurrentPTE
add wave -noupdate -expand -group ptwalker -divider data
-add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/TranslationPAdr
-add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/ValidPTE
-add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/LeafPTE
-add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUStall
-add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/TranslationPAdr
-add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/PageTableEntry
-add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/PageType
-add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/ITLBWriteF
-add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/DTLBWriteM
-add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerInstrPageFaultF
-add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerLoadPageFaultM
-add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/WalkerStorePageFaultM
-add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/MMUStall
-add wave -noupdate -expand -group ptwalker -group {fsm outputs} /testbench/dut/hart/pagetablewalker/EndWalk
-add wave -noupdate -expand -group ptwalker /testbench/dut/hart/pagetablewalker/MMUPAdr
-add wave -noupdate -expand -group {LSU ARB} -color Gold /testbench/dut/hart/arbiter/CurrState
-add wave -noupdate -expand -group {LSU ARB} -color {Medium Orchid} /testbench/dut/hart/arbiter/SelPTW
-add wave -noupdate -expand -group {LSU ARB} /testbench/dut/hart/pagetablewalker/MMUStall
-add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWTranslate
-add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWRead
-add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWPAdr
-add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWReadPTE
-add wave -noupdate -expand -group {LSU ARB} -expand -group hptw /testbench/dut/hart/arbiter/HPTWReady
-add wave -noupdate -expand -group {LSU ARB} -group toLSU /testbench/dut/hart/arbiter/MemAdrMtoLSU
-add wave -noupdate /testbench/dut/hart/lsu/DataStall
add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK
add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn
@@ -356,7 +320,6 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb
add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/tlb/TLBWrite
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
-add wave -noupdate /testbench/dut/hart/pagetablewalker/StartWalk
add wave -noupdate /testbench/dut/hart/lsu/dmmu/tlb/DisableTranslation
add wave -noupdate -group tlbread /testbench/dut/hart/lsu/dmmu/tlb/VirtualAddress
add wave -noupdate -group tlbread /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/CAMHit
@@ -367,8 +330,8 @@ add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/TLBWr
add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/PTEWriteVal
add wave -noupdate -group tlbwrite /testbench/dut/hart/lsu/dmmu/tlb/tlbcam/WriteLines
TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 8} {4545 ns} 0} {{Cursor 3} {3377 ns} 0} {{Cursor 4} {3215 ns} 0}
-quietly wave cursor active 1
+WaveRestoreCursors {{Cursor 8} {4545 ns} 0} {{Cursor 3} {2540 ns} 0} {{Cursor 4} {681 ns} 0}
+quietly wave cursor active 2
configure wave -namecolwidth 250
configure wave -valuecolwidth 189
configure wave -justifyvalue left
@@ -383,4 +346,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
-WaveRestoreZoom {4209 ns} {4657 ns}
+WaveRestoreZoom {2313 ns} {2789 ns}
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 36d859071..45fdf9e0f 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -31,8 +31,7 @@
module lsu (
input logic clk, reset,
input logic StallM, FlushM, StallW, FlushW,
- output logic DataStall,
- output logic HPTWReady,
+ output logic DCacheStall,
// Memory Stage
// connected to cpu (controls)
@@ -72,15 +71,17 @@ module lsu (
// mmu management
// page table walker
- input logic [`XLEN-1:0] PageTableEntryM,
- input logic [1:0] PageTypeM,
input logic [`XLEN-1:0] SATP_REGW, // from csr
input logic STATUS_MXR, STATUS_SUM, // from csr
- input logic DTLBWriteM,
- output logic DTLBMissM,
- input logic DisableTranslation, // used to stop intermediate PTE physical addresses being saved to TLB.
-
+ input logic [`XLEN-1:0] PCF,
+ input logic ITLBMissF,
+ output logic [`XLEN-1:0] PageTableEntryF,
+ output logic [1:0] PageTypeF,
+ output logic ITLBWriteF,
+ output logic WalkerInstrPageFaultF,
+ output logic WalkerLoadPageFaultM,
+ output logic WalkerStorePageFaultM,
output logic DTLBHitM, // not connected
@@ -119,14 +120,106 @@ module lsu (
logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; // *** these are just so that the mmu has somewhere to put these outputs since they aren't used in dmem
// *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete.
+ logic DTLBMissM;
+ logic [`XLEN-1:0] PageTableEntryM;
+ logic [1:0] PageTypeM;
+ logic DTLBWriteM;
+ logic [`XLEN-1:0] MMUReadPTE;
+ logic MMUReady;
+ logic HPTWStall;
+ logic [`XLEN-1:0] MMUPAdr;
+ logic MMUTranslate;
+ logic HPTWRead;
+ logic [1:0] MemRWMtoLSU;
+ logic [2:0] Funct3MtoLSU;
+ logic [1:0] AtomicMtoLSU;
+ logic [`XLEN-1:0] MemAdrMtoLSU;
+ logic [`XLEN-1:0] WriteDataMtoLSU;
+ logic [`XLEN-1:0] ReadDataWFromLSU;
+ logic StallWtoLSU;
+ logic CommittedMfromLSU;
+ logic SquashSCWfromLSU;
+ logic DataMisalignedMfromLSU;
+ logic HPTWReady;
+ logic LSUStall;
+ logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB.
+
+
+
+
// for time being until we have a dcache the AHB Lite read bus HRDATAW will be connected to the
// CPU's read data input ReadDataW.
- assign ReadDataW = HRDATAW;
+ assign ReadDataWFromLSU = HRDATAW;
+
+
+ pagetablewalker pagetablewalker(
+ .clk(clk),
+ .reset(reset),
+ .SATP_REGW(SATP_REGW),
+ .PCF(PCF),
+ .MemAdrM(MemAdrM),
+ .ITLBMissF(ITLBMissF),
+ .DTLBMissM(DTLBMissM),
+ .MemRWM(MemRWM),
+ .PageTableEntryF(PageTableEntryF),
+ .PageTableEntryM(PageTableEntryM),
+ .PageTypeF(PageTypeF),
+ .PageTypeM(PageTypeM),
+ .ITLBWriteF(ITLBWriteF),
+ .DTLBWriteM(DTLBWriteM),
+ .MMUReadPTE(MMUReadPTE),
+ .MMUReady(HPTWReady),
+ .HPTWStall(HPTWStall),
+ .MMUPAdr(MMUPAdr),
+ .MMUTranslate(MMUTranslate),
+ .HPTWRead(HPTWRead),
+ .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
+ .WalkerLoadPageFaultM(WalkerLoadPageFaultM),
+ .WalkerStorePageFaultM(WalkerStorePageFaultM));
+
+
+
+ // arbiter between IEU and pagetablewalker
+ lsuArb arbiter(.clk(clk),
+ .reset(reset),
+ // HPTW connection
+ .HPTWTranslate(MMUTranslate),
+ .HPTWRead(HPTWRead),
+ .HPTWPAdr(MMUPAdr),
+ .HPTWReadPTE(MMUReadPTE),
+ .HPTWStall(HPTWStall),
+ // CPU connection
+ .MemRWM(MemRWM),
+ .Funct3M(Funct3M),
+ .AtomicM(AtomicM),
+ .MemAdrM(MemAdrM),
+ .WriteDataM(WriteDataM), // *** Need to remove this.
+ .StallW(StallW),
+ .ReadDataW(ReadDataW),
+ .CommittedM(CommittedM),
+ .SquashSCW(SquashSCW),
+ .DataMisalignedM(DataMisalignedM),
+ .DCacheStall(DCacheStall),
+ // LSU
+ .DisableTranslation(DisableTranslation),
+ .MemRWMtoLSU(MemRWMtoLSU),
+ .Funct3MtoLSU(Funct3MtoLSU),
+ .AtomicMtoLSU(AtomicMtoLSU),
+ .MemAdrMtoLSU(MemAdrMtoLSU),
+ .WriteDataMtoLSU(WriteDataMtoLSU), // *** ??????????????
+ .StallWtoLSU(StallWtoLSU),
+ .CommittedMfromLSU(CommittedMfromLSU),
+ .SquashSCWfromLSU(SquashSCWfromLSU),
+ .DataMisalignedMfromLSU(DataMisalignedMfromLSU),
+ .ReadDataWFromLSU(ReadDataWFromLSU),
+ .DataStall(LSUStall));
+
+
mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0))
- dmmu(.TLBAccessType(MemRWM),
- .VirtualAddress(MemAdrM),
- .Size(Funct3M[1:0]),
+ dmmu(.TLBAccessType(MemRWMtoLSU),
+ .VirtualAddress(MemAdrMtoLSU),
+ .Size(Funct3MtoLSU[1:0]),
.PTEWriteVal(PageTableEntryM),
.PageTypeWriteVal(PageTypeM),
.TLBWrite(DTLBWriteM),
@@ -137,45 +230,46 @@ module lsu (
.TLBPageFault(DTLBPageFaultM),
.ExecuteAccessF(1'b0),
.AtomicAccessM(AtomicMaskedM[1]),
- .WriteAccessM(MemRWM[0]),
- .ReadAccessM(MemRWM[1]),
+ .WriteAccessM(MemRWMtoLSU[0]),
+ .ReadAccessM(MemRWMtoLSU[1]),
.SquashBusAccess(DSquashBusAccessM),
+ .DisableTranslation(DisableTranslation),
// .SelRegions(DHSELRegionsM),
.*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist?
// Specify which type of page fault is occurring
- assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWM[1];
- assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWM[0];
+ assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoLSU[1];
+ assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoLSU[0];
// Determine if an Unaligned access is taking place
always_comb
- case(Funct3M[1:0])
- 2'b00: DataMisalignedM = 0; // lb, sb, lbu
- 2'b01: DataMisalignedM = MemAdrM[0]; // lh, sh, lhu
- 2'b10: DataMisalignedM = MemAdrM[1] | MemAdrM[0]; // lw, sw, flw, fsw, lwu
- 2'b11: DataMisalignedM = |MemAdrM[2:0]; // ld, sd, fld, fsd
+ case(Funct3MtoLSU[1:0])
+ 2'b00: DataMisalignedMfromLSU = 0; // lb, sb, lbu
+ 2'b01: DataMisalignedMfromLSU = MemAdrMtoLSU[0]; // lh, sh, lhu
+ 2'b10: DataMisalignedMfromLSU = MemAdrMtoLSU[1] | MemAdrMtoLSU[0]; // lw, sw, flw, fsw, lwu
+ 2'b11: DataMisalignedMfromLSU = |MemAdrMtoLSU[2:0]; // ld, sd, fld, fsd
endcase
// Squash unaligned data accesses and failed store conditionals
// *** this is also the place to squash if the cache is hit
- // Changed DataMisalignedM to a larger combination of trap sources
+ // Changed DataMisalignedMfromLSU to a larger combination of trap sources
// NonBusTrapM is anything that the bus doesn't contribute to producing
// By contrast, using TrapM results in circular logic errors
- assign MemReadM = MemRWM[1] & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
- assign MemWriteM = MemRWM[0] & ~NonBusTrapM & ~DTLBMissM & ~SquashSCM & CurrState != STATE_STALLED;
- assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicM : 2'b00 ;
+ assign MemReadM = MemRWMtoLSU[1] & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
+ assign MemWriteM = MemRWMtoLSU[0] & ~NonBusTrapM & ~DTLBMissM & ~SquashSCM & CurrState != STATE_STALLED;
+ assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicMtoLSU : 2'b00 ;
assign MemAccessM = MemReadM | MemWriteM;
// Determine if M stage committed
// Reset whenever unstalled. Set when access successfully occurs
- flopr #(1) committedMreg(clk,reset,(CommittedM | CommitM) & StallM,preCommittedM);
- assign CommittedM = preCommittedM | CommitM;
+ flopr #(1) committedMreg(clk,reset,(CommittedMfromLSU | CommitM) & StallM,preCommittedM);
+ assign CommittedMfromLSU = preCommittedM | CommitM;
// Determine if address is valid
- assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1];
- assign LoadAccessFaultM = MemRWM[1];
- assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0];
- assign StoreAccessFaultM = MemRWM[0];
+ assign LoadMisalignedFaultM = DataMisalignedMfromLSU & MemRWMtoLSU[1];
+ assign LoadAccessFaultM = MemRWMtoLSU[1];
+ assign StoreMisalignedFaultM = DataMisalignedMfromLSU & MemRWMtoLSU[0];
+ assign StoreAccessFaultM = MemRWMtoLSU[0];
// Handle atomic load reserved / store conditional
generate
@@ -184,9 +278,9 @@ module lsu (
logic ReservationValidM, ReservationValidW;
logic lrM, scM, WriteAdrMatchM;
- assign lrM = MemReadM && AtomicM[0];
- assign scM = MemRWM[0] && AtomicM[0];
- assign WriteAdrMatchM = MemRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW;
+ assign lrM = MemReadM && AtomicMtoLSU[0];
+ assign scM = MemRWMtoLSU[0] && AtomicMtoLSU[0];
+ assign WriteAdrMatchM = MemRWMtoLSU[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW;
assign SquashSCM = scM && ~WriteAdrMatchM;
always_comb begin // ReservationValidM (next value of valid reservation)
if (lrM) ReservationValidM = 1; // set valid on load reserve
@@ -195,15 +289,15 @@ module lsu (
end
flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW);
- flopenrc #(1) squashreg(clk, reset, FlushW, ~StallW, SquashSCM, SquashSCW);
+ flopenrc #(1) squashreg(clk, reset, FlushW, ~StallWtoLSU, SquashSCM, SquashSCWfromLSU);
end else begin // Atomic operations not supported
assign SquashSCM = 0;
- assign SquashSCW = 0;
+ assign SquashSCWfromLSU = 0;
end
endgenerate
// Data stall
- //assign DataStall = (NextState == STATE_FETCH) || (NextState == STATE_FETCH_AMO_1) || (NextState == STATE_FETCH_AMO_2);
+ //assign LSUStall = (NextState == STATE_FETCH) || (NextState == STATE_FETCH_AMO_1) || (NextState == STATE_FETCH_AMO_2);
assign HPTWReady = (CurrState == STATE_READY);
@@ -224,22 +318,22 @@ module lsu (
STATE_READY:
if (DTLBMissM) begin
NextState = STATE_PTW_READY;
- DataStall = 1'b1;
+ LSUStall = 1'b1;
end else if (AtomicMaskedM[1]) begin
NextState = STATE_FETCH_AMO_1; // *** should be some misalign check
- DataStall = 1'b1;
- end else if((MemReadM & AtomicM[0]) | (MemWriteM & AtomicM[0])) begin
+ LSUStall = 1'b1;
+ end else if((MemReadM & AtomicMtoLSU[0]) | (MemWriteM & AtomicMtoLSU[0])) begin
NextState = STATE_FETCH_AMO_2;
- DataStall = 1'b1;
- end else if (MemAccessM & ~DataMisalignedM) begin
+ LSUStall = 1'b1;
+ end else if (MemAccessM & ~DataMisalignedMfromLSU) begin
NextState = STATE_FETCH;
- DataStall = 1'b1;
+ LSUStall = 1'b1;
end else begin
NextState = STATE_READY;
- DataStall = 1'b0;
+ LSUStall = 1'b0;
end
STATE_FETCH_AMO_1: begin
- DataStall = 1'b1;
+ LSUStall = 1'b1;
if (MemAckW) begin
NextState = STATE_FETCH_AMO_2;
end else begin
@@ -247,45 +341,45 @@ module lsu (
end
end
STATE_FETCH_AMO_2: begin
- DataStall = 1'b1;
- if (MemAckW & ~StallW) begin
+ LSUStall = 1'b1;
+ if (MemAckW & ~StallWtoLSU) begin
NextState = STATE_FETCH_AMO_2;
- end else if (MemAckW & StallW) begin
+ end else if (MemAckW & StallWtoLSU) begin
NextState = STATE_STALLED;
end else begin
NextState = STATE_FETCH_AMO_2;
end
end
STATE_FETCH: begin
- DataStall = 1'b1;
- if (MemAckW & ~StallW) begin
+ LSUStall = 1'b1;
+ if (MemAckW & ~StallWtoLSU) begin
NextState = STATE_READY;
- end else if (MemAckW & StallW) begin
+ end else if (MemAckW & StallWtoLSU) begin
NextState = STATE_STALLED;
end else begin
NextState = STATE_FETCH;
end
end
STATE_STALLED: begin
- DataStall = 1'b0;
- if (~StallW) begin
+ LSUStall = 1'b0;
+ if (~StallWtoLSU) begin
NextState = STATE_READY;
end else begin
NextState = STATE_STALLED;
end
end
STATE_PTW_READY: begin
- DataStall = 1'b0;
+ LSUStall = 1'b0;
if (DTLBWriteM) begin
NextState = STATE_READY;
- end else if (MemReadM & ~DataMisalignedM) begin
+ end else if (MemReadM & ~DataMisalignedMfromLSU) begin
NextState = STATE_PTW_FETCH;
end else begin
NextState = STATE_PTW_READY;
end
end
STATE_PTW_FETCH : begin
- DataStall = 1'b1;
+ LSUStall = 1'b1;
if (MemAckW & ~DTLBWriteM) begin
NextState = STATE_PTW_READY;
end else if (MemAckW & DTLBWriteM) begin
@@ -298,15 +392,15 @@ module lsu (
NextState = STATE_READY;
end
default: begin
- DataStall = 1'b0;
+ LSUStall = 1'b0;
NextState = STATE_READY;
end
endcase
end // always_comb
// *** for now just pass through size
- assign Funct3MfromLSU = Funct3M;
- assign StallWfromLSU = StallW;
+ assign Funct3MfromLSU = Funct3MtoLSU;
+ assign StallWfromLSU = StallWtoLSU;
endmodule
diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv
index 76d89798a..3f57cabb4 100644
--- a/wally-pipelined/src/lsu/lsuArb.sv
+++ b/wally-pipelined/src/lsu/lsuArb.sv
@@ -35,7 +35,6 @@ module lsuArb
input logic [`XLEN-1:0] HPTWPAdr,
// to page table walker.
output logic [`XLEN-1:0] HPTWReadPTE,
- output logic HPTWReady,
output logic HPTWStall,
// from CPU
@@ -65,7 +64,6 @@ module lsuArb
input logic SquashSCWfromLSU,
input logic DataMisalignedMfromLSU,
input logic [`XLEN-1:0] ReadDataWFromLSU,
- input logic HPTWReadyfromLSU,
input logic DataStall
);
@@ -159,7 +157,6 @@ module lsuArb
assign CommittedM = SelPTW ? 1'b0 : CommittedMfromLSU;
assign SquashSCW = SelPTW ? 1'b0 : SquashSCWfromLSU;
assign DataMisalignedM = SelPTW ? 1'b0 : DataMisalignedMfromLSU;
- assign HPTWReady = HPTWReadyfromLSU;
// *** need to rename DcacheStall and Datastall.
// not clear at all. I think it should be LSUStall from the LSU,
// which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one).
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 9a678189b..89486d8b8 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -128,11 +128,7 @@ module wallypipelinedhart
// IMem stalls
logic ICacheStallF;
logic DCacheStall;
- logic [`XLEN-1:0] MMUPAdr, MMUReadPTE;
- logic MMUTranslate, MMUReady;
- logic HPTWRead;
- logic HPTWReadyfromLSU;
- logic HPTWStall;
+
// bus interface to dmem
@@ -145,7 +141,6 @@ module wallypipelinedhart
logic [`PA_BITS-1:0] InstrPAdrF;
logic [`XLEN-1:0] InstrRData;
logic InstrReadF;
- logic DataStall;
logic InstrAckF, MemAckW;
logic CommitM, CommittedM;
@@ -162,7 +157,6 @@ module wallypipelinedhart
logic [`XLEN-1:0] HRDATAW;
// IEU vs HPTW arbitration signals to send to LSU
- logic DisableTranslation;
logic [1:0] MemRWMtoLSU;
logic [2:0] Funct3MtoLSU;
logic [1:0] AtomicMtoLSU;
@@ -186,87 +180,23 @@ module wallypipelinedhart
// mux2 #(`XLEN) OutputInput2mux(WriteDataM, FWriteDataM, FMemRWM[0], WriteDatatmpM);
- pagetablewalker pagetablewalker(
- .clk(clk),
- .reset(reset),
- .SATP_REGW(SATP_REGW), // already on lsu port
- .PCF(PCF), // add to lsu port
- .MemAdrM(MemAdrM), // alreayd on lsu port
- .ITLBMissF(ITLBMissF), // add to lsu port
- .DTLBMissM(DTLBMissM), // already on lsu port convert to internal
- .MemRWM(MemRWM), // already on lsu port
- .PageTableEntryF(PageTableEntryF), // add to lsu port
- .PageTableEntryM(PageTableEntryM), // already on lsu port convert to internal
- .PageTypeF(PageTypeF), // add to lsu port connects to ifu
- .PageTypeM(PageTypeM), // already on lsu port convert to internal
- .ITLBWriteF(ITLBWriteF), // add to lsu port connects to ifu
- .DTLBWriteM(DTLBWriteM), // already on lsu port convert to internal
- .MMUReadPTE(MMUReadPTE), // from lsu arb convert to internal
- .MMUReady(MMUReady), // to lsu arb, convert to internal
- .HPTWStall(HPTWStall), // from lsu arb convert to internal
- .MMUPAdr(MMUPAdr), // to lsu arb, convert to internal
- .MMUTranslate(MMUTranslate), // to lsu arb, convert to internal
- .HPTWRead(HPTWRead), // to lsu arb, convert to internal
- .WalkerInstrPageFaultF(WalkerInstrPageFaultF), // add to lsu port
- .WalkerLoadPageFaultM(WalkerLoadPageFaultM), // add to lsu port (to privilege)
- .WalkerStorePageFaultM(WalkerStorePageFaultM)); // add to lsu port (to privilege)
-
-
-
- // arbiter between IEU and pagetablewalker
- lsuArb arbiter(.clk(clk),
- .reset(reset),
- // HPTW connection
- .HPTWTranslate(MMUTranslate),
- .HPTWRead(HPTWRead),
- .HPTWPAdr(MMUPAdr),
- .HPTWReadPTE(MMUReadPTE),
- .HPTWReady(MMUReady),
- .HPTWStall(HPTWStall),
- // CPU connection
- .MemRWM(MemRWM),
- .Funct3M(Funct3M),
- .AtomicM(AtomicM),
- .MemAdrM(MemAdrM),
- .WriteDataM(WriteDataM),
- .StallW(StallW),
- .ReadDataW(ReadDataW),
- .CommittedM(CommittedM),
- .SquashSCW(SquashSCW),
- .DataMisalignedM(DataMisalignedM),
- .DCacheStall(DCacheStall),
- // LSU
- .DisableTranslation(DisableTranslation),
- .MemRWMtoLSU(MemRWMtoLSU),
- .Funct3MtoLSU(Funct3MtoLSU),
- .AtomicMtoLSU(AtomicMtoLSU),
- .MemAdrMtoLSU(MemAdrMtoLSU),
- .WriteDataMtoLSU(WriteDataMtoLSU),
- .StallWtoLSU(StallWtoLSU),
- .CommittedMfromLSU(CommittedMfromLSU),
- .SquashSCWfromLSU(SquashSCWfromLSU),
- .DataMisalignedMfromLSU(DataMisalignedMfromLSU),
- .ReadDataWFromLSU(ReadDataWFromLSU),
- .HPTWReadyfromLSU(HPTWReadyfromLSU),
- .DataStall(DataStall));
-
lsu lsu(.clk(clk),
.reset(reset),
.StallM(StallM),
.FlushM(FlushM),
- .StallW(StallWtoLSU),
+ .StallW(StallW),
.FlushW(FlushW),
// connected to arbiter (reconnect to CPU)
- .MemRWM(MemRWMtoLSU), // change to MemRWM
- .Funct3M(Funct3MtoLSU), // change to Funct3M
- .AtomicM(AtomicMtoLSU), // change to AtomicMtoLSU
- .CommittedM(CommittedMfromLSU), // change to CommitttedM
- .SquashSCW(SquashSCWfromLSU), // change to SquashSCW
- .DataMisalignedM(DataMisalignedMfromLSU), // change to DataMisalignedM
- .MemAdrM(MemAdrMtoLSU), // change to MemAdrM
- .WriteDataM(WriteDataMtoLSU), // change to WriteDataM
- .ReadDataW(ReadDataWFromLSU), // change to ReadDataW
+ .MemRWM(MemRWM),
+ .Funct3M(Funct3M),
+ .AtomicM(AtomicM),
+ .CommittedM(CommittedM),
+ .SquashSCW(SquashSCW),
+ .DataMisalignedM(DataMisalignedM),
+ .MemAdrM(MemAdrM),
+ .WriteDataM(WriteDataM),
+ .ReadDataW(ReadDataW),
// connected to ahb (all stay the same)
.CommitM(CommitM),
@@ -308,16 +238,18 @@ module wallypipelinedhart
.PMPStoreAccessFaultM(PMPStoreAccessFaultM),
// connected to hptw. Move to internal.
- .PageTableEntryM(PageTableEntryM),
- .PageTypeM(PageTypeM),
- .DTLBWriteM(DTLBWriteM), // from hptw.
- .DTLBMissM(DTLBMissM), // to hptw from dmmu
- .DisableTranslation(DisableTranslation), // from hptw to dmmu
- .HPTWReady(HPTWReadyfromLSU), // from hptw, remove
+ .PCF(PCF),
+ .ITLBMissF(ITLBMissF),
+ .PageTableEntryF(PageTableEntryF),
+ .PageTypeF(PageTypeF),
+ .ITLBWriteF(ITLBWriteF),
+ .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
+ .WalkerLoadPageFaultM(WalkerLoadPageFaultM),
+ .WalkerStorePageFaultM(WalkerStorePageFaultM),
.DTLBHitM(DTLBHitM), // not connected remove
- .DataStall(DataStall)) // change to DCacheStall
+ .DCacheStall(DCacheStall)) // change to DCacheStall
;