Reduced icache to 1 port memory.

wally-pipelined/regression/wave.do

@@ -203,7 +203,6 @@ add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbenc
 add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/AlignedInstrRawD
 add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FlushDLastCyclen
 add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/InstrRawD
-add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCNextPF
 add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF
 add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF
 add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPFinalF
@@ -223,8 +222,10 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
+add wave -noupdate /testbench/dut/hart/ifu/icache/PCTagF
+add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {5796691 ns} 0} {{Cursor 4} {1318991 ns} 0}
+WaveRestoreCursors {{Cursor 2} {9951515 ns} 0} {{Cursor 4} {1318991 ns} 0}
 quietly wave cursor active 1
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 513
@@ -240,4 +241,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {5795108 ns} {5798036 ns}
+WaveRestoreZoom {9951431 ns} {9951599 ns}

wally-pipelined/src/cache/sram1rw.sv

@@ -0,0 +1,21 @@
+// Depth is number of bits in one "word" of the memory, width is number of such words
+module sram1rw #(parameter DEPTH=128, WIDTH=256) (
+    input logic 		    clk,
+    // port 1 is read only
+    input logic [$clog2(WIDTH)-1:0] Addr,
+    output logic [DEPTH-1:0] 	    ReadData,
+  
+    // port 2 is write only
+    input logic [DEPTH-1:0] 	    WriteData,
+    input logic 		    WriteEnable
+);
+
+    logic [WIDTH-1:0][DEPTH-1:0] StoredData;
+
+    always_ff @(posedge clk) begin
+        ReadData <= StoredData[Addr];
+        if (WriteEnable) begin
+            StoredData[Addr] <= WriteData;
+        end
+    end
+endmodule

wally-pipelined/src/ifu/icache.sv

@@ -54,12 +54,10 @@ module icache(
 
     // Input signals to cache memory
     logic                       FlushMem;
-    logic [`XLEN-1:12]          ICacheMemReadUpperPAdr;
-    logic [11:0]                ICacheMemReadLowerAdr;
     logic                       ICacheMemWriteEnable;
     logic [ICACHELINESIZE-1:0]  ICacheMemWriteData;
-    logic [`XLEN-1:0]           ICacheMemWritePAdr;
     logic                       EndFetchState;
+    logic [`XLEN-1:0]           PCTagF, PCNextIndexF;  
     // Output signals from cache memory
     logic [31:0]   ICacheMemReadData;
     logic               ICacheMemReadValid;
@@ -69,13 +67,9 @@ module icache(
   cachemem(
         .*,
         // Stall it if the pipeline is stalled, unless we're stalling it and we're ending our stall
-        .re(ICacheReadEn),
         .flush(FlushMem),
-        .ReadUpperPAdr(ICacheMemReadUpperPAdr),
-        .ReadLowerAdr(ICacheMemReadLowerAdr),
         .WriteEnable(ICacheMemWriteEnable),
         .WriteLine(ICacheMemWriteData),
-        .WritePAdr(ICacheMemWritePAdr),
         .DataWord(ICacheMemReadData),
         .DataValid(ICacheMemReadValid)
     );
@@ -95,19 +89,18 @@ module icachecontroller #(parameter LINESIZE = 256) (
     // Input the address to read
     // The upper bits of the physical pc
     input logic [`XLEN-1:0] 	PCNextF,
-    input logic [`XLEN-1:0]     PCPF,
+    input logic [`XLEN-1:0] 	PCPF,
     // Signals to/from cache memory
     // The read coming out of it
     input logic [31:0] 		ICacheMemReadData,
     input logic 		ICacheMemReadValid,
     // The address at which we want to search the cache memory
-    output logic [`XLEN-1:12] 	ICacheMemReadUpperPAdr,
+    output logic [`XLEN-1:0] 	PCTagF,
-    output logic [11:0] 	ICacheMemReadLowerAdr,
+    output logic [`XLEN-1:0]    PCNextIndexF,						     
     output logic 		ICacheReadEn,
     // Load data into the cache
     output logic 		ICacheMemWriteEnable,
     output logic [LINESIZE-1:0] ICacheMemWriteData,
-    output logic [`XLEN-1:0] 	ICacheMemWritePAdr,
 
     // Outputs to rest of ifu
     // High if the instruction in the fetch stage is compressed
@@ -214,6 +207,8 @@ module icachecontroller #(parameter LINESIZE = 256) (
   //logic [`XLEN-1:0] 	     PCPF;
 
   logic 		     reset_q;
+  logic [1:0] 		     PCMux_q;
+  
   
     // Misaligned signals
     //logic [`XLEN:0] MisalignedInstrRawF;
@@ -231,7 +226,16 @@ module icachecontroller #(parameter LINESIZE = 256) (
   assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf
   assign PCPFinalF = PCMux[1] ? PCSpillF : PCPreFinalF;
 
+  // this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later.
+  // *** read enable may not be necessary.
+  flopenr #(2) PCMuxReg(.clk(clk),
+			.reset(reset),
+			.en(ICacheReadEn),
+			.d(PCMux),
+			.q(PCMux_q));
   
+  assign PCTagF = PCMux_q[1] ? PCSpillF : PCPF;
+  assign PCNextIndexF = PCPFinalF;
   
   // truncate the offset from PCPF for memory address generation
   assign PCPTrunkF = PCPFinalF[`XLEN-1:OFFSETWIDTH];
@@ -512,10 +516,4 @@ module icachecontroller #(parameter LINESIZE = 256) (
   //assign InstrRawD = AlignedInstrRawD;
 
   
-  assign {ICacheMemReadUpperPAdr, ICacheMemReadLowerAdr} = PCPFinalF;
-
-  assign ICacheMemWritePAdr = PCPFinalF;
-
-  
-  
 endmodule

wally-pipelined/src/ifu/icacheMem.sv

@@ -2,21 +2,20 @@
 
 module rodirectmappedmemre #(parameter NUMLINES=512, parameter LINESIZE = 256, parameter WORDSIZE = `XLEN) (
     // Pipeline stuff
-    input  logic clk,
+    input logic 	       clk,
-    input  logic reset,
+    input logic 	       reset,
-    input  logic re,
     // If flush is high, invalidate the entire cache
-    input  logic flush,
+    input logic 	       flush,
+													    
     // Select which address to read (broken for efficiency's sake)
-    input  logic [`XLEN-1:12]   ReadUpperPAdr, // physical address Must come one cycle later
+    input logic [`XLEN-1:0]    PCTagF, // physical tag address
-    input  logic [11:0]         ReadLowerAdr, // virtual address
+    input logic [`XLEN-1:0]    PCNextIndexF,
     // Write new data to the cache
-    input  logic                WriteEnable,
+    input logic 	       WriteEnable,
-    input  logic [LINESIZE-1:0] WriteLine,
+    input logic [LINESIZE-1:0] WriteLine,
-    input  logic [`XLEN-1:0]    WritePAdr,
     // Output the word, as well as if it is valid
-    output logic [31:0] DataWord, // *** was WORDSIZE-1
+    output logic [31:0]        DataWord, // *** was WORDSIZE-1
-    output logic                DataValid
+    output logic 	       DataValid
 );
 
     // Various compile-time constants
@@ -33,11 +32,6 @@ module rodirectmappedmemre #(parameter NUMLINES=512, parameter LINESIZE = 256, p
     localparam integer TAGEND = TAGBEGIN + TAGWIDTH - 1;
 
     // Machinery to read from and write to the correct addresses in memory
-    logic [`XLEN-1:0]       ReadPAdr;
-    logic [`XLEN-1:0]       OldReadPAdr;
-    logic [OFFSETWIDTH-1:0] ReadOffset, WriteOffset;
-    logic [SETWIDTH-1:0]    ReadSet, WriteSet;
-    logic [TAGWIDTH-1:0]    ReadTag, WriteTag;
     logic [LINESIZE-1:0]    ReadLine;
     logic [LINESIZE/WORDSIZE-1:0][WORDSIZE-1:0] ReadLineTransformed;
 
@@ -46,41 +40,25 @@ module rodirectmappedmemre #(parameter NUMLINES=512, parameter LINESIZE = 256, p
     logic [NUMLINES-1:0]    ValidOut;
     logic                   DataValidBit;
 
-    flopenr #(`XLEN) ReadPAdrFlop(clk, reset, re, ReadPAdr, OldReadPAdr);
-
-    // Assign the read and write addresses in cache memory
-    always_comb begin
-        ReadOffset = OldReadPAdr[OFFSETEND:OFFSETBEGIN];
-        ReadPAdr = {ReadUpperPAdr, ReadLowerAdr};
-        ReadSet = ReadPAdr[SETEND:SETBEGIN];
-        ReadTag = OldReadPAdr[TAGEND:TAGBEGIN];
-
-        WriteOffset = WritePAdr[OFFSETEND:OFFSETBEGIN];
-        WriteSet = WritePAdr[SETEND:SETBEGIN];
-        WriteTag = WritePAdr[TAGEND:TAGBEGIN];
-    end
-
     // Depth is number of bits in one "word" of the memory, width is number of such words
-    Sram1Read1Write #(.DEPTH(LINESIZE), .WIDTH(NUMLINES)) cachemem (
+    sram1rw #(.DEPTH(LINESIZE), .WIDTH(NUMLINES)) cachemem (
         .*,
-        .ReadAddr(ReadSet),
+        .Addr(PCNextIndexF[SETEND:SETBEGIN]),
         .ReadData(ReadLine),
-        .WriteAddr(WriteSet),
         .WriteData(WriteLine)
     );
-    Sram1Read1Write #(.DEPTH(TAGWIDTH), .WIDTH(NUMLINES)) cachetags (
+    sram1rw #(.DEPTH(TAGWIDTH), .WIDTH(NUMLINES)) cachetags (
         .*,
-        .ReadAddr(ReadSet),
+        .Addr(PCNextIndexF[SETEND:SETBEGIN]),
         .ReadData(DataTag),
-        .WriteAddr(WriteSet),
+        .WriteData(PCTagF[TAGEND:TAGBEGIN])
-        .WriteData(WriteTag)
     );
 
     // Pick the right bits coming out the read line
     //assign DataWord = ReadLineTransformed[ReadOffset];
   //logic [31:0] tempRD;
   always_comb begin
-    case (OldReadPAdr[4:1])
+    case (PCTagF[4:1])
       0: DataWord = ReadLine[31:0];
       1: DataWord = ReadLine[47:16];
       2: DataWord = ReadLine[63:32];
@@ -115,10 +93,10 @@ module rodirectmappedmemre #(parameter NUMLINES=512, parameter LINESIZE = 256, p
             ValidOut <= {NUMLINES{1'b0}};
         end else begin
             if (WriteEnable) begin
-                ValidOut[WriteSet] <= 1;
+                ValidOut[PCNextIndexF[SETEND:SETBEGIN]] <= 1;
             end
         end
-        DataValidBit <= ValidOut[ReadSet];
+        DataValidBit <= ValidOut[PCNextIndexF[SETEND:SETBEGIN]];
     end
-    assign DataValid = DataValidBit && (DataTag == ReadTag);
+    assign DataValid = DataValidBit && (DataTag == PCTagF[TAGEND:TAGBEGIN]);
 endmodule