diff --git a/tests/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py b/tests/testgen/imperas/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py
similarity index 100%
rename from tests/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py
rename to tests/testgen/imperas/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py
diff --git a/tests/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py b/tests/testgen/imperas/testgen-ADDI-XORI-ORI-ANDI-SLTI.py
similarity index 100%
rename from tests/testgen/testgen-ADDI-XORI-ORI-ANDI-SLTI.py
rename to tests/testgen/imperas/testgen-ADDI-XORI-ORI-ANDI-SLTI.py
diff --git a/tests/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py b/tests/testgen/imperas/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py
similarity index 100%
rename from tests/testgen/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py
rename to tests/testgen/imperas/testgen-ADDIW-SLLIW-SRLIW-SRAIW.py
diff --git a/tests/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py b/tests/testgen/imperas/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py
similarity index 100%
rename from tests/testgen/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py
rename to tests/testgen/imperas/testgen-ADDW-SUBW-SLLW-SRLW-SRAW.py
diff --git a/tests/testgen/testgen-BRANCH.py b/tests/testgen/imperas/testgen-BRANCH.py
similarity index 100%
rename from tests/testgen/testgen-BRANCH.py
rename to tests/testgen/imperas/testgen-BRANCH.py
diff --git a/tests/testgen/testgen-CSR.py b/tests/testgen/imperas/testgen-CSR.py
similarity index 100%
rename from tests/testgen/testgen-CSR.py
rename to tests/testgen/imperas/testgen-CSR.py
diff --git a/tests/testgen/testgen-JAL-JALR.py b/tests/testgen/imperas/testgen-JAL-JALR.py
similarity index 100%
rename from tests/testgen/testgen-JAL-JALR.py
rename to tests/testgen/imperas/testgen-JAL-JALR.py
diff --git a/tests/testgen/testgen-LOAD.py b/tests/testgen/imperas/testgen-LOAD.py
similarity index 100%
rename from tests/testgen/testgen-LOAD.py
rename to tests/testgen/imperas/testgen-LOAD.py
diff --git a/tests/testgen/testgen-PIPELINE.py b/tests/testgen/imperas/testgen-PIPELINE.py
similarity index 100%
rename from tests/testgen/testgen-PIPELINE.py
rename to tests/testgen/imperas/testgen-PIPELINE.py
diff --git a/tests/testgen/testgen-SLL-SRL-SRA.py b/tests/testgen/imperas/testgen-SLL-SRL-SRA.py
similarity index 100%
rename from tests/testgen/testgen-SLL-SRL-SRA.py
rename to tests/testgen/imperas/testgen-SLL-SRL-SRA.py
diff --git a/tests/testgen/testgen-SLLI-SRLI-SRAI.py b/tests/testgen/imperas/testgen-SLLI-SRLI-SRAI.py
similarity index 100%
rename from tests/testgen/testgen-SLLI-SRLI-SRAI.py
rename to tests/testgen/imperas/testgen-SLLI-SRLI-SRAI.py
diff --git a/tests/testgen/testgen-SLTIU.py b/tests/testgen/imperas/testgen-SLTIU.py
similarity index 100%
rename from tests/testgen/testgen-SLTIU.py
rename to tests/testgen/imperas/testgen-SLTIU.py
diff --git a/tests/testgen/testgen-STORE.py b/tests/testgen/imperas/testgen-STORE.py
similarity index 100%
rename from tests/testgen/testgen-STORE.py
rename to tests/testgen/imperas/testgen-STORE.py
diff --git a/tests/testgen/testgen-VIRTUALMEMORY.py b/tests/testgen/imperas/testgen-VIRTUALMEMORY.py
similarity index 100%
rename from tests/testgen/testgen-VIRTUALMEMORY.py
rename to tests/testgen/imperas/testgen-VIRTUALMEMORY.py
diff --git a/tests/testgen/imperas/testgen_footer.S b/tests/testgen/imperas/testgen_footer.S
new file mode 100644
index 000000000..f7cc0b18b
--- /dev/null
+++ b/tests/testgen/imperas/testgen_footer.S
@@ -0,0 +1,18 @@
+	# ---------------------------------------------------------------------------------------------
+	
+	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	RV_COMPLIANCE_HALT
+
+RV_COMPLIANCE_CODE_END
+
+# Input data section.
+	.data
+
+
+# Output data section.
+RV_COMPLIANCE_DATA_BEGIN
+
+test_1_res:
diff --git a/tests/testgen/imperas/testgen_header.S b/tests/testgen/imperas/testgen_header.S
new file mode 100644
index 000000000..118042a5c
--- /dev/null
+++ b/tests/testgen/imperas/testgen_header.S
@@ -0,0 +1,38 @@
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+// Adapted from Imperas RISCV-TEST_SUITE
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "riscv_test_macros.h"
+#include "compliance_test.h"
+#include "compliance_io.h"
+
+RV_COMPLIANCE_RV64M
+
+RV_COMPLIANCE_CODE_BEGIN
+
+
+	RVTEST_IO_INIT
+	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
+	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
+
+	# ---------------------------------------------------------------------------------------------
+
+	#RVTEST_IO_WRITE_STR(x31, "# Test group 1\n")
+
+
+    # address for test results
+    la x6, test_1_res
+		
\ No newline at end of file
diff --git a/tests/testgen/testgen_footer.S b/tests/testgen/testgen_footer.S
index f7cc0b18b..b0137b792 100644
--- a/tests/testgen/testgen_footer.S
+++ b/tests/testgen/testgen_footer.S
@@ -1,18 +1,46 @@
-	# ---------------------------------------------------------------------------------------------
-	
-	RVTEST_IO_WRITE_STR(x31, "Test End\n")
+RVTEST_CODE_END
+RVMODEL_HALT
 
-	# ---------------------------------------------------------------------------------------------
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+RVTEST_DATA_END
 
-	RV_COMPLIANCE_HALT
-
-RV_COMPLIANCE_CODE_END
-
-# Input data section.
-	.data
+RVMODEL_DATA_BEGIN
 
 
-# Output data section.
-RV_COMPLIANCE_DATA_BEGIN
+signature_x8_0:
+    .fill 0*(XLEN/32),4,0xdeadbeef
 
-test_1_res:
+
+signature_x8_1:
+    .fill 19*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_0:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 256*(XLEN/32),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 148*(XLEN/32),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+
+mtrap_sigptr:
+    .fill 64*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*(XLEN/32),4,0xdeadbeef
+
+#endif
+
+RVMODEL_DATA_END
diff --git a/tests/testgen/testgen_header.S b/tests/testgen/testgen_header.S
index 118042a5c..3b3bd6876 100644
--- a/tests/testgen/testgen_header.S
+++ b/tests/testgen/testgen_header.S
@@ -1,6 +1,5 @@
 //
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-// Adapted from Imperas RISCV-TEST_SUITE
 //
 // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
 // files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
@@ -15,24 +14,18 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
-#include "riscv_test_macros.h"
-#include "compliance_test.h"
-#include "compliance_io.h"
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV64I")
 
-RV_COMPLIANCE_RV64M
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
 
-RV_COMPLIANCE_CODE_BEGIN
+#ifdef TEST_CASE_1
 
+RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add)
 
-	RVTEST_IO_INIT
-	RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
-	RVTEST_IO_WRITE_STR(x31, "Test Begin\n")
-
-	# ---------------------------------------------------------------------------------------------
-
-	#RVTEST_IO_WRITE_STR(x31, "# Test group 1\n")
-
-
-    # address for test results
-    la x6, test_1_res
-		
\ No newline at end of file
+RVTEST_SIGBASE( x8,signature_x8_1)
diff --git a/tests/testgen/wally-I.py b/tests/testgen/wally-I.py
new file mode 100755
index 000000000..b186e21c5
--- /dev/null
+++ b/tests/testgen/wally-I.py
@@ -0,0 +1,153 @@
+#!/usr/bin/python3
+##################################
+# wally-I.py
+#
+# David_Harris@hmc.edu 27 October 2021
+#
+# Generate directed and random test vectors for RISC-V Design Validation.
+##################################
+
+##################################
+# libraries
+##################################
+from datetime import datetime
+from random import randint 
+from random import seed
+from random import getrandbits
+
+##################################
+# functions
+##################################
+
+def twoscomp(a):
+  amsb = a >> (xlen-1)
+  alsbs = ((1 << (xlen-1)) - 1) & a
+  if (amsb):
+      asigned = a - (1<<xlen)
+  else:
+      asigned = a
+  #print("a: " + str(a) + " amsb: "+str(amsb)+ " alsbs: " + str(alsbs) + " asigned: "+str(asigned))
+  return asigned
+
+def computeExpected(a, b, test, xlen):
+  asigned = twoscomp(a)
+  bsigned = twoscomp(b)
+
+  if (test == "ADD"):
+    return a + b
+  elif (test == "SUB"):
+    return a - b
+  elif (test == "SLT"):
+    return asigned < bsigned
+  elif (test == "SLTU"):
+    return a < b
+  elif (test == "XOR"):
+    return a ^ b
+  elif (test == "OR"):
+    return a | b
+  elif (test == "AND"):
+    return a & b
+  else:
+    die("bad test name ", test)
+  #  exit(1)
+
+def randRegs():
+  reg1 = randint(1,31)
+  reg2 = randint(1,31)
+  reg3 = randint(1,31) 
+  if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
+    return randRegs()
+  else:
+      return reg1, reg2, reg3
+
+def writeVector(a, b, storecmd, xlen):
+  global testnum
+  expected = computeExpected(a, b, test, xlen)
+  expected = expected % 2**xlen # drop carry if necessary
+  if (expected < 0): # take twos complement
+    expected = 2**xlen + expected
+  reg1, reg2, reg3 = randRegs()
+  lines = "\n# Testcase " + str(testnum) + ":  rs1:x" + str(reg1) + "(" + formatstr.format(a)
+  lines = lines + "), rs2:x" + str(reg2) + "(" +formatstr.format(b) 
+  lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n"
+  lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
+  lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n"
+  lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n"
+  lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n"
+  lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg3) +", "+formatstr.format(expected)+")\n"
+  f.write(lines)
+  if (xlen == 32):
+    line = formatrefstr.format(expected)+"\n"
+  else:
+    line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
+  r.write(line)
+  testnum = testnum+1
+
+##################################
+# main body
+##################################
+
+# change these to suite your tests
+instrs = ["ADD", "SUB", "SLT", "SLTU", "XOR", "OR", "AND"]
+author = "David_Harris@hmc.edu"
+xlens = [32, 64]
+numrand = 100
+
+# setup
+seed(0) # make tests reproducible
+
+# generate files for each test
+for xlen in xlens:
+  formatstrlen = str(int(xlen/4))
+  formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
+  formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
+  if (xlen == 32):
+    storecmd = "sw"
+    wordsize = 4
+  else:
+    storecmd = "sd"
+    wordsize = 8
+  pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/"
+  fname = pathname + "src/WALLY-PIPELINE.S"
+  testnum = 0
+
+  # print custom header part
+  f = open(fname, "w")
+#  r = open(refname, "w")
+  line = "///////////////////////////////////////////\n"
+  f.write(line)
+  lines="// "+fname+ "\n// " + author + "\n"
+  f.write(lines)
+  line ="// Created " + str(datetime.now()) 
+  f.write(line)
+
+  # insert generic header
+  h = open("testgen_header.S", "r")
+  for line in h:  
+    f.write(line)
+
+  # print directed and random test vectors
+  # for a in corners:
+  #   for b in corners:
+  #     writeVector(a, b, storecmd, xlen)
+  # for i in range(0,numrand):
+  #   a = getrandbits(xlen)
+  #   b = getrandbits(xlen)
+  #   writeVector(a, b, storecmd, xlen)
+
+
+  # print footer
+  h = open("testgen_footer.S", "r")
+  for line in h:  
+    f.write(line)
+
+  # Finish
+#  lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
+#  lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
+  f.write(lines)
+  f.close()
+#  r.close()
+
+
+
+
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag
index 9331e7e14..e2cdf44da 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/Makefrag
@@ -28,7 +28,7 @@
 # Description: Makefrag for RV32I architectural tests
 
 rv32i_sc_tests = \
-
+	       WALLY-PIPELINE \
 
 rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))
 
diff --git a/wally-pipelined/regression/sim-wally-batch b/wally-pipelined/regression/sim-wally-batch
index 4b627b768..c603b8432 100755
--- a/wally-pipelined/regression/sim-wally-batch
+++ b/wally-pipelined/regression/sim-wally-batch
@@ -1,3 +1,3 @@
 vsim -c <<!
-do wally-pipelined-batch.do rv32g arch32f
+do wally-pipelined-batch.do rv64g arch64d
 !
diff --git a/wally-pipelined/testbench/testbench.sv b/wally-pipelined/testbench/testbench.sv
index e7f7e1f5d..8c25f1549 100644
--- a/wally-pipelined/testbench/testbench.sv
+++ b/wally-pipelined/testbench/testbench.sv
@@ -83,6 +83,7 @@ logic [3:0] dummy;
         "arch64priv":                     tests = arch64priv;
         "arch64c":      if (`C_SUPPORTED) tests = arch64c;
         "arch64m":      if (`M_SUPPORTED) tests = arch64m;
+        "arch64d":      if (`D_SUPPORTED) tests = arch64d;
         "imperas64i":                     tests = imperas64i;
         "imperas64p":                     tests = imperas64p;
         "imperas64mmu": if (`MEM_VIRTMEM) tests = imperas64mmu;
diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh
index 57de30760..c99d64b62 100644
--- a/wally-pipelined/testbench/tests.vh
+++ b/wally-pipelined/testbench/tests.vh
@@ -636,6 +636,181 @@ string imperas32f[] = '{
     "rv64i_m/I/xori-01", "6010"
   };
 
+
+  string arch64d[] = '{
+    `RISCVARCHTEST,
+    "rv64i_m/D/d_fadd_b10-01", "8690",
+    "rv64i_m/D/d_fadd_b1-01", "8430",
+    "rv64i_m/D/d_fadd_b11-01", "74da0",
+    "rv64i_m/D/d_fadd_b12-01", "2350",
+    "rv64i_m/D/d_fadd_b13-01", "3cb0",
+    "rv64i_m/D/d_fadd_b2-01", "5160",
+    "rv64i_m/D/d_fadd_b3-01", "d640",
+    "rv64i_m/D/d_fadd_b4-01", "3900",
+    "rv64i_m/D/d_fadd_b5-01", "3d50",
+    "rv64i_m/D/d_fadd_b7-01", "5530",
+    "rv64i_m/D/d_fadd_b8-01", "11c10",
+    "rv64i_m/D/d_fclass_b1-01", "2110",
+    "rv64i_m/D/d_fcvt.d.l_b25-01", "2110",
+    "rv64i_m/D/d_fcvt.d.l_b26-01", "2220",
+    "rv64i_m/D/d_fcvt.d.lu_b25-01", "2110",
+    "rv64i_m/D/d_fcvt.d.lu_b26-01", "2220",
+    "rv64i_m/D/d_fcvt.d.s_b1-01", "2110",
+    "rv64i_m/D/d_fcvt.d.s_b22-01", "2110",
+    "rv64i_m/D/d_fcvt.d.s_b23-01", "2110",
+    "rv64i_m/D/d_fcvt.d.s_b24-01", "2110",
+    "rv64i_m/D/d_fcvt.d.s_b27-01", "2110",
+    "rv64i_m/D/d_fcvt.d.s_b28-01", "2110",
+    "rv64i_m/D/d_fcvt.d.s_b29-01", "2110",
+    "rv64i_m/D/d_fcvt.d.w_b25-01", "2120",
+    "rv64i_m/D/d_fcvt.d.w_b26-01", "2220",
+    "rv64i_m/D/d_fcvt.d.wu_b25-01", "2110",
+    "rv64i_m/D/d_fcvt.d.wu_b26-01", "2220",
+    "rv64i_m/D/d_fcvt.l.d_b1-01", "2120",
+    "rv64i_m/D/d_fcvt.l.d_b22-01", "2260",
+    "rv64i_m/D/d_fcvt.l.d_b23-01", "2180",
+    "rv64i_m/D/d_fcvt.l.d_b24-01", "2360",
+    "rv64i_m/D/d_fcvt.l.d_b27-01", "2110",
+    "rv64i_m/D/d_fcvt.l.d_b28-01", "2120",
+    "rv64i_m/D/d_fcvt.l.d_b29-01", "22a0",
+    "rv64i_m/D/d_fcvt.lu.d_b1-01", "2120",
+    "rv64i_m/D/d_fcvt.lu.d_b22-01", "2260",
+    "rv64i_m/D/d_fcvt.lu.d_b23-01", "2180",
+    "rv64i_m/D/d_fcvt.lu.d_b24-01", "2360",
+    "rv64i_m/D/d_fcvt.lu.d_b27-01", "2120",
+    "rv64i_m/D/d_fcvt.lu.d_b28-01", "2120",
+    "rv64i_m/D/d_fcvt.lu.d_b29-01", "22a0",
+    "rv64i_m/D/d_fcvt.s.d_b1-01", "2110",
+    "rv64i_m/D/d_fcvt.s.d_b22-01", "2110",
+    "rv64i_m/D/d_fcvt.s.d_b23-01", "2180",
+    "rv64i_m/D/d_fcvt.s.d_b24-01", "2360",
+    "rv64i_m/D/d_fcvt.s.d_b27-01", "2110",
+    "rv64i_m/D/d_fcvt.s.d_b28-01", "2110",
+    "rv64i_m/D/d_fcvt.s.d_b29-01", "22a0",
+    "rv64i_m/D/d_fcvt.w.d_b1-01", "2120",
+    "rv64i_m/D/d_fcvt.w.d_b22-01", "2160",
+    "rv64i_m/D/d_fcvt.w.d_b23-01", "2180",
+    "rv64i_m/D/d_fcvt.w.d_b24-01", "2360",
+    "rv64i_m/D/d_fcvt.w.d_b27-01", "2120",
+    "rv64i_m/D/d_fcvt.w.d_b28-01", "2120",
+    "rv64i_m/D/d_fcvt.w.d_b29-01", "22a0",
+    "rv64i_m/D/d_fcvt.wu.d_b1-01", "2120",
+    "rv64i_m/D/d_fcvt.wu.d_b22-01", "2160",
+    "rv64i_m/D/d_fcvt.wu.d_b23-01", "2180",
+    "rv64i_m/D/d_fcvt.wu.d_b24-01", "2360",
+    "rv64i_m/D/d_fcvt.wu.d_b27-01", "2120",
+    "rv64i_m/D/d_fcvt.wu.d_b28-01", "2120",
+    "rv64i_m/D/d_fcvt.wu.d_b29-01", "22a0",
+    "rv64i_m/D/d_fdiv_b1-01", "8430",
+    "rv64i_m/D/d_fdiv_b20-01", "3fa0",
+    "rv64i_m/D/d_fdiv_b2-01", "5170",
+    "rv64i_m/D/d_fdiv_b21-01", "8a70",
+    "rv64i_m/D/d_fdiv_b3-01", "d630",
+    "rv64i_m/D/d_fdiv_b4-01", "38f0",
+    "rv64i_m/D/d_fdiv_b5-01", "3d50",
+    "rv64i_m/D/d_fdiv_b6-01", "38f0",
+    "rv64i_m/D/d_fdiv_b7-01", "5530",
+    "rv64i_m/D/d_fdiv_b8-01", "11c10",
+    "rv64i_m/D/d_fdiv_b9-01", "1b0f0",
+    "rv64i_m/D/d_feq_b1-01", "7430",
+    "rv64i_m/D/d_feq_b19-01", "c4c0",
+    "rv64i_m/D/d_fld-align-01", "2010",
+    "rv64i_m/D/d_fle_b1-01", "7430",
+    "rv64i_m/D/d_fle_b19-01", "c4c0",
+    "rv64i_m/D/d_flt_b1-01", "7430",
+    "rv64i_m/D/d_flt_b19-01", "d800",
+    "rv64i_m/D/d_fmadd_b14-01", "3fd0",
+    "rv64i_m/D/d_fmadd_b16-01", "43b0",
+    "rv64i_m/D/d_fmadd_b17-01", "43b0",
+    "rv64i_m/D/d_fmadd_b18-01", "5a20",
+    "rv64i_m/D/d_fmadd_b2-01", "5ab0",
+    "rv64i_m/D/d_fmadd_b3-01", "119d0",
+    "rv64i_m/D/d_fmadd_b4-01", "3df0",
+    "rv64i_m/D/d_fmadd_b5-01", "4480",
+    "rv64i_m/D/d_fmadd_b6-01", "3df0",
+    "rv64i_m/D/d_fmadd_b7-01", "6050",
+    "rv64i_m/D/d_fmadd_b8-01", "15aa0",
+    "rv64i_m/D/d_fmax_b1-01", "8430",
+    "rv64i_m/D/d_fmax_b19-01", "d5c0",
+    "rv64i_m/D/d_fmin_b1-01", "8430",
+    "rv64i_m/D/d_fmin_b19-01", "d4b0",
+    "rv64i_m/D/d_fmsub_b14-01", "3fd0",
+    "rv64i_m/D/d_fmsub_b16-01", "43b0",
+    "rv64i_m/D/d_fmsub_b17-01", "43b0",
+    "rv64i_m/D/d_fmsub_b18-01", "5a20",
+    "rv64i_m/D/d_fmsub_b2-01", "5ab0",
+    "rv64i_m/D/d_fmsub_b3-01", "119f0",
+    "rv64i_m/D/d_fmsub_b4-01", "3df0",
+    "rv64i_m/D/d_fmsub_b5-01", "4480",
+    "rv64i_m/D/d_fmsub_b6-01", "3df0",
+    "rv64i_m/D/d_fmsub_b7-01", "6050",
+    "rv64i_m/D/d_fmsub_b8-01", "15aa0",
+    "rv64i_m/D/d_fmul_b1-01", "8430",
+    "rv64i_m/D/d_fmul_b2-01", "5180",
+    "rv64i_m/D/d_fmul_b3-01", "d640",
+    "rv64i_m/D/d_fmul_b4-01", "38f0",
+    "rv64i_m/D/d_fmul_b5-01", "3d50",
+    "rv64i_m/D/d_fmul_b6-01", "38f0",
+    "rv64i_m/D/d_fmul_b7-01", "5540",
+    "rv64i_m/D/d_fmul_b8-01", "11c10",
+    "rv64i_m/D/d_fmul_b9-01", "1b0f0",
+    "rv64i_m/D/d_fmv.d.x_b25-01", "2110",
+    "rv64i_m/D/d_fmv.d.x_b26-01", "2220",
+    "rv64i_m/D/d_fmv.x.d_b1-01", "2120",
+    "rv64i_m/D/d_fmv.x.d_b22-01", "2110",
+    "rv64i_m/D/d_fmv.x.d_b23-01", "2110",
+    "rv64i_m/D/d_fmv.x.d_b24-01", "2120",
+    "rv64i_m/D/d_fmv.x.d_b27-01", "2120",
+    "rv64i_m/D/d_fmv.x.d_b28-01", "2110",
+    "rv64i_m/D/d_fmv.x.d_b29-01", "2120",
+    "rv64i_m/D/d_fnmadd_b14-01", "3fd0",
+    "rv64i_m/D/d_fnmadd_b16-01", "4390",
+    "rv64i_m/D/d_fnmadd_b17-01", "4390",
+    "rv64i_m/D/d_fnmadd_b18-01", "5a20",
+    "rv64i_m/D/d_fnmadd_b2-01", "5ab0",
+    "rv64i_m/D/d_fnmadd_b3-01", "119d0",
+    "rv64i_m/D/d_fnmadd_b4-01", "3df0",
+    "rv64i_m/D/d_fnmadd_b5-01", "4480",
+    "rv64i_m/D/d_fnmadd_b6-01", "3df0",
+    "rv64i_m/D/d_fnmadd_b7-01", "6050",
+    "rv64i_m/D/d_fnmadd_b8-01", "15aa0",
+    "rv64i_m/D/d_fnmsub_b14-01", "3fd0",
+    "rv64i_m/D/d_fnmsub_b16-01", "4390",
+    "rv64i_m/D/d_fnmsub_b17-01", "4390",
+    "rv64i_m/D/d_fnmsub_b18-01", "5a20",
+    "rv64i_m/D/d_fnmsub_b2-01", "5aa0",
+    "rv64i_m/D/d_fnmsub_b3-01", "119d0",
+    "rv64i_m/D/d_fnmsub_b4-01", "3e20",
+    "rv64i_m/D/d_fnmsub_b5-01", "4480",
+    "rv64i_m/D/d_fnmsub_b6-01", "3e10",
+    "rv64i_m/D/d_fnmsub_b7-01", "6050",
+    "rv64i_m/D/d_fnmsub_b8-01", "15aa0",
+    "rv64i_m/D/d_fsd-align-01", "2010",
+    "rv64i_m/D/d_fsgnj_b1-01", "8430",
+    "rv64i_m/D/d_fsgnjn_b1-01", "8430",
+    "rv64i_m/D/d_fsgnjx_b1-01", "8430",
+    "rv64i_m/D/d_fsqrt_b1-01", "2110",
+    "rv64i_m/D/d_fsqrt_b20-01", "3460",
+    "rv64i_m/D/d_fsqrt_b2-01", "2190",
+    "rv64i_m/D/d_fsqrt_b3-01", "2120",
+    "rv64i_m/D/d_fsqrt_b4-01", "2110",
+    "rv64i_m/D/d_fsqrt_b5-01", "2110",
+    "rv64i_m/D/d_fsqrt_b7-01", "2110",
+    "rv64i_m/D/d_fsqrt_b8-01", "2110",
+    "rv64i_m/D/d_fsqrt_b9-01", "4c10",
+    "rv64i_m/D/d_fsub_b10-01", "8660",
+    "rv64i_m/D/d_fsub_b1-01", "8440",
+    "rv64i_m/D/d_fsub_b11-01", "74da0",
+    "rv64i_m/D/d_fsub_b12-01", "2350",
+    "rv64i_m/D/d_fsub_b13-01", "3cb0",
+    "rv64i_m/D/d_fsub_b2-01", "5160",
+    "rv64i_m/D/d_fsub_b3-01", "d630",
+    "rv64i_m/D/d_fsub_b4-01", "38f0",
+    "rv64i_m/D/d_fsub_b5-01", "3d50",
+    "rv64i_m/D/d_fsub_b7-01", "5530",
+    "rv64i_m/D/d_fsub_b8-01", "11c10"
+  };
+
     string arch32priv[] = '{
     `RISCVARCHTEST,
     "rv32i_m/privilege/ebreak", "2070",
@@ -669,7 +844,6 @@ string imperas32f[] = '{
    };
 
   string arch32f[] = '{
-
     `RISCVARCHTEST,
     // "rv32i_m/F/fadd_b1-01", "7220",
     // "rv32i_m/F/fadd_b10-01", "2270",