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Removed all old references to the old flash card controller.

Browse Source 
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
This commit is contained in:
Ross Thompson 2023-07-24 15:45:57 -05:00
parent d418e4fa5e
commit 717833b11a
16 changed files with 25 additions and 1505 deletions
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3
.gitmodules vendored
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@ -30,3 +30,6 @@
[submodule "addins/vivado-boards"]
path = addins/vivado-boards
url = https://github.com/Digilent/vivado-boards/
[submodule "addins/vivado-risc-v"]
path = addins/vivado-risc-v
url = https://github.com/eugene-tarassov/vivado-risc-v.git

1
addins/vivado-risc-v Submodule

@ -0,0 +1 @@
Subproject commit c76a8613a177b3a04face2cb8e15dd07a8d2fc40

11
config/fpga/config.vh
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@ -130,14 +130,9 @@ localparam PLIC_SUPPORTED = 1'b1;
localparam logic [63:0] PLIC_BASE = 64'h0C000000;
localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF;
localparam SDC_SUPPORTED = 1'b0;
localparam logic [63:0] SDC_BASE = 64'h00012100;
localparam logic [63:0] SDC_RANGE = 64'h0000001F;
// Temporary Boot Process Stuff
localparam SDC2_SUPPORTED = 1'b1;
localparam logic [63:0] SDC2_BASE = 64'h00013000;
localparam logic [63:0] SDC2_RANGE = 64'h0000007F;
localparam SDC_SUPPORTED = 1'b1;
localparam logic [63:0] SDC_BASE = 64'h00013000;
localparam logic [63:0] SDC_RANGE = 64'h0000007F;
// Test modes

3
config/shared/parameter-defs.vh
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@ -72,9 +72,6 @@ parameter cvw_t P = '{
SDC_SUPPORTED : SDC_SUPPORTED,
SDC_BASE : SDC_BASE,
SDC_RANGE : SDC_RANGE,
SDC2_SUPPORTED : SDC2_SUPPORTED,
SDC2_BASE : SDC2_BASE,
SDC2_RANGE : SDC2_RANGE,
GPIO_LOOPBACK_TEST : GPIO_LOOPBACK_TEST,
UART_PRESCALE : UART_PRESCALE ,
PLIC_NUM_SRC : PLIC_NUM_SRC,

9
fpga/generator/wally.tcl
View File

@ -41,9 +41,14 @@ if {$board=="ArtyA7"} {
# read in all other rtl
read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
read_verilog [glob -type f ../../pipelined/src/uncore/newsdc/*.v]
# *** Once the sdc is updated to use ahb changes these to system verilog.
read_verilog [glob -type f ../src/axi_sdc_controller.v]
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_cmd_master.v]
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_cmd_serial_host.v]
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_master.v]
read_verilog [glob -type f ../../addins/vivado-risc-v/sdc/sd_data_serial_host.v]
set_property include_dirs {../../config/fpga ../../config/shared} [current_fileset]
set_property include_dirs {../../config/fpga ../../config/shared ../../addins/vivado-risc-v/sdc} [current_fileset]
if {$board=="ArtyA7"} {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc

0
pipelined/src/uncore/newsdc/axi_sdc_controller.v → fpga/src/axi_sdc_controller.v
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502
pipelined/src/uncore/newsdc/license.txt
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@ -1,502 +0,0 @@
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That's all there is to it!

152
pipelined/src/uncore/newsdc/sd_cmd_master.v
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@ -1,152 +0,0 @@
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013-2022 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from https://www.gnu.org/licenses/ ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "sd_defines.h"
module sd_cmd_master(
input clock,
input clock_posedge,
input reset,
input start,
input int_status_rst,
output [1:0] setting,
output reg start_xfr,
output reg go_idle,
output reg [39:0] cmd,
input [119:0] response,
input crc_error,
input index_ok,
input finish,
input busy, // direct signal from data sd data input (data[0])
//input card_detect,
input [31:0] argument,
input [`CMD_REG_SIZE-1:0] command,
input [`CMD_TIMEOUT_W-1:0] timeout,
output [`INT_CMD_SIZE-1:0] int_status,
output reg [31:0] response_0,
output reg [31:0] response_1,
output reg [31:0] response_2,
output reg [31:0] response_3
);
reg expect_response;
reg long_response;
reg [`INT_CMD_SIZE-1:0] int_status_reg;
reg [`CMD_TIMEOUT_W-1:0] watchdog;
reg watchdog_enable;
reg [2:0] state;
parameter IDLE = 3'b001;
parameter EXECUTE = 3'b010;
parameter BUSY_CHECK = 3'b100;
assign setting[1:0] = {long_response, expect_response};
assign int_status = state == IDLE ? int_status_reg : 5'h0;
always @(posedge clock) begin
if (reset) begin
response_0 <= 0;
response_1 <= 0;
response_2 <= 0;
response_3 <= 0;
int_status_reg <= 0;
expect_response <= 0;
long_response <= 0;
cmd <= 0;
start_xfr <= 0;
watchdog <= 0;
watchdog_enable <= 0;
go_idle <= 0;
state <= IDLE;
end else if (clock_posedge) begin
case (state)
IDLE: begin
go_idle <= 0;
if (command[`CMD_RESPONSE_CHECK] == 2'b10 || command[`CMD_RESPONSE_CHECK] == 2'b11) begin
expect_response <= 1;
long_response <= 1;
end else if (command[`CMD_RESPONSE_CHECK] == 2'b01) begin
expect_response <= 1;
long_response <= 0;
end else begin
expect_response <= 0;
long_response <= 0;
end
cmd[39:38] <= 2'b01;
cmd[37:32] <= command[`CMD_INDEX];
cmd[31:0] <= argument;
watchdog <= 0;
watchdog_enable <= timeout != 0;
if (start) begin
start_xfr <= 1;
int_status_reg <= 0;
state <= EXECUTE;
end
end
EXECUTE: begin
start_xfr <= 0;
if (watchdog_enable && watchdog >= timeout) begin
int_status_reg[`INT_CMD_CTE] <= 1;
int_status_reg[`INT_CMD_EI] <= 1;
go_idle <= 1;
state <= IDLE;
end else if (finish) begin
if (command[`CMD_CRC_CHECK] && crc_error) begin
int_status_reg[`INT_CMD_CCRCE] <= 1;
int_status_reg[`INT_CMD_EI] <= 1;
end
if (command[`CMD_IDX_CHECK] && !index_ok) begin
int_status_reg[`INT_CMD_CIE] <= 1;
int_status_reg[`INT_CMD_EI] <= 1;
end
int_status_reg[`INT_CMD_CC] <= 1;
if (expect_response) begin
response_0 <= response[119:88];
response_1 <= response[87:56];
response_2 <= response[55:24];
response_3 <= {response[23:0], 8'h00};
end
if (command[`CMD_BUSY_CHECK]) state <= BUSY_CHECK;
else state <= IDLE;
end else if (watchdog_enable) begin
watchdog <= watchdog + 1;
end
end
BUSY_CHECK: begin
if (!busy) state <= IDLE;
end
endcase
if (int_status_rst)
int_status_reg <= 0;
end
end
endmodule

263
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@ -1,263 +0,0 @@
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013-2022 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from https://www.gnu.org/licenses/ ////
//// ////
//////////////////////////////////////////////////////////////////////
module sd_cmd_serial_host (
//---------------Input ports---------------
input clock,
input clock_posedge,
input clock_data_in,
input reset,
input [1:0] setting,
input [39:0] cmd,
input start,
input cmd_i,
//---------------Output ports---------------
output reg [119:0] response,
output reg finish,
output reg crc_ok,
output reg index_ok,
output reg cmd_oe,
output reg cmd_o
);
//-------------Internal Constant-------------
parameter INIT_DELAY = 4;
parameter BITS_TO_SEND = 48;
parameter CMD_SIZE = 40;
parameter RESP_SIZE = 128;
//---------------Internal variable-----------
reg cmd_dat_reg;
integer resp_len;
reg with_response;
reg [CMD_SIZE-1:0] cmd_buff;
reg [RESP_SIZE-1:0] resp_buff;
integer resp_idx;
//CRC
reg crc_rst;
reg [6:0]crc_in;
wire [6:0] crc_val;
reg crc_enable;
reg crc_bit;
reg crc_match;
//-Internal Counterns
integer counter;
//-State Machine
parameter
STATE_SIZE = 8,
INIT = 8'b00000001,
IDLE = 8'b00000010,
SETUP_CRC = 8'b00000100,
WRITE = 8'b00001000,
READ_WAIT = 8'b00010000,
READ = 8'b00100000,
FINISH_WR = 8'b01000000,
FINISH_WO = 8'b10000000;
reg [STATE_SIZE-1:0] state;
//Misc
`define cmd_idx (CMD_SIZE-1-counter)
//sd cmd input pad register
always @(posedge clock) begin
if (clock_data_in) cmd_dat_reg <= cmd_i;
end
//------------------------------------------
sd_crc_7 CRC_7(
crc_bit,
crc_enable & clock_posedge,
clock,
crc_rst,
crc_val);
//------------------------------------------
always @(posedge clock) begin
if (reset) begin
resp_len <= 0;
with_response <= 0;
cmd_buff <= 0;
crc_enable <= 0;
resp_idx <= 0;
cmd_oe <= 1;
cmd_o <= 1;
resp_buff <= 0;
finish <= 0;
crc_rst <= 1;
crc_bit <= 0;
crc_in <= 0;
response <= 0;
index_ok <= 0;
crc_ok <= 0;
crc_match <= 0;
counter <= 0;
state <= INIT;
end else if (clock_posedge) begin
case (state)
INIT: begin
counter <= counter+1;
// Pull cmd line up
cmd_oe <= 1;
cmd_o <= 1;
if (counter >= INIT_DELAY) state <= IDLE;
end
IDLE: begin
cmd_oe <= 0;
counter <= 0;
crc_rst <= 1;
crc_enable <= 0;
response <= 0;
resp_idx <= 0;
crc_ok <= 0;
index_ok <= 0;
finish <= 0;
if (start) begin
resp_len <= setting[1] ? 127 : 39;
with_response <= setting[0];
cmd_buff <= cmd;
state <= SETUP_CRC;
end
end
SETUP_CRC: begin
crc_rst <= 0;
crc_enable <= 1;
crc_bit <= cmd_buff[`cmd_idx];
state <= WRITE;
end
WRITE: begin
if (counter < BITS_TO_SEND-8) begin // 1->40 CMD, (41 >= CNT && CNT <=47) CRC, 48 stop_bit
cmd_oe <= 1;
cmd_o <= cmd_buff[`cmd_idx];
if (counter < BITS_TO_SEND-9) begin //1 step ahead
crc_bit <= cmd_buff[`cmd_idx-1];
end else begin
crc_enable <= 0;
end
end else if (counter < BITS_TO_SEND-1) begin
cmd_oe <= 1;
crc_enable <= 0;
cmd_o <= crc_val[BITS_TO_SEND-counter-2];
end else if (counter == BITS_TO_SEND-1) begin
cmd_oe <= 1;
cmd_o <= 1'b1;
end else begin
cmd_oe <= 0;
cmd_o <= 1'b1;
end
counter <= counter + 1;
if (counter >= BITS_TO_SEND && with_response) state <= READ_WAIT;
else if (counter >= BITS_TO_SEND) state <= FINISH_WO;
end
READ_WAIT: begin
crc_enable <= 0;
crc_rst <= 1;
counter <= 1;
cmd_oe <= 0;
resp_buff[RESP_SIZE-1] <= cmd_dat_reg;
if (!cmd_dat_reg) state <= READ;
end
FINISH_WO: begin
finish <= 1;
crc_enable <= 0;
crc_rst <= 1;
counter <= 0;
cmd_oe <= 0;
state <= IDLE;
end
READ: begin
crc_rst <= 0;
crc_enable <= (resp_len != RESP_SIZE-1 || counter > 7);
cmd_oe <= 0;
if (counter <= resp_len) begin
if (counter < 8) //1+1+6 (S,T,Index)
resp_buff[RESP_SIZE-1-counter] <= cmd_dat_reg;
else begin
resp_idx <= resp_idx + 1;
resp_buff[RESP_SIZE-9-resp_idx] <= cmd_dat_reg;
end
crc_bit <= cmd_dat_reg;
end else if (counter-resp_len <= 7) begin
crc_in[(resp_len+7)-(counter)] <= cmd_dat_reg;
crc_enable <= 0;
end else begin
crc_enable <= 0;
crc_match <= crc_in == crc_val;
end
counter <= counter + 1;
if (counter >= resp_len+8) state <= FINISH_WR;
end
FINISH_WR: begin
index_ok <= cmd_buff[37:32] == resp_buff[125:120];
crc_ok <= crc_match;
finish <= 1;
crc_enable <= 0;
crc_rst <= 1;
counter <= 0;
cmd_oe <= 0;
response <= resp_buff[119:0];
state <= IDLE;
end
default:
state <= INIT;
endcase
end
end
endmodule
module sd_crc_7(
input BITVAL, // Next input bit
input ENABLE, // Enable calculation
input BITSTRB, // Current bit valid (Clock)
input CLEAR, // Init CRC value
output reg [6:0] CRC // Current output CRC value
);
wire inv;
assign inv = BITVAL ^ CRC[6];
always @(posedge BITSTRB or posedge CLEAR) begin
if (CLEAR) begin
CRC <= 0;
end else if (ENABLE == 1) begin
CRC[6] <= CRC[5];
CRC[5] <= CRC[4];
CRC[4] <= CRC[3];
CRC[3] <= CRC[2] ^ inv;
CRC[2] <= CRC[1];
CRC[1] <= CRC[0];
CRC[0] <= inv;
end
end
endmodule

150
pipelined/src/uncore/newsdc/sd_data_master.v
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@ -1,150 +0,0 @@
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013-2022 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from https://www.gnu.org/licenses/ ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "sd_defines.h"
module sd_data_master (
input clock,
input clock_posedge,
input reset,
input start_tx,
input start_rx,
input [`DATA_TIMEOUT_W-1:0] timeout,
// Output to SD-Host Reg
output reg d_write,
output reg d_read,
// To fifo filler
(* mark_debug = "true" *) output reg en_tx_fifo,
output reg en_rx_fifo,
(* mark_debug = "true" *) input fifo_empty,
input fifo_ready,
input fifo_full,
(* mark_debug = "true" *) input bus_cycle,
// SD-DATA_Host
input xfr_complete,
input crc_error,
input bus_error,
// status output
output reg [`INT_DATA_SIZE-1:0] int_status,
input int_status_rst
);
reg [3:0] state;
localparam IDLE = 4'b0001;
localparam START_TX_FIFO = 4'b0010;
localparam START_RX_FIFO = 4'b0100;
localparam DATA_TRANSFER = 4'b1000;
(* mark_debug = "true" *) reg [`DATA_TIMEOUT_W-1:0] watchdog;
reg watchdog_enable;
always @(posedge clock) begin
if (reset) begin
en_tx_fifo <= 0;
en_rx_fifo <= 0;
d_write <= 0;
d_read <= 0;
int_status <= 0;
watchdog <= 0;
watchdog_enable <= 0;
state <= IDLE;
end else if (clock_posedge) begin
case (state)
IDLE: begin
en_tx_fifo <= 0;
en_rx_fifo <= 0;
d_write <= 0;
d_read <= 0;
watchdog <= 0;
watchdog_enable <= timeout != 0;
if (start_tx) state <= START_TX_FIFO;
else if (start_rx) state <= START_RX_FIFO;
end
START_RX_FIFO: begin
en_rx_fifo <= 1;
en_tx_fifo <= 0;
d_read <= 1;
if (!xfr_complete) state <= DATA_TRANSFER;
end
START_TX_FIFO: begin
en_rx_fifo <= 0;
en_tx_fifo <= 1;
if (fifo_ready) begin
d_write <= 1;
if (!xfr_complete) state <= DATA_TRANSFER;
end
end
DATA_TRANSFER: begin
d_read <= 0;
d_write <= 0;
if (en_tx_fifo && fifo_empty) begin
int_status[`INT_DATA_CFE] <= 1;
int_status[`INT_DATA_EI] <= 1;
state <= IDLE;
// stop sd_data_serial_host
d_write <= 1;
d_read <= 1;
end else if (en_rx_fifo && fifo_full) begin
int_status[`INT_DATA_CFE] <= 1;
int_status[`INT_DATA_EI] <= 1;
state <= IDLE;
// stop sd_data_serial_host
d_write <= 1;
d_read <= 1;
end else if (watchdog_enable && watchdog >= timeout) begin
int_status[`INT_DATA_CTE] <= 1;
int_status[`INT_DATA_EI] <= 1;
state <= IDLE;
// stop sd_data_serial_host
d_write <= 1;
d_read <= 1;
end else if (xfr_complete && !bus_cycle && (en_tx_fifo || fifo_empty)) begin
state <= IDLE;
if (crc_error) begin
int_status[`INT_DATA_CCRCE] <= 1;
int_status[`INT_DATA_EI] <= 1;
end
if (bus_error) begin
int_status[`INT_DATA_CBE] <= 1;
int_status[`INT_DATA_EI] <= 1;
end
int_status[`INT_DATA_CC] <= 1;
end else if (watchdog_enable) begin
watchdog <= watchdog + 1;
end
end
endcase
if (int_status_rst)
int_status <= 0;
end
end
endmodule

311
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@ -1,311 +0,0 @@
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013-2022 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from https://www.gnu.org/licenses/ ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "sd_defines.h"
module sd_data_serial_host(
input clock,
input clock_posedge,
input clock_data_in,
input reset,
// Tx Fifo
input [31:0] data_in,
output reg rd,
// Rx Fifo
output reg [31:0] data_out,
output reg we,
// tristate data
output reg dat_oe,
output reg[3:0] dat_o,
input [3:0] dat_i,
// Controll signals
input [`BLKSIZE_W-1:0] blksize,
input bus_4bit,
input [`BLKCNT_W-1:0] blkcnt,
input [1:0] start,
input [1:0] byte_alignment,
output sd_data_busy,
output busy,
output reg crc_ok
);
reg [3:0] DAT_dat_reg;
reg bus_4bit_reg;
reg crc_en;
reg crc_rst;
wire [15:0] crc_out [3:0];
reg [`BLKSIZE_W+4-1:0] data_cycles;
reg [`BLKSIZE_W+4-1:0] transf_cnt;
reg [3:0] drt_bit;
reg [3:0] drt_reg;
(* mark_debug = "true" *) reg [`BLKCNT_W-1:0] blkcnt_reg;
reg [1:0] byte_alignment_reg;
reg [3:0] crc_bit;
reg [3:0] last_din;
reg [4:0] data_index;
reg [6:0] state;
parameter IDLE = 7'b0000001;
parameter WRITE_DAT = 7'b0000010;
parameter WRITE_WAIT = 7'b0000100;
parameter WRITE_DRT = 7'b0001000;
parameter WRITE_BUSY = 7'b0010000;
parameter READ_WAIT = 7'b0100000;
parameter READ_DAT = 7'b1000000;
// sd data input pad register
always @(posedge clock) begin
if (clock_data_in) DAT_dat_reg <= dat_i;
end
genvar i;
generate
for (i=0; i<4; i=i+1) begin: CRC_16_gen
sd_crc_16 CRC_16_i (last_din[i], crc_en & clock_posedge, clock, crc_rst, crc_out[i]);
end
endgenerate
assign busy = (state != IDLE);
assign sd_data_busy = !DAT_dat_reg[0];
always @(posedge clock) begin
if (reset) begin
state <= IDLE;
dat_oe <= 0;
crc_en <= 0;
crc_rst <= 1;
transf_cnt <= 0;
rd <= 0;
last_din <= 0;
crc_bit <= 0;
dat_o <= 4'b1111;
drt_bit <= 0;
drt_reg <= 0;
we <= 0;
data_out <= 0;
crc_ok <= 0;
data_index <= 0;
blkcnt_reg <= 0;
byte_alignment_reg <= 0;
data_cycles <= 0;
bus_4bit_reg <= 0;
end else if (clock_posedge) begin
case (state)
IDLE: begin
dat_oe <= 0;
dat_o <= 4'b1111;
transf_cnt <= 0;
crc_en <= 0;
crc_rst <= 1;
crc_bit <= 15;
we <= 0;
rd <= 0;
data_index <= 0;
blkcnt_reg <= blkcnt;
byte_alignment_reg <= byte_alignment;
data_cycles <= (bus_4bit ? {3'b000, blksize, 1'b0} + 2 : {1'b0, blksize, 3'b000} + 8);
bus_4bit_reg <= bus_4bit;
if (start == 2'b01) state <= WRITE_DAT;
else if (start == 2'b10) state <= READ_WAIT;
end
WRITE_DAT: begin
rd <= 0;
transf_cnt <= transf_cnt + 16'h1;
if (transf_cnt == 0) begin
crc_ok <= 0;
crc_bit <= 15;
end else if (transf_cnt == 1) begin
crc_rst <= 0;
crc_en <= 1;
if (bus_4bit_reg) begin
last_din <= {
data_in[31-(byte_alignment_reg << 3)],
data_in[30-(byte_alignment_reg << 3)],
data_in[29-(byte_alignment_reg << 3)],
data_in[28-(byte_alignment_reg << 3)]
};
end else begin
last_din <= {3'h7, data_in[31-(byte_alignment_reg << 3)]};
end
dat_oe <= 1;
dat_o <= bus_4bit_reg ? 4'h0 : 4'he;
data_index <= bus_4bit_reg ? {2'b00, byte_alignment_reg, 1'b1} : {byte_alignment_reg, 3'b001};
end else if (transf_cnt <= data_cycles+1) begin
if (bus_4bit_reg) begin
last_din <= {
data_in[31-(data_index[2:0]<<2)],
data_in[30-(data_index[2:0]<<2)],
data_in[29-(data_index[2:0]<<2)],
data_in[28-(data_index[2:0]<<2)]
};
if (data_index[2:0] == 3'h6 && transf_cnt <= data_cycles-1) rd <= 1;
end else begin
last_din <= {3'h7, data_in[31-data_index]};
if (data_index == 30) rd <= 1;
end
data_index <= data_index + 5'h1;
dat_o <= last_din;
if (transf_cnt == data_cycles+1) crc_en <= 0;
end else if (transf_cnt <= data_cycles+17) begin
crc_en <= 0;
dat_o[0] <= crc_out[0][crc_bit];
if (bus_4bit_reg)
dat_o[3:1] <= {crc_out[3][crc_bit], crc_out[2][crc_bit], crc_out[1][crc_bit]};
crc_bit <= crc_bit - 1;
end else if (transf_cnt == data_cycles+18) begin
dat_o <= 4'hf;
end else if (transf_cnt == data_cycles+19) begin
dat_oe <= 0;
end else begin
state <= WRITE_WAIT;
end
end
WRITE_WAIT: begin
drt_bit <= 0;
if (!DAT_dat_reg[0]) state <= WRITE_DRT;
end
WRITE_DRT: begin
// See 7.3.3.1 Data Response Token
if (drt_bit <= 3) begin
drt_reg[drt_bit] <= DAT_dat_reg[0];
end else if (drt_bit == 15) begin
crc_ok <= drt_reg[3:0] == 4'b1010;
state <= WRITE_BUSY;
end
drt_bit <= drt_bit + 1;
end
WRITE_BUSY: begin
if (DAT_dat_reg[0]) begin
if (blkcnt_reg != 0 && crc_ok) begin
transf_cnt <= 0;
blkcnt_reg <= blkcnt_reg - 1;
byte_alignment_reg <= byte_alignment_reg + blksize[1:0] + 2'b1;
crc_rst <= 1;
state <= WRITE_DAT;
end else begin
state <= IDLE;
end
end
end
READ_WAIT: begin
dat_oe <= 0;
crc_bit <= 15;
last_din <= 0;
transf_cnt <= 0;
data_index <= bus_4bit_reg ? (byte_alignment_reg << 1) : (byte_alignment_reg << 3);
if (!DAT_dat_reg[0]) begin
crc_rst <= 0;
crc_en <= 1;
state <= READ_DAT;
end
end
READ_DAT: begin
last_din <= DAT_dat_reg;
transf_cnt <= transf_cnt + 16'h1;
if (transf_cnt < data_cycles) begin
if (bus_4bit_reg) begin
we <= (data_index[2:0] == 7 || (transf_cnt == data_cycles-1 && !blkcnt_reg));
data_out[31-(data_index[2:0]<<2)] <= DAT_dat_reg[3];
data_out[30-(data_index[2:0]<<2)] <= DAT_dat_reg[2];
data_out[29-(data_index[2:0]<<2)] <= DAT_dat_reg[1];
data_out[28-(data_index[2:0]<<2)] <= DAT_dat_reg[0];
end else begin
we <= (data_index == 31 || (transf_cnt == data_cycles-1 && !blkcnt_reg));
data_out[31-data_index] <= DAT_dat_reg[0];
end
data_index <= data_index + 5'h1;
crc_ok <= 1;
end else if (transf_cnt == data_cycles) begin
crc_en <= 0;
we <= 0;
end else if (transf_cnt <= data_cycles+16) begin
if (crc_out[0][crc_bit] != last_din[0]) crc_ok <= 0;
if (bus_4bit_reg) begin
if (crc_out[1][crc_bit] != last_din[1]) crc_ok <= 0;
if (crc_out[2][crc_bit] != last_din[2]) crc_ok <= 0;
if (crc_out[3][crc_bit] != last_din[3]) crc_ok <= 0;
end
if (crc_bit == 0) begin
byte_alignment_reg <= byte_alignment_reg + blksize[1:0] + 2'b1;
crc_rst <= 1;
end else begin
crc_bit <= crc_bit - 1;
end
end else if (blkcnt_reg != 0 && crc_ok) begin
blkcnt_reg <= blkcnt_reg - 1;
state <= READ_WAIT;
end else begin
state <= IDLE;
end
end
default:
state <= IDLE;
endcase
if (start == 2'b11) state <= IDLE; // Abort
end
end
endmodule
module sd_crc_16(
input BITVAL, // Next input bit
input ENABLE, // Enable calculation
input BITSTRB, // Current bit valid (Clock)
input CLEAR, // Init CRC value
output reg [15:0] CRC // Current output CRC value
);
assign inv = BITVAL ^ CRC[15];
always @(posedge BITSTRB) begin
if (CLEAR) begin
CRC <= 0;
end else if (ENABLE == 1) begin
CRC[15] <= CRC[14];
CRC[14] <= CRC[13];
CRC[13] <= CRC[12];
CRC[12] <= CRC[11] ^ inv;
CRC[11] <= CRC[10];
CRC[10] <= CRC[9];
CRC[9] <= CRC[8];
CRC[8] <= CRC[7];
CRC[7] <= CRC[6];
CRC[6] <= CRC[5];
CRC[5] <= CRC[4] ^ inv;
CRC[4] <= CRC[3];
CRC[3] <= CRC[2];
CRC[2] <= CRC[1];
CRC[1] <= CRC[0];
CRC[0] <= inv;
end
end
endmodule

91
pipelined/src/uncore/newsdc/sd_defines.h
View File

@ -1,91 +0,0 @@
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013-2022 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson (adam.edvardsson@orsoc.se) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from https://www.gnu.org/licenses/ ////
//// ////
//////////////////////////////////////////////////////////////////////
// global defines
`define BLKSIZE_W 12
`define BLKCNT_W 16
`define CMD_TIMEOUT_W 25
`define DATA_TIMEOUT_W 28
// cmd module interrupts
`define INT_CMD_SIZE 5
`define INT_CMD_CC 0
`define INT_CMD_EI 1
`define INT_CMD_CTE 2
`define INT_CMD_CCRCE 3
`define INT_CMD_CIE 4
// data module interrupts
`define INT_DATA_SIZE 6
`define INT_DATA_CC 0
`define INT_DATA_EI 1
`define INT_DATA_CTE 2 // Timeout
`define INT_DATA_CCRCE 3 // CRC error
`define INT_DATA_CFE 4 // FIFO error
`define INT_DATA_CBE 5 // Bus error
// command register defines
`define CMD_REG_SIZE 14
`define CMD_RESPONSE_CHECK 1:0
`define CMD_BUSY_CHECK 2
`define CMD_CRC_CHECK 3
`define CMD_IDX_CHECK 4
`define CMD_WITH_DATA 6:5
`define CMD_INDEX 13:8
// register addreses
`define argument 8'h00
`define command 8'h04
`define resp0 8'h08
`define resp1 8'h0c
`define resp2 8'h10
`define resp3 8'h14
`define data_timeout 8'h18
`define controller 8'h1c
`define cmd_timeout 8'h20
`define clock_d 8'h24
`define reset 8'h28
`define voltage 8'h2c
`define capa 8'h30
`define cmd_isr 8'h34
`define cmd_iser 8'h38
`define data_isr 8'h3c
`define data_iser 8'h40
`define blksize 8'h44
`define blkcnt 8'h48
`define card_detect 8'h4c
`define dst_src_addr 8'h60
`define dst_src_addr_high 8'h64
// register contents
`define RESET_BLOCK_SIZE 12'd511
`define RESET_CLOCK_DIV 124

3
src/cvw.sv
View File

@ -127,9 +127,6 @@ typedef struct packed {
logic SDC_SUPPORTED;
logic [63:0] SDC_BASE;
logic [63:0] SDC_RANGE;
logic SDC2_SUPPORTED;
logic [63:0] SDC2_BASE;
logic [63:0] SDC2_RANGE;
// Test modes

7
src/mmu/adrdecs.sv
View File

@ -32,7 +32,7 @@ module adrdecs import cvw::*; #(parameter cvw_t P) (
input logic [P.PA_BITS-1:0] PhysicalAddress,
input logic AccessRW, AccessRX, AccessRWX,
input logic [1:0] Size,
output logic [11:0] SelRegions
output logic [10:0] SelRegions
);
localparam logic [3:0] SUPPORTED_SIZE = (P.LLEN == 32 ? 4'b0111 : 4'b1111);
@ -46,10 +46,9 @@ module adrdecs import cvw::*; #(parameter cvw_t P) (
adrdec #(P.PA_BITS) gpiodec(PhysicalAddress, P.GPIO_BASE[P.PA_BITS-1:0], P.GPIO_RANGE[P.PA_BITS-1:0], P.GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[4]);
adrdec #(P.PA_BITS) uartdec(PhysicalAddress, P.UART_BASE[P.PA_BITS-1:0], P.UART_RANGE[P.PA_BITS-1:0], P.UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[3]);
adrdec #(P.PA_BITS) plicdec(PhysicalAddress, P.PLIC_BASE[P.PA_BITS-1:0], P.PLIC_RANGE[P.PA_BITS-1:0], P.PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[2]);
adrdec #(P.PA_BITS) sdcdec(PhysicalAddress, P.SDC_BASE[P.PA_BITS-1:0], P.SDC_RANGE[P.PA_BITS-1:0], P.SDC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE & 4'b1100, SelRegions[1]);
adrdec #(P.PA_BITS) newsdc(PhysicalAddress, P.SDC2_BASE[P.PA_BITS-1:0], P.SDC2_RANGE[P.PA_BITS-1:0], P.SDC2_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[11]);
adrdec #(P.PA_BITS) sdcdec(PhysicalAddress, P.SDC_BASE[P.PA_BITS-1:0], P.SDC_RANGE[P.PA_BITS-1:0], P.SDC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[1]);
assign SelRegions[0] = ~|(SelRegions[11:1]); // none of the regions are selected
assign SelRegions[0] = ~|(SelRegions[10:1]); // none of the regions are selected
endmodule
// verilator lint_on UNOPTFLAT

2
src/mmu/pmachecker.sv
View File

@ -43,7 +43,7 @@ module pmachecker import cvw::*; #(parameter cvw_t P) (
logic PMAAccessFault;
logic AccessRW, AccessRWX, AccessRX;
logic [11:0] SelRegions;
logic [10:0] SelRegions;
logic AtomicAllowed;
// Determine what type of access is being made

20
src/uncore/uncore.sv
View File

@ -59,9 +59,9 @@ module uncore import cvw::*; #(parameter cvw_t P)(
logic [P.XLEN-1:0] HREADRam, HREADSDC;
logic [11:0] HSELRegions;
logic [10:0] HSELRegions;
logic HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSDC;
logic HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD;
logic HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD;
logic HRESPRam, HRESPSDC;
logic HREADYRam, HRESPSDCD;
logic [P.XLEN-1:0] HREADBootRom;
@ -88,7 +88,7 @@ module uncore import cvw::*; #(parameter cvw_t P)(
adrdecs #(P) adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
// unswizzle HSEL signals
assign {HSELEXTSDC, HSELDTIM, HSELIROM, HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[11:1];
assign {HSELDTIM, HSELIROM, HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELEXTSDC} = HSELRegions[10:1];
// AHB -> APB bridge
ahbapbbridge #(P, 4) ahbapbbridge (
@ -146,29 +146,21 @@ module uncore import cvw::*; #(parameter cvw_t P)(
assign UARTSout = 0; assign UARTIntr = 0;
end
// eventually remove
assign HREADSDC = '0;
assign HREADYSDC = '1;
assign HRESPSDC = '0;
// AHB Read Multiplexer
assign HRDATA = ({P.XLEN{HSELRamD}} & HREADRam) |
({P.XLEN{HSELEXTD | HSELEXTSDCD}} & HRDATAEXT) |
({P.XLEN{HSELBRIDGED}} & HREADBRIDGE) |
({P.XLEN{HSELBootRomD}} & HREADBootRom) |
({P.XLEN{HSELSDCD}} & HREADSDC);
({P.XLEN{HSELBootRomD}} & HREADBootRom);
assign HRESP = HSELRamD & HRESPRam |
(HSELEXTD | HSELEXTSDCD) & HRESPEXT |
HSELBRIDGE & HRESPBRIDGE |
HSELBootRomD & HRESPBootRom |
HSELSDC & HRESPSDC;
HSELBootRomD & HRESPBootRom;
assign HREADY = HSELRamD & HREADYRam |
(HSELEXTD | HSELEXTSDCD) & HREADYEXT |
HSELBRIDGED & HREADYBRIDGE |
HSELBootRomD & HREADYBootRom |
HSELSDCD & HREADYSDC |
HSELNoneD; // don't lock up the bus if no region is being accessed
// Address Decoder Delay (figure 4-2 in spec)
@ -176,6 +168,6 @@ module uncore import cvw::*; #(parameter cvw_t P)(
// takes more than 1 cycle to repsond it needs to hold on to the old select until the
// device is ready. Hense this register must be selectively enabled by HREADY.
// However on reset None must be seleted.
flopenl #(12) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions[11:0], 12'b1, {HSELEXTSDCD, HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD});
flopenl #(11) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 11'b1, {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELEXTSDCD, HSELNoneD});
flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED);
endmodule