Don't generate HPTW when MEM_VIRTMEM=0

wally-pipelined/config/rv64icfd/wally-config.vh

@@ -46,7 +46,7 @@
 `define MEM_DCACHE 0
 `define MEM_DTIM 1
 `define MEM_ICACHE 0
-`define MEM_VIRTMEM 1
+`define MEM_VIRTMEM 0\1
 `define VECTORED_INTERRUPTS_SUPPORTED 1
 
 `define ITLB_ENTRIES 32

wally-pipelined/src/mmu/pagetablewalker.sv

@@ -70,6 +70,8 @@ module pagetablewalker
    output logic 	    WalkerStorePageFaultM
    );
 
+  generate
+    if (`MEM_VIRTMEM) begin
       // Internal signals
       // register TLBs translation miss requests
       logic [`XLEN-1:0] 	    TranslationVAdrQ;
@@ -175,13 +177,13 @@ module pagetablewalker
       assign PageTypeM = PageType;
 
 
-  generate
+//      generate
         if (`XLEN == 32) begin
           logic [9:0] VPN1, VPN0;
 
           flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
 
-/* -----\/----- EXCLUDED -----\/-----
+    /* -----\/----- EXCLUDED -----\/-----
           assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall;
     -----/\----- EXCLUDED -----/\----- */
 
@@ -549,6 +551,15 @@ module pagetablewalker
           // we support larger physical address spaces
           assign MMUPAdr = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
         end
+      //endgenerate
+    end else begin
+      assign MMUPAdr = 0;
+      assign MMUTranslate = 0;
+      assign HPTWRead = 0;
+      assign WalkerInstrPageFaultF = 0;
+      assign WalkerLoadPageFaultM = 0;
+      assign WalkerStorePageFaultM = 0;
+    end
   endgenerate
 
 endmodule