1
0
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00

Don't generate HPTW when MEM_VIRTMEM=0

This commit is contained in:
David Harris 2021-07-05 23:35:44 -04:00
parent 179c8d3ed4
commit 71711c54c9
2 changed files with 453 additions and 442 deletions
wally-pipelined
config/rv64icfd
src/mmu

View File

@ -46,7 +46,7 @@
`define MEM_DCACHE 0 `define MEM_DCACHE 0
`define MEM_DTIM 1 `define MEM_DTIM 1
`define MEM_ICACHE 0 `define MEM_ICACHE 0
`define MEM_VIRTMEM 1 `define MEM_VIRTMEM 0\1
`define VECTORED_INTERRUPTS_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1
`define ITLB_ENTRIES 32 `define ITLB_ENTRIES 32

View File

@ -70,6 +70,8 @@ module pagetablewalker
output logic WalkerStorePageFaultM output logic WalkerStorePageFaultM
); );
generate
if (`MEM_VIRTMEM) begin
// Internal signals // Internal signals
// register TLBs translation miss requests // register TLBs translation miss requests
logic [`XLEN-1:0] TranslationVAdrQ; logic [`XLEN-1:0] TranslationVAdrQ;
@ -175,13 +177,13 @@ module pagetablewalker
assign PageTypeM = PageType; assign PageTypeM = PageType;
generate // generate
if (`XLEN == 32) begin if (`XLEN == 32) begin
logic [9:0] VPN1, VPN0; logic [9:0] VPN1, VPN0;
flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState); flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
/* -----\/----- EXCLUDED -----\/----- /* -----\/----- EXCLUDED -----\/-----
assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall; assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall;
-----/\----- EXCLUDED -----/\----- */ -----/\----- EXCLUDED -----/\----- */
@ -549,6 +551,15 @@ module pagetablewalker
// we support larger physical address spaces // we support larger physical address spaces
assign MMUPAdr = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]}; assign MMUPAdr = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
end end
//endgenerate
end else begin
assign MMUPAdr = 0;
assign MMUTranslate = 0;
assign HPTWRead = 0;
assign WalkerInstrPageFaultF = 0;
assign WalkerLoadPageFaultM = 0;
assign WalkerStorePageFaultM = 0;
end
endgenerate endgenerate
endmodule endmodule