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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Don't generate HPTW when MEM_VIRTMEM=0
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parent
179c8d3ed4
commit
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wally-pipelined
@ -46,7 +46,7 @@
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`define MEM_DCACHE 0
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`define MEM_DCACHE 0
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`define MEM_DTIM 1
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`define MEM_DTIM 1
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`define MEM_ICACHE 0
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`define MEM_ICACHE 0
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`define MEM_VIRTMEM 1
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`define MEM_VIRTMEM 0\1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define ITLB_ENTRIES 32
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`define ITLB_ENTRIES 32
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@ -70,6 +70,8 @@ module pagetablewalker
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output logic WalkerStorePageFaultM
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output logic WalkerStorePageFaultM
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);
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);
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generate
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if (`MEM_VIRTMEM) begin
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// Internal signals
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// Internal signals
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// register TLBs translation miss requests
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// register TLBs translation miss requests
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logic [`XLEN-1:0] TranslationVAdrQ;
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logic [`XLEN-1:0] TranslationVAdrQ;
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@ -175,13 +177,13 @@ module pagetablewalker
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assign PageTypeM = PageType;
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assign PageTypeM = PageType;
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generate
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// generate
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if (`XLEN == 32) begin
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if (`XLEN == 32) begin
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logic [9:0] VPN1, VPN0;
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logic [9:0] VPN1, VPN0;
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flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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flopenl #(.TYPE(statetype)) mmureg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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/* -----\/----- EXCLUDED -----\/-----
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/* -----\/----- EXCLUDED -----\/-----
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assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall;
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assign PRegEn = (WalkerState == LEVEL1_WDV || WalkerState == LEVEL0_WDV) && ~HPTWStall;
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-----/\----- EXCLUDED -----/\----- */
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-----/\----- EXCLUDED -----/\----- */
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@ -549,6 +551,15 @@ module pagetablewalker
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// we support larger physical address spaces
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// we support larger physical address spaces
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assign MMUPAdr = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
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assign MMUPAdr = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
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end
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end
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//endgenerate
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end else begin
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assign MMUPAdr = 0;
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assign MMUTranslate = 0;
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assign HPTWRead = 0;
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assign WalkerInstrPageFaultF = 0;
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assign WalkerLoadPageFaultM = 0;
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assign WalkerStorePageFaultM = 0;
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end
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endgenerate
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endgenerate
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endmodule
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endmodule
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