From 7139279e50bbcf6307fd5e8f6a84b1367f08b529 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Aug 2021 13:17:07 -0500 Subject: [PATCH] Moved more logic inside the dcache memory. --- wally-pipelined/src/cache/DCacheMem.sv | 23 +++++++++++++++-------- wally-pipelined/src/cache/dcache.sv | 21 ++++++++------------- 2 files changed, 23 insertions(+), 21 deletions(-) diff --git a/wally-pipelined/src/cache/DCacheMem.sv b/wally-pipelined/src/cache/DCacheMem.sv index 2e99917b2..207a0aa40 100644 --- a/wally-pipelined/src/cache/DCacheMem.sv +++ b/wally-pipelined/src/cache/DCacheMem.sv @@ -41,16 +41,20 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26 input logic ClearValid, input logic SetDirty, input logic ClearDirty, + input logic SelEvict, + input logic VictimWay, - output logic [BLOCKLEN-1:0] ReadData, - output logic [TAGLEN-1:0] ReadTag, - output logic Valid, - output logic Dirty, - output logic WayHit + output logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM, + output logic WayHit, + output logic VictimDirtyWay, + output logic [TAGLEN-1:0] VictimTagWay ); logic [NUMLINES-1:0] ValidBits, DirtyBits; - + logic [BLOCKLEN-1:0] ReadDataBlockWayM; + logic [TAGLEN-1:0] ReadTag; + logic Valid; + logic Dirty; genvar words; @@ -60,7 +64,7 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26 .WIDTH(NUMLINES)) CacheDataMem(.clk(clk), .Addr(Adr), - .ReadData(ReadData[(words+1)*`XLEN-1:words*`XLEN]), + .ReadData(ReadDataBlockWayM[(words+1)*`XLEN-1:words*`XLEN]), .WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]), .WriteEnable(WriteEnable & WriteWordEnable[words])); end @@ -75,8 +79,11 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26 .WriteEnable(TagWriteEnable)); assign WayHit = Valid & (ReadTag == MemPAdrM[`PA_BITS-1:OFFSETLEN+INDEXLEN]); - + assign SelectedWay = SelEvict ? VictimWay : WayHit; + assign ReadDataBlockWayMaskedM = SelectedWay ? ReadDataBlockWayM : '0; // first part of AO mux. + assign VictimDirtyWay = VictimWay & Dirty & Valid; + assign VictimTagWay = VictimWay ? ReadTag : '0; always_ff @(posedge clk, posedge reset) begin if (reset) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index ede050e1a..94274ef15 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -95,17 +95,14 @@ module dcache logic [BLOCKLEN-1:0] DCacheMemWriteData; logic SetValidM, ClearValidM; logic SetDirtyM, ClearDirtyM; - logic [BLOCKLEN-1:0] ReadDataBlockWayM [NUMWAYS-1:0]; logic [BLOCKLEN-1:0] ReadDataBlockWayMaskedM [NUMWAYS-1:0]; - logic [TAGLEN-1:0] ReadTag [NUMWAYS-1:0]; - logic [NUMWAYS-1:0] Valid, Dirty, WayHit, SelectedWay; + logic [NUMWAYS-1:0] WayHit; logic CacheHit; logic [NUMWAYS-2:0] ReplacementBits [NUMLINES-1:0]; logic [NUMWAYS-2:0] BlockReplacementBits; logic [NUMWAYS-2:0] NewReplacement; logic [BLOCKLEN-1:0] ReadDataBlockM; logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0]; - logic [`XLEN-1:0] VictimReadDataBlockSetsM [(WORDSPERLINE)-1:0]; logic [`XLEN-1:0] ReadDataWordM, ReadDataWordMuxM; logic [`XLEN-1:0] FinalWriteDataM, FinalAMOWriteDataM; logic [BLOCKLEN-1:0] FinalWriteDataWordsM; @@ -223,17 +220,15 @@ module dcache .ClearValid(ClearValidM), .SetDirty(SetDirtyM), .ClearDirty(ClearDirtyM), - .ReadData(ReadDataBlockWayM[way]), - .ReadTag(ReadTag[way]), - .Valid(Valid[way]), - .Dirty(Dirty[way]), - .WayHit(WayHit[way])); - assign SelectedWay[way] = SelEvict ? VictimWay[way] : WayHit[way]; - assign ReadDataBlockWayMaskedM[way] = SelectedWay[way] ? ReadDataBlockWayM[way] : '0; // first part of AO mux. + .SelEvict, + .VictimWay(VictimWay[way]), + .ReadDataBlockWayMaskedM(ReadDataBlockWayMaskedM[way]), + .WayHit(WayHit[way]), + .VictimDirtyWay(VictimDirtyWay[way]), + .VictimTagWay(VictimTagWay[way])); + // the cache block candiate for eviction - assign VictimDirtyWay[way] = VictimWay[way] & Dirty[way] & Valid[way]; - assign VictimTagWay[way] = VictimWay[way] ? ReadTag[way] : '0; end endgenerate