Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

Browse Source
This commit is contained in:
Ross Thompson 2022-02-08 17:52:15 -06:00
commit 7133e790ea
5 changed files with 57 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
fpga/constraints/debug2.xdc
View File

@ -282,7 +282,7 @@ connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/core/priv.p
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe66] set_property port_width 1 [get_debug_ports u_ila_0/probe66]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StorePageFaultM ]] connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/core/priv.priv/trap/StoreAmoPageFaultM ]]
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe67] set_property port_width 1 [get_debug_ports u_ila_0/probe67]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
@ -446,7 +446,7 @@ connect_debug_port u_ila_0/probe98 [get_nets [list wallypipelinedsoc/core/hzu/Fl
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe99] set_property port_width 4 [get_debug_ports u_ila_0/probe99]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99]
connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/core/ifu/icache.icache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/icache.icache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/icache.icache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/ifu/icache.icache/cachefsm/CurrState[3]}]] connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[0]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[1]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[2]} {wallypipelinedsoc/core/ifu/bus.icache.icache/cachefsm/CurrState[3]}]]
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
@ -555,7 +555,7 @@ connect_debug_port u_ila_0/probe119 [get_nets [list wallypipelinedsoc/core/lsu/D
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 11 [get_debug_ports u_ila_0/probe120] set_property port_width 11 [get_debug_ports u_ila_0/probe120]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe120] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe120]
connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[0]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[1]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[2]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[3]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[4]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[5]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[6]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[7]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[8]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[9]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.hptw/WalkerState[10]}]] connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[0]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[1]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[2]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[3]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[4]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[5]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[6]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[7]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[8]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[9]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/hptw/WalkerState[10]}]]
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
@ -574,23 +574,23 @@ connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsoc/core/ifu/
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe123] set_property port_width 3 [get_debug_ports u_ila_0/probe123]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe123] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe123]
connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsoc/core/ifu/bus.busfsm/BusCurrState[0]} {wallypipelinedsoc/core/ifu/bus.busfsm/BusCurrState[1]} {wallypipelinedsoc/core/ifu/bus.busfsm/BusCurrState[2]} ]] connect_debug_port u_ila_0/probe123 [get_nets [list {wallypipelinedsoc/core/ifu/bus.busdp/busfsm/BusCurrState[0]} {wallypipelinedsoc/core/ifu/bus.busdp/busfsm/BusCurrState[1]} {wallypipelinedsoc/core/ifu/bus.busdp/busfsm/BusCurrState[2]} ]]
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe124] set_property port_width 1 [get_debug_ports u_ila_0/probe124]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe124] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe124]
connect_debug_port u_ila_0/probe124 [get_nets [list wallypipelinedsoc/core/ifu/SpillSupport.CurrState[0] ]] connect_debug_port u_ila_0/probe124 [get_nets [list wallypipelinedsoc/core/ifu/SpillSupport.spillsupport/CurrState[0] ]]
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe125] set_property port_width 3 [get_debug_ports u_ila_0/probe125]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe125] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe125]
connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/core/lsu/bus.busfsm/BusCurrState[0]} {wallypipelinedsoc/core/lsu/bus.busfsm/BusCurrState[1]} {wallypipelinedsoc/core/lsu/bus.busfsm/BusCurrState[2]} ]] connect_debug_port u_ila_0/probe125 [get_nets [list {wallypipelinedsoc/core/lsu/bus.busdp/busfsm/BusCurrState[0]} {wallypipelinedsoc/core/lsu/bus.busdp/busfsm/BusCurrState[1]} {wallypipelinedsoc/core/lsu/bus.busdp/busfsm/BusCurrState[2]} ]]
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe126] set_property port_width 3 [get_debug_ports u_ila_0/probe126]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe126]
connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[0]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[1]} {wallypipelinedsoc/core/lsu/MEM_VIRTMEM.interlockfsm/InterlockCurrState[2]} ]] connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/interlockfsm/InterlockCurrState[0]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/interlockfsm/InterlockCurrState[1]} {wallypipelinedsoc/core/lsu/VIRTMEM_SUPPORTED.lsuvirtmem/interlockfsm/InterlockCurrState[2]} ]]
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe

6
fpga/generator/xlnx_ahblite_axi_bridge.tcl
View File

@ -1,9 +1,15 @@
#set partNumber $::env(XILINX_PART) #set partNumber $::env(XILINX_PART)
#set boardNmae $::env(XILINX_BOARD) #set boardNmae $::env(XILINX_BOARD)
# vcu118 board
set partNumber xcvu9p-flga2104-2L-e set partNumber xcvu9p-flga2104-2L-e
set boardName xilinx.com:vcu118:part0:2.4 set boardName xilinx.com:vcu118:part0:2.4
# kcu105 board
#set partNumber xcku040-ffva1156-2-e
#set boardName xilinx.com:kcu105:part0:1.7
set ipName xlnx_ahblite_axi_bridge set ipName xlnx_ahblite_axi_bridge
create_project $ipName . -force -part $partNumber create_project $ipName . -force -part $partNumber

84
pipelined/src/uncore/ram.sv
View File

@ -59,48 +59,48 @@ module ram #(parameter BASE=0, RANGE = 65535) (
// *** need to address this preload for fpga. It should work as a preload file // *** need to address this preload for fpga. It should work as a preload file
// but for some reason vivado is not synthesizing the preload. // but for some reason vivado is not synthesizing the preload.
//$readmemh(PRELOAD, RAM); //$readmemh(PRELOAD, RAM);
RAM[0] = 64'h94e1819300002197; RAM[0] = 64'h94e1819300002197;
RAM[1] = 64'h4281420141014081; RAM[1] = 64'h4281420141014081;
RAM[2] = 64'h4481440143814301; RAM[2] = 64'h4481440143814301;
RAM[3] = 64'h4681460145814501; RAM[3] = 64'h4681460145814501;
RAM[4] = 64'h4881480147814701; RAM[4] = 64'h4881480147814701;
RAM[5] = 64'h4a814a0149814901; RAM[5] = 64'h4a814a0149814901;
RAM[6] = 64'h4c814c014b814b01; RAM[6] = 64'h4c814c014b814b01;
RAM[7] = 64'h4e814e014d814d01; RAM[7] = 64'h4e814e014d814d01;
RAM[8] = 64'h0110011b4f814f01; RAM[8] = 64'h0110011b4f814f01;
RAM[9] = 64'h059b45011161016e; RAM[9] = 64'h059b45011161016e;
RAM[10] = 64'h0004063705fe0010; RAM[10] = 64'h0004063705fe0010;
RAM[11] = 64'h05a000ef8006061b; RAM[11] = 64'h05a000ef8006061b;
RAM[12] = 64'h0ff003930000100f; RAM[12] = 64'h0ff003930000100f;
RAM[13] = 64'h4e952e3110012e37; RAM[13] = 64'h4e952e3110060e37;
RAM[14] = 64'hc602829b0053f2b7; RAM[14] = 64'hc602829b0053f2b7;
RAM[15] = 64'h2023fe02dfe312fd; RAM[15] = 64'h2023fe02dfe312fd;
RAM[16] = 64'h829b0053f2b7007e; RAM[16] = 64'h829b0053f2b7007e;
RAM[17] = 64'hfe02dfe312fdc602; RAM[17] = 64'hfe02dfe312fdc602;
RAM[18] = 64'h4de31efd000e2023; RAM[18] = 64'h4de31efd000e2023;
RAM[19] = 64'h059bf1402573fdd0; RAM[19] = 64'h059bf1402573fdd0;
RAM[20] = 64'h0000061705e20870; RAM[20] = 64'h0000061705e20870;
RAM[21] = 64'h0010029b01260613; RAM[21] = 64'h0010029b01260613;
RAM[22] = 64'h11010002806702fe; RAM[22] = 64'h11010002806702fe;
RAM[23] = 64'h84b2842ae426e822; RAM[23] = 64'h84b2842ae426e822;
RAM[24] = 64'h892ee04aec064505; RAM[24] = 64'h892ee04aec064505;
RAM[25] = 64'h06e000ef07e000ef; RAM[25] = 64'h06e000ef07e000ef;
RAM[26] = 64'h979334fd02905563; RAM[26] = 64'h979334fd02905563;
RAM[27] = 64'h07930177d4930204; RAM[27] = 64'h07930177d4930204;
RAM[28] = 64'h4089093394be2004; RAM[28] = 64'h4089093394be2004;
RAM[29] = 64'h04138522008905b3; RAM[29] = 64'h04138522008905b3;
RAM[30] = 64'h19e3014000ef2004; RAM[30] = 64'h19e3014000ef2004;
RAM[31] = 64'h64a2644260e2fe94; RAM[31] = 64'h64a2644260e2fe94;
RAM[32] = 64'h6749808261056902; RAM[32] = 64'h6749808261056902;
RAM[33] = 64'hdfed8b8510472783; RAM[33] = 64'hdfed8b8510472783;
RAM[34] = 64'h2423479110a73823; RAM[34] = 64'h2423479110a73823;
RAM[35] = 64'h10472783674910f7; RAM[35] = 64'h10472783674910f7;
RAM[36] = 64'h20058693ffed8b89; RAM[36] = 64'h20058693ffed8b89;
RAM[37] = 64'h05a1118737836749; RAM[37] = 64'h05a1118737836749;
RAM[38] = 64'hfed59be3fef5bc23; RAM[38] = 64'hfed59be3fef5bc23;
RAM[39] = 64'h1047278367498082; RAM[39] = 64'h1047278367498082;
RAM[40] = 64'h67c98082dfed8b85; RAM[40] = 64'h67c98082dfed8b85;
RAM[41] = 64'h0000808210a7a023; RAM[41] = 64'h0000808210a7a023;
end // initial begin end // initial begin
end // if (FPGA) end // if (FPGA)

2
tests/testsBP/fpga-test-sdc/Makefile
View File

@ -106,7 +106,7 @@ $(TARGET).memfile: $(TARGET)
@echo 'Making object dump file.' @echo 'Making object dump file.'
@riscv64-unknown-elf-objdump -D $< > $<.objdump @riscv64-unknown-elf-objdump -D $< > $<.objdump
@echo 'Making memory file' @echo 'Making memory file'
exe2memfile0.pl $< riscv64-unknown-elf-elf2hex --bit-width 64 --input $^ --output $@
extractFunctionRadix.sh $<.objdump extractFunctionRadix.sh $<.objdump
mkdir -p ../../imperas-riscv-tests/work/rv64BP/ mkdir -p ../../imperas-riscv-tests/work/rv64BP/
cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/ cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/

2
tests/testsBP/fpga-test-sdc/bios.s
View File

@ -61,7 +61,7 @@ _start:
# write to gpio # write to gpio
li t2, 0xFF li t2, 0xFF
la t3, 0x1001200C la t3, 0x1006000C
li t4, 5 li t4, 5
loop: loop: