From 70fc32104e0aa2290bb8d0fdea9fbc4536967ecd Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 21 May 2023 14:05:57 -0700 Subject: [PATCH] more lint fixes --- src/fpu/divremsqrt/divremsqrtpostprocess.sv | 2 +- src/fpu/divremsqrt/drsu.sv | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/fpu/divremsqrt/divremsqrtpostprocess.sv b/src/fpu/divremsqrt/divremsqrtpostprocess.sv index 6ab1a54e5..43aba0c3e 100644 --- a/src/fpu/divremsqrt/divremsqrtpostprocess.sv +++ b/src/fpu/divremsqrt/divremsqrtpostprocess.sv @@ -145,7 +145,7 @@ module divremsqrtpostprocess ( // round to nearest max magnitude // calulate result sign used in rounding unit - divremsqrtroundsign roundsign( .DivOp, .Sqrt, .Xs, .Ys, , .Ms); + divremsqrtroundsign roundsign( .DivOp, .Sqrt, .Xs, .Ys, Ms); divremsqrtround round(.OutFmt, .Frm, .Plus1, .Qe, .Ms, .Mf, .DivSticky, .DivOp, .UfPlus1, .FullRe, .Rf, .Re, .Sticky, .Round, .Guard, .Me); diff --git a/src/fpu/divremsqrt/drsu.sv b/src/fpu/divremsqrt/drsu.sv index 938dcbc15..6e23c548b 100644 --- a/src/fpu/divremsqrt/drsu.sv +++ b/src/fpu/divremsqrt/drsu.sv @@ -77,6 +77,9 @@ module drsu( logic NegQuotM, ALTBM, AsM, W64M; // Special handling for postprocessor logic [`XLEN-1:0] AM; // Original Numerator for postprocessor logic ISpecialCaseE; // Integer div/remainder special cases + logic [`DIVb:0] QmM; + logic [`NE+1:0] QeM; + logic DivStickyM; divremsqrt divremsqrt(.clk, .reset, .XsE, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE, .SqrtM,