From 03cea6e29ba4728c4fda09c4e274074bef1eeb46 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Thu, 28 Jan 2021 16:13:10 -0500 Subject: [PATCH 1/6] more misaligned read fixing I'm getting fairly concerned about this, I feel like this should only work if the memory ignores the lower 3 or 4 bits of the adr --- wally-pipelined/regression/wally-busybear.do | 1 + 1 file changed, 1 insertion(+) diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index ab1cfac31..cd739993c 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -54,6 +54,7 @@ add wave -hex /testbench_busybear/MemRWM[0] add wave -hex /testbench_busybear/MemRWM[1] add wave -hex /testbench_busybear/ByteMaskM add wave -hex /testbench_busybear/WriteDataM +add wave -hex /testbench_busybear/ReadDataM add wave -hex /testbench_busybear/DataAdrM add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[1] add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[2] From cbab07967a2d82e1e26f893d41ce9df62fb55908 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Thu, 28 Jan 2021 16:26:15 -0500 Subject: [PATCH 2/6] more of the same fixes --- wally-pipelined/regression/wally-busybear.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index cd739993c..cd0282855 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -131,6 +131,6 @@ add wave /testbench_busybear/InstrWName #set DefaultRadix hexadecimal # #-- Run the Simulation -run 3850 +run 5240 #run -all ##quit From 9c0580f2e1255ad0946487e91c75670a7697d1cc Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Thu, 28 Jan 2021 16:35:12 -0500 Subject: [PATCH 3/6] oops forgot to add C.BEQZ, C.BNEZ checks to busybear testbench --- wally-pipelined/testbench/testbench-busybear.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index 07b48d373..0482c3c2a 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -180,6 +180,8 @@ module testbench_busybear(); 16'bXXXXXXXXX1101111, // JAL 16'bXXXXXXXXX1100111, // JALR 16'bXXXXXXXXX1100011, // B + 16'b110XXXXXXXXXXX01, // C.BEQZ + 16'b111XXXXXXXXXXX01, // C.BNEZ 16'b101XXXXXXXXXXX01: // C.J speculative = 1; 16'b1001000000000010: // C.EBREAK: From df1d174aea41b9b0354c21a4b4236535e192aafc Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Thu, 28 Jan 2021 16:41:37 -0500 Subject: [PATCH 4/6] busybear: add more test instructions currently testing first 1k instrs --- wally-pipelined/regression/wally-busybear.do | 2 +- wally-pipelined/testbench/testbench-busybear.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index cd0282855..bca0eaab9 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -131,6 +131,6 @@ add wave /testbench_busybear/InstrWName #set DefaultRadix hexadecimal # #-- Run the Simulation -run 5240 +run 8690 #run -all ##quit diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index 0482c3c2a..edc82ac65 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -171,7 +171,7 @@ module testbench_busybear(); // then expected PC value scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected); if (instrs < 10 || (instrs < 100 && instrs % 10 == 0) || - (instrs < 1000 && instrs % 50 == 0) || instrs > 205) begin + (instrs < 1000 && instrs % 50 == 0) || instrs > 700) begin $display("loaded %0d instructions", instrs); end instrs += 1; From 96ceac0e8028278433831916a09ef2ac275405a2 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Thu, 28 Jan 2021 19:35:09 -0500 Subject: [PATCH 5/6] busybear: fix misaligned writing checking --- wally-pipelined/regression/wally-busybear.do | 2 +- wally-pipelined/testbench/testbench-busybear.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index bca0eaab9..93c6951a4 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -131,6 +131,6 @@ add wave /testbench_busybear/InstrWName #set DefaultRadix hexadecimal # #-- Run the Simulation -run 8690 +run 12422 #run -all ##quit diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index edc82ac65..89248e258 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -171,7 +171,7 @@ module testbench_busybear(); // then expected PC value scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected); if (instrs < 10 || (instrs < 100 && instrs % 10 == 0) || - (instrs < 1000 && instrs % 50 == 0) || instrs > 700) begin + (instrs < 1000 && instrs % 50 == 0)) begin $display("loaded %0d instructions", instrs); end instrs += 1; From c4964352f0b066ee41d8390e1f75913080bc1b4c Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Thu, 28 Jan 2021 19:44:58 -0500 Subject: [PATCH 6/6] busybear: simulate first 10k instructions I know we need to add CSR checking sometime soon Also I'm a bit sketpical this is all working properly, and that no new bugs were uncovered from 1k instrs to 10k instrs --- wally-pipelined/regression/wally-busybear.do | 2 +- wally-pipelined/testbench/testbench-busybear.sv | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index 93c6951a4..b9b173bd8 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -131,6 +131,6 @@ add wave /testbench_busybear/InstrWName #set DefaultRadix hexadecimal # #-- Run the Simulation -run 12422 +run 129812 #run -all ##quit diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index 89248e258..0cfcc0dab 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -170,8 +170,8 @@ module testbench_busybear(); scan_file_PC = $fscanf(data_file_PC, "%x\n", InstrF); // then expected PC value scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected); - if (instrs < 10 || (instrs < 100 && instrs % 10 == 0) || - (instrs < 1000 && instrs % 50 == 0)) begin + if (instrs <= 10 || (instrs <= 100 && instrs % 10 == 0) || + (instrs <= 1000 && instrs % 100 == 0) || (instrs <= 10000 && instrs % 1000 == 0)) begin $display("loaded %0d instructions", instrs); end instrs += 1;