diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index 9ce59c6bc..991f3e71c 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -42,7 +42,7 @@ IP_VCU: $(dst)/sysrst.log \ $(dst)/ahbaxibridge.log IP_Arty: $(dst)/sysrst.log \ MEM_Arty \ - $(dst)/xlnx_mmcm.log \ + $(dst)/mmcm.log $(dst)/clkconverter.log \ $(dst)/ahbaxibridge.log diff --git a/fpga/generator/mmcm.tcl b/fpga/generator/mmcm.tcl index f5a7da06f..a791a60b6 100644 --- a/fpga/generator/mmcm.tcl +++ b/fpga/generator/mmcm.tcl @@ -1,26 +1,29 @@ set partNumber $::env(XILINX_PART) set boardName $::env(XILINX_BOARD) set SYSTEMCLOCK $::env(SYSTEMCLOCK) - set ipName mmcm +set SYSTEMCLOCK_MHz [expr $SYSTEMCLOCK/1000000.0] + create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \ - CONFIG.NUM_OUT_CLKS {3} \ + CONFIG.NUM_OUT_CLKS {4} \ CONFIG.CLKOUT2_USED {true} \ CONFIG.CLKOUT3_USED {true} \ CONFIG.CLKOUT4_USED {true} \ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {$SYSTEMCLOCK} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ $SYSTEMCLOCK_MHz \ CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \ CONFIG.CLKIN1_JITTER_PS {10.0} \ ] [get_ips $ipName] +#set_property CONFIG.CLKOUT3_REQUESTED_OUT_FREQ $SYSTEMCLOCK_MHz [get_ips $ipName] + generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]