Added ability to split boot.memfile into boot.mem and data.mem.

fpga/zsbl/Makefile

@@ -17,6 +17,7 @@ OBJECTS		:= $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(OBJECTS))
 
 TARGETDIR	:= bin
 TARGET		:= $(TARGETDIR)/boot
+MEMFILES    := $(TARGETDIR/boot.mem $(TARGETDIR)/data.mem
 ROOT		:= ..
 LIBRARY_DIRS	:= 
 LIBRARY_FILES	:=
@@ -37,7 +38,7 @@ AR=riscv64-unknown-elf-ar
 
 
 #Default Make
-all: directories  $(TARGET).memfile
+all: directories $(TARGET).memfile
 
 #Remake
 remake: clean all
@@ -48,7 +49,7 @@ directories:
 	@mkdir -p $(BUILDDIR)
 
 clean:
-	rm -rf $(BUILDDIR) $(TARGETDIR) *.memfile *.objdump 
+	rm -rf $(BUILDDIR) $(TARGETDIR) *.memfile *.objdump boot.mem data.mem
 
 
 #Needed for building additional library projects
@@ -112,3 +113,7 @@ $(TARGET).memfile: $(TARGET)
 	extractFunctionRadix.sh $<.objdump
 	mkdir -p ../../imperas-riscv-tests/work/rv64BP/
 	cp -f $(TARGETDIR)/* ../../imperas-riscv-tests/work/rv64BP/
+	@echo 'Splitting memfile.'
+	./splitfile.sh $@
+	mv boot.mem ../src/boot.mem
+	mv data.mem ../src/data.mem

src/generic/mem/ram1p1rwbe.sv

@@ -83,11 +83,26 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
   end else begin: ram
     bit [WIDTH-1:0] RAM[DEPTH-1:0];
 
-    if (PRELOAD_ENABLED) begin
+    // if (PRELOAD_ENABLED) begin
-      initial begin
+    //   initial begin
-        RAM[0] = 64'h00600100d2e3ca40;
+    //     RAM[0] = 64'h00600100d2e3ca40;
+    //   end
+    // end
+
+    initial 
+      if (PRELOAD_ENABLED) begin
+        if (WIDTH == 64) begin
+          `ifdef VERILATOR
+            // because Verilator doesn't automatically accept $WALLY from shell
+            string       WALLY_DIR = getenvval("WALLY"); 
+            $readmemh({WALLY_DIR,"/fpga/src/data.mem"}, RAM, 0);  // load boot ROM for FPGA
+          `else
+            $readmemh({"$WALLY/fpga/src/data.mem"}, RAM, 0);  // load boot ROM for FPGA
+          `endif
+        end else begin // put something in the ROM so it is not optimized away
+        RAM[0] = 'h00002197;
+        end
       end
-    end
     
     // Combinational read: register address and read after clock edge
     logic [$clog2(DEPTH)-1:0] addrd;

src/uncore/uncore.sv

@@ -78,13 +78,13 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
   logic                        SDCIntM;
   
   logic                        PCLK, PRESETn, PWRITE, PENABLE;
-  logic [4:0]                  PSEL;
+  logic [5:0]                  PSEL;
   logic [31:0]                 PADDR;
   logic [P.XLEN-1:0]           PWDATA;
   logic [P.XLEN/8-1:0]         PSTRB;
   /* verilator lint_off UNDRIVEN */ // undriven in rv32e configuration
-  logic [4:0]                  PREADY;
+  logic [5:0]                  PREADY;
-  logic [4:0][P.XLEN-1:0]      PRDATA;
+  logic [5:0][P.XLEN-1:0]      PRDATA;
   /* verilator lint_on UNDRIVEN */
   logic [P.XLEN-1:0]           HREADBRIDGE;
   logic                        HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED;
@@ -102,7 +102,7 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
 
   // AHB -> APB bridge
   ahbapbbridge #(P, 6) ahbapbbridge (
-    .HCLK, .HRESETn, .HSEL({HSELSPI, HSELUART, HSELPLIC, HSELCLINT, HSELGPIO, HSELSDC}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY, 
+    .HCLK, .HRESETn, .HSEL({HSELSDC, HSELSPI, HSELUART, HSELPLIC, HSELCLINT, HSELGPIO}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY, 
     .HRDATA(HREADBRIDGE), .HRESP(HRESPBRIDGE), .HREADYOUT(HREADYBRIDGE),
     .PCLK, .PRESETn, .PSEL, .PWRITE, .PENABLE, .PADDR, .PWDATA, .PSTRB, .PREADY, .PRDATA);
   assign HSELBRIDGE = HSELGPIO | HSELCLINT | HSELPLIC | HSELUART | HSELSPI | HSELSDC; // if any of the bridge signals are selected
@@ -172,7 +172,7 @@ module uncore import cvw::*;  #(parameter cvw_t P)(
       .PREADY(PREADY[5]), .PRDATA(PRDATA[5]),
       .SPIOut(SDCCmd), .SPIIn(SDCIn), .SPICS(SDCCS), .SPICLK(SDCCLK), .SPIIntr(SDCIntr));                                      
   end else begin : sdc
-    assign SDCCmd = '0; assign SDCCD = 1'b0; assign SDCIntr = 1'b0; assign SDCCLK = 1'b0;
+    assign SDCCmd = '0; assign SDCCS = 1'b0; assign SDCIntr = 1'b0; assign SDCCLK = 1'b0;
   end
   
 

testbench/testbench.sv

@@ -76,8 +76,7 @@ module testbench;
 
   // DUT signals
   logic [P.AHBW-1:0]    HRDATAEXT;
-  logic                 HREADYEXT, HRESPEXT;
+  logic                 HREADYEXT, HRESPEXT; 
-  logic                 HSELEXTSDC;
   logic [P.PA_BITS-1:0] HADDR;
   logic [P.AHBW-1:0]    HWDATA;
   logic [P.XLEN/8-1:0]  HWSTRB;
@@ -93,7 +92,11 @@ module testbench;
   logic        UARTSin, UARTSout;
   logic        SPIIn, SPIOut;
   logic [3:0]  SPICS;
-  logic        SDCIntr;
+  logic        SPICLK;
+  logic        SDCCmd;
+  logic        SDCIn;
+  logic [3:0]  SDCCS;
+  logic        SDCCLK;        
 
   logic        HREADY;
   logic        HSELEXT;
@@ -371,6 +374,11 @@ module testbench;
         uartoutfile = $fopen(uartoutfilename, "w"); // delete UART output file
         ProgramAddrMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.addr"};
         ProgramLabelMapFile = {RISCV_DIR, "/buildroot/output/images/disassembly/vmlinux.objdump.lab"};
+      end else if(TEST == "fpga") begin
+        bootmemfilename = {WALLY_DIR, "/fpga/src/boot.mem"};
+        memfilename = {WALLY_DIR, "/fpga/src/data.mem"};
+        ProgramAddrMapFile = {WALLY_DIR, "/fpga/zsbl/bin/boot.objdump.addr"};
+        ProgramLabelMapFile = {WALLY_DIR, "/fpga/zsbl/bin/boot.objdump.lab"};
       end else if(ElfFile != "none") begin
         elffilename = ElfFile;
         memfilename = {ElfFile, ".memfile"};
@@ -505,6 +513,23 @@ module testbench;
           end
           readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.ram.RAM, memFile);
           $fclose(memFile);
+        end else if (TEST == "fpga") begin
+          memFile = $fopen(bootmemfilename, "rb");
+          if (memFile == 0) begin
+            $display("Error: Could not open file %s", memfilename);
+            $finish;
+          end
+          if (P.BOOTROM_SUPPORTED) begin
+            readResult = $fread(dut.uncoregen.uncore.bootrom.bootrom.memory.ROM, memFile);
+          end
+          $fclose(memFile);
+          memFile = $fopen(memfilename, "rb");
+          if (memFile == 0) begin
+            $display("Error: Could not open file %s", memfilename);
+            $finish;
+          end
+          readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.ram.RAM, memFile);
+          $fclose(memFile);
         end else begin
           uncoreMemFile = $fopen(memfilename, "r");  // Is there a better way to test if a file exists?
           if (uncoreMemFile == 0) begin
@@ -584,15 +609,15 @@ module testbench;
     assign SDCDat = sd_dat_reg_t ? sd_dat_reg_o : sd_dat_i;
     assign SDCDatIn = SDCDat;
     -----/\----- EXCLUDED -----/\----- */
-    assign SDCIntr = 1'b0;
   end else begin
-    assign SDCIntr = 1'b0;
+    assign SDCIn = 1'b1;
+    
   end
 
-  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
+  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT,
     .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
     .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
-    .UARTSin, .UARTSout, .SDCIntr, .SPIIn, .SPIOut, .SPICS); 
+    .UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SPICLK, .SDCIn, .SDCCmd, .SDCCS, .SDCCLK); 
 
   // generate clock to sequence tests
   always begin