diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv
index c84d7e82a..3d3c15752 100644
--- a/pipelined/src/ifu/spillsupport.sv
+++ b/pipelined/src/ifu/spillsupport.sv
@@ -93,7 +93,8 @@ module spillsupport (
                               .d((`IMEM == `MEM_CACHE) ? InstrRawF[15:0] : InstrRawF[31:16]),
                               .q(SpillDataLine0));
 
-  assign PostSpillInstrRawF = SpillF ? {InstrRawF[15:0], SpillDataLine0} : InstrRawF;
+  mux2 #(32) postspillmux(.d0(InstrRawF), .d1({InstrRawF[15:0], SpillDataLine0}), .s(SpillF),
+    .y(PostSpillInstrRawF));
   assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11;
 
 endmodule