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Third attempt at fixing the write enables for the icache cacheway.

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This commit is contained in:
Ross Thompson 2021-09-09 15:08:10 -05:00
parent 6965bde95c
commit 6f4542f063
1 changed files with 1 additions and 1 deletions
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2
wally-pipelined/src/cache/icache.sv vendored
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@ -142,7 +142,7 @@ module icache
.RAdr(RAdr), .RAdr(RAdr),
.PAdr(PCTagF), .PAdr(PCTagF),
.WriteEnable(SRAMWayWriteEnable), .WriteEnable(SRAMWayWriteEnable),
.WriteWordEnable({NUMWAYS{1'b1}}), .WriteWordEnable({{(BLOCKLEN/`XLEN){1'b1}}}),
.TagWriteEnable(SRAMWayWriteEnable), .TagWriteEnable(SRAMWayWriteEnable),
.WriteData(ICacheMemWriteData), .WriteData(ICacheMemWriteData),
.SetValid(ICacheMemWriteEnable), .SetValid(ICacheMemWriteEnable),