From 6f3b8680d5e2467a93c151cd74c203305f354e41 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 20 Jan 2023 09:41:18 -0600
Subject: [PATCH] Imperas found a bug with the Fence.I instruction. If a
 fence.i directly followed a store miss, the d$ would release Stall during the
 cache line write. Then transition to ReadHold.  This cause the d$ flush to go
 high while in ReadHold.  The solution is to ensure the cache continues to
 assert Stall while in WriteLine state.

There was a second issue also.  The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
---
 pipelined/src/cache/cachefsm.sv | 4 ++--
 pipelined/src/cache/cacheway.sv | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv
index 4abbe59a2..a8be120b0 100644
--- a/pipelined/src/cache/cachefsm.sv
+++ b/pipelined/src/cache/cachefsm.sv
@@ -141,7 +141,7 @@ module cachefsm
   assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | 
                       (CurrState == STATE_FETCH) |
                       (CurrState == STATE_WRITEBACK) |
-                      (CurrState == STATE_WRITE_LINE & ~(StoreAMO)) |  // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
+                      (CurrState == STATE_WRITE_LINE) |  // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
                       (CurrState == STATE_FLUSH) |
                       (CurrState == STATE_FLUSH_WRITEBACK);
   // write enables internal to cache
@@ -181,6 +181,6 @@ module cachefsm
                   resetDelay;
 
   assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD;
-  assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset;
+  assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache;
                        
 endmodule // cachefsm
diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv
index 10bb4cfa0..8e9d12b18 100644
--- a/pipelined/src/cache/cacheway.sv
+++ b/pipelined/src/cache/cacheway.sv
@@ -152,7 +152,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
     if (reset) ValidBits        <= #1 '0;
     if(CacheEn) begin 
 	  ValidWay <= #1 ValidBits[CAdr];
-	  if(InvalidateCache & ~FlushStage)                    ValidBits <= #1 '0;
+	  if(InvalidateCache)                    ValidBits <= #1 '0;
       else if (SetValidEN | (ClearValidWay & ~FlushStage)) ValidBits[CAdr] <= #1 SetValidWay;
     end
   end