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https://github.com/openhwgroup/cvw
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Added adder input selection to on the fly converter
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@ -87,6 +87,7 @@ module srt (
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// Divisor Selection logic
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// Divisor Selection logic
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assign Db = ~D;
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assign Db = ~D;
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mux3onehot #(`DIVLEN) divisorsel(Db, {(`DIVLEN+4){1'b0}}, D, qp, qz, qm, Dsel);
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mux3onehot #(`DIVLEN) divisorsel(Db, {(`DIVLEN+4){1'b0}}, D, qp, qz, qm, Dsel);
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fsel2 fsel(qp, qn, )
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// Partial Product Generation
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// Partial Product Generation
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csa #(`DIVLEN+4) csa(WS, WC, Dsel, qp, WSA, WCA);
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csa #(`DIVLEN+4) csa(WS, WC, Dsel, qp, WSA, WCA);
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@ -95,7 +96,7 @@ module srt (
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otfc2 #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, Quot);
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otfc2 #(`DIVLEN) otfc2(clk, Start, qp, qz, qm, Quot);
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// otherwise use sotfc
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// otherwise use sotfc
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// creg sotfcC(clk, Start, C);
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// creg sotfcC(clk, Start, C);
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// sotfc2 #(`DIVLEN) sotfc2(clk, Start, qp, qn, C, Quot);
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// sotfc2 #(`DIVLEN) sotfc2(clk, Start, qp, qn, C, Quot, F);
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expcalc expcalc(.XExp, .YExp, .calcExp, .Sqrt);
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expcalc expcalc(.XExp, .YExp, .calcExp, .Sqrt);
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@ -263,6 +264,7 @@ module sotfc2(
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input logic sp, sn,
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input logic sp, sn,
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input logic [`DIVLEN+3:0] C,
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input logic [`DIVLEN+3:0] C,
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output logic [`DIVLEN-1:0] Sq,
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output logic [`DIVLEN-1:0] Sq,
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output logic [`DIVLEN+3:0] F,
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);
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);
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@ -288,6 +290,8 @@ module sotfc2(
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end
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end
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assign Sq = S[`DIVLEN-1:0];
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assign Sq = S[`DIVLEN-1:0];
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fsel2 fsel(sp, sn, C, S, SM, F);
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endmodule
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endmodule
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//////////////////////////
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//////////////////////////
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