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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
At least it simulates and gets through fpga elaboration.
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@ -80,6 +80,8 @@ set_property PACKAGE_PIN E2 [get_ports {SDCDat[1]}]
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set_property PACKAGE_PIN F4 [get_ports {SDCDat[0]}]
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set_property PACKAGE_PIN F4 [get_ports {SDCDat[0]}]
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set_property PACKAGE_PIN F3 [get_ports SDCCLK]
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set_property PACKAGE_PIN F3 [get_ports SDCCLK]
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set_property PACKAGE_PIN D3 [get_ports {SDCCmd}]
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set_property PACKAGE_PIN D3 [get_ports {SDCCmd}]
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set_property PACKAGE_PIN H2 [get_ports {SDCCD}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[2]}]
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@ -87,11 +89,13 @@ set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK]
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set_property IOSTANDARD LVCMOS33 [get_ports {SDCCmd}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SDCCmd}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SDCCD}]
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set_property PULLUP true [get_ports {SDCDat[3]}]
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set_property PULLUP true [get_ports {SDCDat[3]}]
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set_property PULLUP true [get_ports {SDCDat[2]}]
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set_property PULLUP true [get_ports {SDCDat[2]}]
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set_property PULLUP true [get_ports {SDCDat[1]}]
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set_property PULLUP true [get_ports {SDCDat[1]}]
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set_property PULLUP true [get_ports {SDCDat[0]}]
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set_property PULLUP true [get_ports {SDCDat[0]}]
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set_property PULLUP true [get_ports {SDCCmd}]
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set_property PULLUP true [get_ports {SDCCmd}]
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set_property PULLUP true [get_ports {SDCCD}]
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set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
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set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
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@ -21,7 +21,7 @@ all: FPGA_Arty
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# VCU 108 and VCU 118 boards
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# VCU 108 and VCU 118 boards
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#all: FPGA_VCU
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#all: FPGA_VCU
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FPGA_Arty: PreProcessFiles IP_Arty SDC
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FPGA_Arty: PreProcessFiles IP_Arty
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vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
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vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
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FPGA_VCU: PreProcessFiles IP_VCU SDC
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FPGA_VCU: PreProcessFiles IP_VCU SDC
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@ -40,15 +40,12 @@ IP_Arty: $(dst)/xlnx_proc_sys_reset.log \
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$(dst)/xlnx_ddr3-$(board).log \
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$(dst)/xlnx_ddr3-$(board).log \
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$(dst)/xlnx_mmcm.log \
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$(dst)/xlnx_mmcm.log \
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$(dst)/xlnx_axi_clock_converter.log \
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$(dst)/xlnx_axi_clock_converter.log \
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$(dst)/xlnx_ahblite_axi_bridge.log
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$(dst)/xlnx_ahblite_axi_bridge.log \
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$(dst)/xlnx_axi_crossbar.log \
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$(dst)/xlnx_axi_crossbar.log \
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$(dst)/xlnx_axi_dwidth_conv_32to64.log \
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$(dst)/xlnx_axi_dwidth_conv_32to64.log \
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$(dst)/xlnx_axi_dwidth_conv_64to32.log \
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$(dst)/xlnx_axi_dwidth_conv_64to32.log \
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$(dst)/xlnx_axi_prtcl_conv.log
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$(dst)/xlnx_axi_prtcl_conv.log
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SDC:
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cp $(sdc_src) ../src/
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tar xzf ../src/sdc.tar.gz -C ../src
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PreProcessFiles:
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PreProcessFiles:
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rm -rf ../src/CopiedFiles_do_not_add_to_repo/
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rm -rf ../src/CopiedFiles_do_not_add_to_repo/
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@ -35,9 +35,10 @@ module fpgaTop
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input UARTSin,
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input UARTSin,
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output UARTSout,
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output UARTSout,
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input [3:0] SDCDat,
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inout [3:0] SDCDat,
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output SDCCLK,
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output SDCCLK,
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inout SDCCmd,
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inout SDCCmd,
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input SDCCD,
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inout [15:0] ddr3_dq,
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inout [15:0] ddr3_dq,
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inout [1:0] ddr3_dqs_n,
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inout [1:0] ddr3_dqs_n,
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@ -999,7 +1000,7 @@ module fpgaTop
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.s_axi_rready(s00_axi_rready),
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.s_axi_rready(s00_axi_rready),
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.m_axi_aclk(BUSCLK),
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.m_axi_aclk(BUSCLK),
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.m_axi_aresetn(~reset),
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.m_axi_aresetn(resetn),
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.m_axi_awid(BUS_axi_awid),
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.m_axi_awid(BUS_axi_awid),
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.m_axi_awlen(BUS_axi_awlen),
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.m_axi_awlen(BUS_axi_awlen),
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.m_axi_awsize(BUS_axi_awsize),
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.m_axi_awsize(BUS_axi_awsize),
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@ -1040,9 +1041,6 @@ module fpgaTop
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.m_axi_rlast(BUS_axi_rlast),
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.m_axi_rlast(BUS_axi_rlast),
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.m_axi_rready(BUS_axi_rready));
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.m_axi_rready(BUS_axi_rready));
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assign CPUCLK = CLK208;
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xlnx_ddr3 xlnx_ddr3_c0
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xlnx_ddr3 xlnx_ddr3_c0
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(
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(
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// ddr3 I/O
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// ddr3 I/O
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@ -11,10 +11,10 @@ NAME="$GREEN"${0:2}"$NC"
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# File location variables
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# File location variables
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RISCV=/opt/riscv
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RISCV=/opt/riscv
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IMAGES=$RISCV/buildroot/output/images
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IMAGES=/home/ross/repos/buildroot/output/images/
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FW_JUMP=$IMAGES/fw_jump.bin
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FW_JUMP=$IMAGES/fw_jump.bin
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LINUX_KERNEL=$IMAGES/Image
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LINUX_KERNEL=$IMAGES/Image
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DEVICE_TREE=$IMAGES/wally-vcu108.dtb
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DEVICE_TREE=$IMAGES/wally-artya7.dtb
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# Mount Directory
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# Mount Directory
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MNT_DIR=wallyimg
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MNT_DIR=wallyimg
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@ -117,4 +117,4 @@ fi
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echo
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echo
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echo "GPT Information for $1 ==================================="
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echo "GPT Information for $1 ==================================="
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sgdisk -p $1
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sudo sgdisk -p $1
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