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Recreated coverage changes

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This commit is contained in:
David Harris 2024-09-05 16:32:45 -07:00
parent 712274af3d
commit 6e0b0487dd
6 changed files with 29 additions and 26 deletions
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10
bin/regression-wally
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@ -232,8 +232,8 @@ bpredtests = [
# list of tests not supported by ImperasDV yet that should be waived during lockstep testing
lockstepwaivers = [
"WALLY-q-01.S_ref.elf", # Q extension is not supported by ImperasDV
"WALLY-cbom-01.S_ref.elf", # cbom extension is not supported by ImperasDV because there is no cache model in ImperasDV
"coverage_ieu.elf" # Issue 881: ImperasDV misinterprets 0x6BF05013 as a grevi rather than an illegal instruction
"WALLY-cbom-01.S_ref.elf" #, # cbom extension is not supported by ImperasDV because there is no cache model in ImperasDV
# "coverage_ieu.elf" # Issue 881: ImperasDV misinterprets 0x6BF05013 as a grevi rather than an illegal instruction
]
##################################
@ -408,7 +408,8 @@ if (args.ccov): # only run RV64GC tests on Questa in code coverage mode
if (args.fp):
addTests(tests64gc_fp, coveragesim)
elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode
addLockstepTestsByDir(WALLY+"/tests/functcov/rv64/I", "rv64gc", coveragesim)
# addLockstepTestsByDir(WALLY+"/tests/functcov/rv64/I", "rv64gc", coveragesim)
addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/I", "rv32gc", coveragesim)
elif (args.fcovrvvi): # only run RV64GC tests on Questa in rvvi coverage mode
addTests(tests64gc_nofp, coveragesim)
if (args.fp):
@ -545,7 +546,8 @@ def main():
if args.ccov:
os.system('make QuestaCodeCoverage')
if args.fcov:
os.system('make QuestaFunctCoverage')
#os.system('make QuestaFunctCoverage')
os.system('make -f '+WALLY+'/addins/cvw-arch-verif/Makefile merge')
if args.fcovrvvi:
os.system('make QuestaFunctCoverageRvvi')
# Count the number of failures

16
bin/wsim
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@ -27,8 +27,8 @@ parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilat
parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
parser.add_argument("--ccov", "-c", help="Code Coverage", action="store_true")
parser.add_argument("--fcov", "-f", help="Functional Coverage, implies lockstep", action="store_true")
parser.add_argument("--fcov2", "-f2", help="Functional Coverage, implies lockstep", action="store_true")
parser.add_argument("--fcovimp", "-f2", help="Functional Coverage with Imperas licensed riscvISACOV, implies lockstep", action="store_true")
parser.add_argument("--fcov", "-f", help="Functional Coverage with cvw-arch-verif, implies lockstep", action="store_true")
parser.add_argument("--fcovrvvi", "-fr", help="Functional Coverage RVVI", action="store_true")
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
parser.add_argument("--params", "-p", help="Optional top-level parameter overrides of the form param=value", default="")
@ -68,7 +68,7 @@ if(args.testsuite.endswith('.elf') and args.elf == ""): # No --elf argument; che
# Validate arguments
if (args.gui or args.ccov or args.fcov or args.fcov2 or args.fcovrvvi or args.lockstep):
if (args.gui or args.ccov or args.fcov or args.fcovimp or args.fcovrvvi or args.lockstep):
if args.sim not in ["questa", "vcs"]:
print("Option only supported for Questa and VCS")
exit(1)
@ -85,7 +85,7 @@ if (args.tb == "testbench_fp"):
# if lockstep is enabled, then we need to pass the Imperas lockstep arguments
if(int(args.locksteplog) >= 1): EnableLog = 1
else: EnableLog = 0
if((args.lockstep or args.fcov or args.fcov2) and args.sim == "questa"):
if((args.lockstep or args.fcov or args.fcovimp) and args.sim == "questa"):
prefix = "IMPERAS_TOOLS=" + WALLY + "/config/"+args.config+"/imperas.ic"
prefix = "MTI_VCO_MODE=64 " + prefix
else:
@ -94,13 +94,13 @@ else:
if (args.lockstep):
if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog)
else: ImperasPlusArgs = ""
if(args.fcov):
if(args.fcovimp):
CovEnableStr = "1" if int(args.covlog) > 0 else "0"
if(args.covlog >= 1): EnableLog = 1
else: EnableLog = 0
ImperasPlusArgs = " +IDV_TRACE2COV=" + str(EnableLog) + " +TRACE2LOG_AFTER=" + str(args.covlog) + " +TRACE2COV_ENABLE=" + CovEnableStr
suffix = ""
if(args.fcov2):
if(args.fcov):
CovEnableStr = "1" if int(args.covlog) > 0 else "0";
if(args.covlog >= 1): EnableLog = 1
else: EnableLog = 0
@ -121,8 +121,8 @@ if (args.ccov):
flags += " --ccov"
if (args.fcov):
flags += " --fcov"
if (args.fcov2):
flags += " --fcov2"
if (args.fcovimp):
flags += " --fcovimp"
if (args.fcovrvvi):
flags += "--fcovrvvi"

6
config/rv32gc/imperas.ic
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@ -111,9 +111,9 @@
# Add Imperas simulator application instruction tracing
# uncomment these to provide tracing
--verbose --trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange # --traceafter 300000000
--override cpu/debugflags=6 --override cpu/verbose=1
--override cpu/show_c_prefix=T
#--verbose --trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange # --traceafter 300000000
#--override cpu/debugflags=6 --override cpu/verbose=1
#--override cpu/show_c_prefix=T
# Store simulator output to logfile
--output imperas.log

15
sim/questa/wally.do
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@ -115,8 +115,8 @@ if {[lcheck lst "--fcovrvvi"]} {
set FCdefineRVVI_COVERAGE "+define+RVVI_COVERAGE"
}
# if --fcov found set flag and remove from list
if {[lcheck lst "--fcov"]} {
# if --fcovimp found set flag and remove from list
if {[lcheck lst "--fcovimp"]} {
set FunctCoverage 1
set FCvlog "+define+INCLUDE_TRACE2COV \
+define+IDV_INCLUDE_TRACE2COV \
@ -135,15 +135,17 @@ if {[lcheck lst "--fcov"]} {
}
# if --fcov2 found set flag and remove from list
if {[lcheck lst "--fcov2"]} {
# if --fcov found set flag and remove from list
if {[lcheck lst "--fcov"]} {
set FunctCoverage 1
set FCvlog "+define+INCLUDE_TRACE2COV \
+define+IDV_INCLUDE_TRACE2COV \
+define+COVER_BASE_RV32I \
+define+COVER_LEVEL_DV_PR_EXT \
+incdir+$env(WALLY)/addins/riscvISACOV/source \
+incdir+$env(WALLY)/addins/cvw-arch-verif/fcov/RV32"
"
# +incdir+$env(WALLY)/addins/cvw-arch-verif/fcov/rv32 \
set FCvopt "+TRACE2COV_ENABLE=1 +IDV_TRACE2COV=1"
# Uncomment various cover statements below to control which extensions get functional coverage
lappend FCdefineCOVER_EXTS "+define+COVER_RV32I"
@ -165,7 +167,6 @@ if {[lcheck lst "--lockstep"] || $FunctCoverage == 1} {
${IMPERAS_HOME}/ImpPublic/source/host/rvvi/*.sv \
${IMPERAS_HOME}/ImpProprietary/source/host/idv/*.sv"
set SVLib "-sv_lib ${IMPERAS_HOME}/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model"
#set OtherFlags $::env(OTHERFLAGS) # not working 7/15/24 dh; this should be the way to pass things like --verbose (Issue 871)
}
# Set PlusArgs passed using the --args flag
@ -202,7 +203,7 @@ if {$DEBUG > 0} {
# suppress spurious warnngs about
# "Extra checking for conflicts with always_comb done at vopt time"
# because vsim will run vopt
set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI}/common +incdir+${FCRVVI}"
set INC_DIRS "+incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared +incdir+${FCRVVI} +incdir+${FCRVVI}/rv32 +incdir+${FCRVVI}/common +incdir+${FCRVVI}"
set SOURCES "${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv"
vlog -lint +nowarnRDGN -work ${WKDIR} {*}${INC_DIRS} {*}${FCvlog} {*}${FCdefineCOVER_EXTS} {*}${lockstepvlog} ${FCdefineRVVI_COVERAGE} {*}${SOURCES} -suppress 2244 -suppress 2282 -suppress 2583 -suppress 7063,2596,13286

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/README.md
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@ -8,7 +8,7 @@ This folder consists of all the required files and tools to generate Q tests for
NOTE : Only some of the IBM tests are currently supporting Quad testing.
Tests which are working : ibm1, ibm9,ibm21,ibm23,ibm24,ibm25,ibm26,ibm27,ibm28,ibm29
Tests which are implemented in riscv-isac/riscv_isac/fp_dataset.py : ibm1, ibm9,ibm21,ibm23,ibm24,ibm25,ibm26,ibm27,ibm28,ibm29
These ibm tests can be included in the riscv-ctg tests generation command, along with riscof.
The tests which are currently breaking due to overflow errors are : ibm2,ibm3,ibm4,ibm5,ibm6,ibm7,ibm8,ibm10,ibm11,ibm12,ibm13,ibm14,ibm15,ibm16,ibm17,ibm18,ibm19,ibm20,ibm22
@ -26,7 +26,7 @@ TO DO:
Debug why fadd.q_b1 doesn't match Sail vs. Spike
Run the q test on Wally RTL
Make more tests from the working datasets
Get other datasets working by using softfloat to do quad math
Get other fp_dataset.py datasets working by using softfloat to do quad math
Push changes back to riscv-ctg and riscv-isac and remove them from wally-riscv-arch/tsts/riscv-test-suite/rv64i_m/Q

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/riscv-isac/riscv_isac/fp_dataset.py
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@ -393,7 +393,7 @@ def ibm_b1(flen, iflen, opcode, ops):
qinfinity + qdefaultnan + [qqnan[0], qqnan[1]] + \
[qsnan[0], qsnan[1]] + qone
else:
logger.error('Invalid iflen value!')
logger.error('Invalid iflen value is ' + iflen)
sys.exit(1)
# the following creates a cross product for ops number of variables
@ -4073,7 +4073,7 @@ def ibm_b21(flen, iflen, opcode, ops):
qinfinity + qdefaultnan + [qqnan[0], qqnan[1]] + \
[qsnan[0], qsnan[1]]
else:
logger.error('Invalid iflen value!')
logger.error('Invalid iflen value 2 ' + iflen)
sys.exit(1)
# the following creates a cross product for ops number of variables