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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Ross Thompson 2022-11-22 18:07:32 -06:00
commit 6dd5668d21
4 changed files with 22 additions and 24 deletions
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2
pipelined/regression/wave-fpu.do
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@ -8,7 +8,7 @@ add wave -noupdate /testbenchfp/Z
add wave -noupdate /testbenchfp/Res add wave -noupdate /testbenchfp/Res
add wave -noupdate /testbenchfp/Ans add wave -noupdate /testbenchfp/Ans
add wave -noupdate /testbenchfp/DivStart add wave -noupdate /testbenchfp/DivStart
add wave -noupdate /testbenchfp/DivBusy add wave -noupdate /testbenchfp/FDivBusyE
add wave -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtfsm/state add wave -noupdate /testbenchfp/fdivsqrt/fdivsqrt/fdivsqrtfsm/state
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/* add wave -group {PostProc} -noupdate /testbenchfp/postprocess/*
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/* add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/*

2
pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
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@ -85,7 +85,7 @@ module fdivsqrt(
.FDivBusyE); .FDivBusyE);
fdivsqrtpostproc fdivsqrtpostproc( fdivsqrtpostproc fdivsqrtpostproc(
.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun,
.SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]), .SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]), .ForwardedSrcAE,
.MDUE, .n, .ALTB, .m, .BZero, .As, .MDUE, .n, .ALTB, .m, .BZero, .As,
.QmM, .WZero, .DivSM); .QmM, .WZero, .DivSM);
endmodule endmodule

22
pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -38,6 +38,7 @@ module fdivsqrtpostproc(
input logic Firstun, input logic Firstun,
input logic SqrtM, input logic SqrtM,
input logic SpecialCaseM, input logic SpecialCaseM,
input logic [`XLEN-1:0] ForwardedSrcAE,
input logic RemOp, MDUE, ALTB, BZero, As, input logic RemOp, MDUE, ALTB, BZero, As,
input logic [`DIVBLEN:0] n, m, input logic [`DIVBLEN:0] n, m,
output logic [`DIVb:0] QmM, output logic [`DIVb:0] QmM,
@ -52,7 +53,7 @@ module fdivsqrtpostproc(
logic [`DIVBLEN:0] NormShift; logic [`DIVBLEN:0] NormShift;
logic [`DIVb:0] IntQuot, NormQuot; logic [`DIVb:0] IntQuot, NormQuot;
logic [`DIVb+3:0] IntRem, NormRem; logic [`DIVb+3:0] IntRem, NormRem;
logic [`DIVb:0] PreResult, Result; logic [`DIVb+3:0] PreResult, Result;
// check for early termination on an exact result. If the result is not exact, the sticky should be set // check for early termination on an exact result. If the result is not exact, the sticky should be set
aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0); aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0);
@ -101,15 +102,14 @@ module fdivsqrtpostproc(
PostInc = 1; PostInc = 1;
end end
/*
always_comb always_comb
if(ALTB) begin if(ALTB) begin
IntQuot = '0; IntQuot = '0;
IntRem = ForwardedSrcAE; IntRem = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAE};
end else if (BZero) begin end else if (BZero) begin
IntQuot = '1; IntQuot = '1;
IntRem = ForwardedSrcAE; IntRem = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAE};
end else if (EarlyTerm) begin end else if (WZero) begin
if (weq0) begin if (weq0) begin
IntQuot = FirstU; IntQuot = FirstU;
IntRem = '0; IntRem = '0;
@ -121,22 +121,20 @@ module fdivsqrtpostproc(
IntQuot = NormQuot; IntQuot = NormQuot;
IntRem = NormRem; IntRem = NormRem;
end end
*/
/*
always_comb always_comb
if (RemOp) begin if (RemOp) begin
NormShift = m + (`DIVBLEN)'(`DIVa); NormShift = (m + (`DIVBLEN)'(`DIVa));
PreResult = IntRem; PreResult = IntRem;
end else begin end else begin
NormShift = DIVb - (j << `LOGR); NormShift = ((`DIVBLEN)'(`DIVb) - (n << `LOGR));
PreResult = IntQuot; PreResult = {3'b000, IntQuot};
end end
*/
// division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
// assign Result = ($signed(PreResult) >>> NormShift) + (PostInc & ~RemOp); assign Result = ($signed(PreResult) >>> NormShift) + {{(`DIVb+3){1'b0}}, (PostInc & ~RemOp)};
assign PreQmM = NegSticky ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit assign PreQmM = NegSticky ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit
assign QmM = SqrtM ? (PreQmM << 1) : PreQmM; assign QmM = SqrtM ? (PreQmM << 1) : PreQmM;

12
pipelined/testbench/testbench-fp.sv
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@ -82,7 +82,7 @@ module testbenchfp;
logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
logic [`DIVb:0] Quot; logic [`DIVb:0] Quot;
logic CvtResDenormUfE; logic CvtResDenormUfE;
logic DivStart, DivBusy; logic DivStart, FDivBusyE;
logic reset = 1'b0; logic reset = 1'b0;
logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt; logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
logic [`DURLEN-1:0] Dur; logic [`DURLEN-1:0] Dur;
@ -717,9 +717,9 @@ module testbenchfp;
end end
if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt
fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]), fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
.XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .DivStartE(DivStart), .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN),
.MDUE(1'b0), .W64E(1'b0), .FDivStartE(DivStart), .IDivStartE(1'b0), .MDUE(1'b0), .W64E(1'b0),
.StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .DivBusy, .QeM(DivCalcExp), .StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .FDivBusyE, .QeM(DivCalcExp),
.QmM(Quot), .DivDone); .QmM(Quot), .DivDone);
end end
@ -879,7 +879,7 @@ always @(negedge clk) begin
// check if result is correct // check if result is correct
// - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) // - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
// if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&~((DivBusy===1'b1)|DivStart)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin // if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&~((FDivBusyE===1'b1)|DivStart)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin
ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx); ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx);
FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx); FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx);
divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL; divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL;
@ -911,7 +911,7 @@ always @(negedge clk) begin
$stop; $stop;
end end
if(~(DivBusy|DivStart)|(UnitVal != `DIVUNIT)) VectorNum += 1; // increment the vector if(~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) VectorNum += 1; // increment the vector
if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the end of file if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the end of file