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Possible workign instruction class prediction repair.

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This commit is contained in:
Ross Thompson 2023-01-28 16:42:19 -06:00
parent 8a277f6b75
commit 6d9c463893
1 changed files with 11 additions and 13 deletions
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24
pipelined/src/ifu/brpred/speculativegshare.sv
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@ -52,7 +52,7 @@ module speculativegshare
logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE; logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE;
logic [k-1:0] GHRF, OldGHRF; logic [k-1:0] GHRF, OldGHRF;
logic OldGHRExtraF; logic GHRExtraF;
logic [k-1:0] GHRD, OldGHRE, GHRE, GHRM, GHRW; logic [k-1:0] GHRD, OldGHRE, GHRE, GHRM, GHRW;
logic [k-1:0] GHRNextF; logic [k-1:0] GHRNextF;
logic [k-1:0] GHRNextD; logic [k-1:0] GHRNextD;
@ -113,30 +113,28 @@ module speculativegshare
always_comb begin always_comb begin
if(FlushD) begin if(FlushD) begin
//if(BranchInstrE) GHRNextF = {PCSrcE, GHRNextD[k-1:1]};
//else GHRNextF = GHRNextD[k-1:0];
GHRNextF = GHRNextD[k-1:0]; GHRNextF = GHRNextD[k-1:0];
end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]}; end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]};
else GHRNextF = GHRF; else GHRNextF = GHRF;
end end
flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF); flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
//flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, OldGHRF); flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRF[0], GHRExtraF);
//flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRNextF[0], OldGHRExtraF);
// assign GHRF = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRF[k-1:1]} : // shift right // use with out instruction class prediction
// WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], OldGHRExtraF}: // shift left //assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0];
// OldGHRF[k-1:0]; // with instruction class prediction
assign GHRNextD = FlushD ? GHRNextE[k-1:0] :
//assign GHRNextD = FlushD ? {GHRNextE} : {DirPredictionF[1], GHRF[k-1:1]}; WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right
assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0]; WrongPredInstrClassD[0] & ~BranchInstrD ? {OldGHRF[k-2:0], GHRExtraF}: // shift left
GHRF[k-1:0];
flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD); flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
assign GHRNextE = DirPredictionWrongE & BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} : // if the branch is not flushed and was mispredicted assign GHRNextE = BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} : // if the branch is not flushed
FlushE ? GHRNextM : // branch is flushed FlushE ? GHRNextM : // branch is flushed
GHRD; GHRD;
flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE); flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE);
//assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
assign GHRNextM = FlushM ? GHRNextW : GHRE; assign GHRNextM = FlushM ? GHRNextW : GHRE;
flopenr #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM); flopenr #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);