Name cleanup.

pipelined/src/cache/cache.sv

@@ -41,7 +41,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, DCACHE = 1) (
   input logic                 InvalidateCacheM,
   input logic [11:0]          NextAdr, // virtual address, but we only use the lower 12 bits.
   input logic [`PA_BITS-1:0]  PAdr, // physical address
-  input logic [(`XLEN-1)/8:0] ByteWe,
+  input logic [(`XLEN-1)/8:0] ByteMask,
   input logic [`XLEN-1:0]     FinalWriteData,
   output logic                CacheCommitted,
   output logic                CacheStall,
@@ -115,7 +115,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, DCACHE = 1) (
 
   // Array of cache ways, along with victim, hit, dirty, and read merging logic
   cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0](
-    .clk, .reset, .RAdr, .PAdr, .CacheWriteData, .ByteWe,
+    .clk, .reset, .RAdr, .PAdr, .CacheWriteData, .ByteMask,
     .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay,
     .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, 
     .Invalidate(InvalidateCacheM));

pipelined/src/cache/cacheway.sv

@@ -47,7 +47,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   input logic                        VictimWay,
   input logic                        FlushWay,
   input logic                        Invalidate,
-  input logic [(`XLEN-1)/8:0]        ByteWe,
+  input logic [(`XLEN-1)/8:0]        ByteMask,
 
   output logic [LINELEN-1:0]         ReadDataLineWay,
   output logic                       HitWay,
@@ -69,7 +69,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   logic [$clog2(NUMLINES)-1:0]       RAdrD;
   logic [2**LOGWPL-1:0]              MemPAdrDecoded;
   logic [LINELEN/`XLEN-1:0]          SelectedWriteWordEn;
-  logic [(`XLEN-1)/8:0]              FinalByteWe;
+  logic [(`XLEN-1)/8:0]              FinalByteMask;
   
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Write Enable demux
@@ -78,14 +78,14 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
     .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded));
   // If writing the whole line set all write enables to 1, else only set the correct word.
   assign SelectedWriteWordEn = SetValidWay ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND
-  assign FinalByteWe = SetValidWay ? '1 : ByteWe; // OR
+  assign FinalByteMask = SetValidWay ? '1 : ByteMask; // OR
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Tag Array
   /////////////////////////////////////////////////////////////////////////////////////////////
 
   sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk,
-    .Adr(RAdr), .ReadData(ReadTag), .ByteWe('1),
+    .Adr(RAdr), .ReadData(ReadTag), .ByteMask('1),
     .CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(SetValidWay));
 
   // AND portion of distributed tag multiplexer
@@ -104,7 +104,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
     sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk, .Adr(RAdr),
       .ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ),
       .CacheWriteData(CacheWriteData[(words+1)*`XLEN-1:words*`XLEN]),
-      .WriteEnable(SelectedWriteWordEn[words]), .ByteWe(FinalByteWe));
+      .WriteEnable(SelectedWriteWordEn[words]), .ByteMask(FinalByteMask));
   end
 
   // AND portion of distributed read multiplexers

pipelined/src/cache/sram1p1rw.sv

@@ -38,7 +38,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
   input logic [$clog2(DEPTH)-1:0] Adr,
   input logic [WIDTH-1:0]         CacheWriteData,
   input logic                     WriteEnable,
-  input logic [(WIDTH-1)/8:0]     ByteWe,
+  input logic [(WIDTH-1)/8:0]     ByteMask,
   output logic [WIDTH-1:0]        ReadData);
 
   logic [WIDTH-1:0]               StoredData[DEPTH-1:0];
@@ -50,7 +50,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
   genvar                          index;
   for(index = 0; index < WIDTH/8; index++) begin
     always_ff @(posedge clk) begin
-      if (WriteEnable & ByteWe[index]) begin
+      if (WriteEnable & ByteMask[index]) begin
         StoredData[Adr][8*(index+1)-1:8*index] <= #1 CacheWriteData[8*(index+1)-1:8*index];
       end
     end
@@ -58,7 +58,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
   // if not a multiple of 8, MSByte is not 8 bits long.
   if(WIDTH%8 != 0) begin
     always_ff @(posedge clk) begin
-      if (WriteEnable & ByteWe[WIDTH/8]) begin
+      if (WriteEnable & ByteMask[WIDTH/8]) begin
         StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1 CacheWriteData[WIDTH-1:WIDTH-WIDTH%8];
       end
     end

pipelined/src/generic/flop/simpleram.sv

@@ -34,7 +34,7 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
   input  logic             clk, 
   input  logic [31:0]      a,
   input  logic             we,
-  input  logic [`XLEN/8-1:0] ByteWe,
+  input  logic [`XLEN/8-1:0] ByteMask,
   input  logic [`XLEN-1:0] wd,
   output logic [`XLEN-1:0] rd
 );
@@ -52,7 +52,7 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
   genvar            index;
   for(index = 0; index < `XLEN/8; index++) begin
     always_ff @(posedge clk) begin
-      if (we & ByteWe[index]) RAM[adrmsbs][8*(index+1)-1:8*index] <= #1 wd[8*(index+1)-1:8*index];
+      if (we & ByteMask[index]) RAM[adrmsbs][8*(index+1)-1:8*index] <= #1 wd[8*(index+1)-1:8*index];
     end
   end
 endmodule

pipelined/src/ifu/ifu.sv

@@ -175,7 +175,7 @@ module ifu (
   
   if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name.  Probably use a ROM rather than DTIM
     dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill),
-              .TrapM(1'b0), .FinalWriteDataM(), .ByteWeM('0),
+              .TrapM(1'b0), .FinalWriteDataM(), .ByteMaskM('0),
               .ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead),
               .BusCommittedM(), .ReadDataWordMuxM(), .DCacheStallM(ICacheStallF), 
               .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess));
@@ -220,7 +220,7 @@ module ifu (
              .CacheWriteLine(), .ReadDataLine(ReadDataLine),
              .save, .restore, .Cacheable(CacheableF),
              .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
-             .ByteWe('0),
+             .ByteMask('0),
              .FinalWriteData('0),
              .RW(2'b10), 
              .Atomic('0), .FlushCache('0),

pipelined/src/lsu/dtim.sv

@@ -37,7 +37,7 @@ module dtim(
   input logic [`XLEN-1:0]     IEUAdrE,
   input logic                 TrapM, 
   input logic [`XLEN-1:0]     FinalWriteDataM,
-  input logic [`XLEN/8-1:0]   ByteWeM,
+  input logic [`XLEN/8-1:0]   ByteMaskM,
   output logic [`XLEN-1:0]    ReadDataWordM,
   output logic                BusStall,
   output logic                LSUBusWrite,
@@ -50,7 +50,7 @@ module dtim(
   output logic                DCacheAccess);
 
   simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
-      .clk, .ByteWe(ByteWeM),
+      .clk, .ByteMask(ByteMaskM),
       .a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), // move mux out; this shouldn't be needed when stails are handled differently ***
       .we(LSURWM[0] & ~TrapM),  // have to ignore write if Trap.
       .wd(FinalWriteDataM), .rd(ReadDataWordM));

pipelined/src/lsu/lsu.sv

@@ -105,7 +105,7 @@ module lsu (
   logic                     LSUBusWriteCrit;
   logic                     DataDAPageFaultM;
   logic [`XLEN-1:0]         LSUWriteDataM;
-  logic [(`XLEN-1)/8:0]     ByteWeM;
+  logic [(`XLEN-1)/8:0]     ByteMaskM;
   
   // *** TO DO: Burst mode, byte write enables to DTIM, cache, exeternal memory, remove subword write from uncore, 
 
@@ -194,7 +194,7 @@ module lsu (
     // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops
     dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, 
               .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM,
-              .ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, .ByteWeM,
+              .ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, .ByteMaskM,
               .DCacheMiss, .DCacheAccess);
     assign SelUncachedAdr = '0; // value does not matter.
   end else begin : bus  
@@ -235,7 +235,7 @@ module lsu (
               .NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1)) dcache(
         .clk, .reset, .CPUBusy, .save, .restore, .RW(LSURWM), .Atomic(LSUAtomicM),
         .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), 
-        .ByteWe(ByteWeM),
+        .ByteMask(ByteMaskM),
         .FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM),
         .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
         .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheCommitted(DCacheCommittedM), 
@@ -253,10 +253,6 @@ module lsu (
     end
   end
 
-  subwordwrite subwordwrite(.HADDRD(LSUPAdrM[2:0]),
-    .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}),
-    .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM), .ByteWeM);
-
   subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]),
 		.Funct3M(LSUFunct3M), .ReadDataM);
 
@@ -272,4 +268,10 @@ module lsu (
   end else begin:lrsc
     assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = LSUWriteDataM;
   end
+
+  subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]),
+    .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}),
+    .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM), .ByteMaskM);
+
+  
 endmodule

pipelined/src/lsu/subwordwrite.sv

@@ -31,18 +31,16 @@
 `include "wally-config.vh"
 
 module subwordwrite (
-  input logic [2:0]          HADDRD,
+  input logic [2:0]          LSUPAdrM,
   input logic [3:0]          HSIZED,
   input logic [`XLEN-1:0]    HWDATAIN,
   output logic [`XLEN-1:0]   HWDATA,
-  output logic [`XLEN/8-1:0] ByteWeM
+  output logic [`XLEN/8-1:0] ByteMaskM
                      );
                   
   logic [`XLEN-1:0]          WriteDataSubwordDuplicated;
-  logic [(`XLEN/8)-1:0]      ByteMaskM;
 
-  swbytemask swbytemask(.HSIZED, .HADDRD, .ByteMask(ByteMaskM));
+  swbytemask swbytemask(.HSIZED, .HADDRD(LSUPAdrM), .ByteMask(ByteMaskM));
-  assign ByteWeM = ByteMaskM;  
   
   if (`XLEN == 64) begin:sww
     // Handle subword writes