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cleaning up FSM

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This commit is contained in:
David Harris 2021-07-17 04:26:41 -04:00
parent 26cd57aae0
commit 6d8a6eeba0
1 changed files with 12 additions and 45 deletions
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49
wally-pipelined/src/mmu/pagetablewalker.sv
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@ -229,8 +229,6 @@ module pagetablewalker
WalkerLoadPageFaultM = 1'b0; WalkerLoadPageFaultM = 1'b0;
WalkerStorePageFaultM = 1'b0; WalkerStorePageFaultM = 1'b0;
// SelPTW = 1'b1;
case (WalkerState) case (WalkerState)
IDLE: if (AnyTLBMissM & SvMode == `SV32) NextWalkerState = LEVEL1_SET_ADRE; IDLE: if (AnyTLBMissM & SvMode == `SV32) NextWalkerState = LEVEL1_SET_ADRE;
else NextWalkerState = IDLE; else NextWalkerState = IDLE;
@ -251,33 +249,19 @@ module pagetablewalker
HPTWRead = 1'b1; HPTWRead = 1'b1;
end else NextWalkerState = FAULT; end else NextWalkerState = FAULT;
end end
LEVEL0_SET_ADRE: NextWalkerState = LEVEL0_WDV;
LEVEL0_SET_ADRE: begin
NextWalkerState = LEVEL0_WDV;
//TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
end
LEVEL0_WDV: begin LEVEL0_WDV: begin
//TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
HPTWRead = 1'b1; HPTWRead = 1'b1;
if (HPTWStall) begin if (HPTWStall) NextWalkerState = LEVEL0_WDV;
NextWalkerState = LEVEL0_WDV; else begin
end else begin
NextWalkerState = LEVEL0; NextWalkerState = LEVEL0;
PRegEn = 1'b1; PRegEn = 1'b1;
end end
end end
LEVEL0: begin LEVEL0: if (ValidPTE & LeafPTE & ~ADPageFault) NextWalkerState = LEAF;
if (ValidPTE & LeafPTE & ~ADPageFault) begin else NextWalkerState = FAULT;
NextWalkerState = LEAF; LEAF: begin // *** pull out datapath stuff
//TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
end else begin
NextWalkerState = FAULT;
end
end
LEAF: begin
NextWalkerState = IDLE; NextWalkerState = IDLE;
PageTableEntry = CurrentPTE; PageTableEntry = CurrentPTE;
PageType = (PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux? PageType = (PreviousWalkerState == LEVEL1) ? 2'b01 : 2'b00; // *** not sure about this mux?
@ -287,7 +271,6 @@ module pagetablewalker
end end
FAULT: begin FAULT: begin
//SelPTW = 1'b0;
NextWalkerState = IDLE; NextWalkerState = IDLE;
WalkerInstrPageFaultF = ~DTLBMissMQ; WalkerInstrPageFaultF = ~DTLBMissMQ;
WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore; WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
@ -309,13 +292,6 @@ module pagetablewalker
assign HPTWPAdrE = TranslationPAdr[31:0]; assign HPTWPAdrE = TranslationPAdr[31:0];
end else begin end else begin
/* logic [8:0] VPN3, VPN2, VPN1, VPN0;
assign VPN3 = TranslationVAdr[47:39];
assign VPN2 = TranslationVAdr[38:30];
assign VPN1 = TranslationVAdr[29:21];
assign VPN0 = TranslationVAdr[20:12];*/
logic TerapageMisaligned, GigapageMisaligned; logic TerapageMisaligned, GigapageMisaligned;
// A terapage is a level 3 leaf page. This page must have zero PPN[2], // A terapage is a level 3 leaf page. This page must have zero PPN[2],
// zero PPN[1], and zero PPN[0] // zero PPN[1], and zero PPN[0]
@ -328,7 +304,6 @@ module pagetablewalker
always_comb begin always_comb begin
PRegEn = 1'b0; PRegEn = 1'b0;
//TranslationPAdr = '0;
HPTWRead = 1'b0; HPTWRead = 1'b0;
PageTableEntry = '0; PageTableEntry = '0;
PageType = '0; PageType = '0;
@ -340,16 +315,8 @@ module pagetablewalker
WalkerStorePageFaultM = 1'b0; WalkerStorePageFaultM = 1'b0;
case (WalkerState) case (WalkerState)
IDLE: begin IDLE: if (AnyTLBMissM) NextWalkerState = (SvMode == `SV48) ? LEVEL3_SET_ADRE : LEVEL2_SET_ADRE;
//SelPTW = 1'b0; else NextWalkerState = IDLE;
if (AnyTLBMissM & SvMode == `SV48) begin
NextWalkerState = LEVEL3_SET_ADRE;
end else if (AnyTLBMissM & SvMode == `SV39) begin
NextWalkerState = LEVEL2_SET_ADRE;
end else begin
NextWalkerState = IDLE;
end
end
LEVEL3_SET_ADRE: begin LEVEL3_SET_ADRE: begin
NextWalkerState = LEVEL3_WDV; NextWalkerState = LEVEL3_WDV;